From: Zeyu Fan <zeyu....@amd.com>
Signed-off-by: Zeyu Fan <zeyu....@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
---
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c | 152 +++++++++++----------
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h | 102 +++++++++++---
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 3 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h | 3 +-
drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h | 83 +++++++----
.../amd/dal/dc/virtual/virtual_stream_encoder.c | 3 +-
6 files changed, 223 insertions(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index e0654793e6b7..98925f9278db 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -71,6 +71,31 @@ static void dce110_update_generic_info_packet(
const struct encoder_info_packet *info_packet)
{
uint32_t regval;
+ /* TODOFPGA Figure out a proper number for max_retries polling for lock
+ * use 50 for now.
+ */
+ uint32_t max_retries = 50;
+
+ if (REG(AFMT_VBI_PACKET_CONTROL1)) {
+ if (packet_index >= 8)
+ ASSERT(0);
+
+ /* poll dig_update_lock is not locked -> asic internal signal
+ * assume otg master lock will unlock it
+ */
+ REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
+ 1, 10, max_retries);
+
+ /* check if HW reading GSP memory */
+ REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
+ 1, 10, max_retries);
+
+ /* HW does is not reading GSP memory not reading too long ->
+ * something wrong. clear GPS memory access and notify?
+ * hw SW is writing to GSP memory
+ */
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR,
1);
+ }
/* choose which generic packet to use */
{
regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
@@ -105,15 +130,11 @@ static void dce110_update_generic_info_packet(
REG_WRITE(AFMT_GENERIC_7, 0);
}
- /* force double-buffered packet update */
- if (enc110->se_mask->AFMT_GENERIC0_UPDATE &&
- enc110->se_mask->AFMT_GENERIC2_UPDATE) {
+ if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
+ /* force double-buffered packet update */
REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
AFMT_GENERIC0_UPDATE, (packet_index == 0),
AFMT_GENERIC2_UPDATE, (packet_index == 2));
- } else {
- ASSERT(enc110->se_mask->AFMT_GENERIC0_UPDATE);
- ASSERT(enc110->se_mask->AFMT_GENERIC2_UPDATE);
}
}
@@ -160,15 +181,15 @@ static void dce110_update_hdmi_info_packet(
break;
case 2:
REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
- HDMI_GENERIC2_CONT, cont,
- HDMI_GENERIC2_SEND, send,
- HDMI_GENERIC2_LINE, line);
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
break;
case 3:
REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
- HDMI_GENERIC3_CONT, cont,
- HDMI_GENERIC3_SEND, send,
- HDMI_GENERIC3_LINE, line);
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
break;
default:
/* invalid HW packet index */
@@ -183,10 +204,20 @@ static void dce110_update_hdmi_info_packet(
/* setup stream encoder in dp mode */
static void dce110_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
- struct dc_crtc_timing *crtc_timing)
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space)
{
+ uint32_t h_active_start;
+ uint32_t v_active_start;
+ uint32_t misc0;
+ uint32_t misc1;
+ uint32_t h_blank;
+ uint32_t h_back_porch;
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
+ /* for bring up, disable dp double TODO */
+ REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
+
/* set pixel encoding */
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
@@ -219,39 +250,46 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
}
+ misc1 = REG_READ(DP_MSA_MISC);
/* set color depth */
switch (crtc_timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+ 0);
+ misc0 = 0;
+ break;
case COLOR_DEPTH_888:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_8BPC);
+ misc0 = 1;
break;
case COLOR_DEPTH_101010:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_10BPC);
+
+ misc0 = 2;
break;
case COLOR_DEPTH_121212:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_12BPC);
+ misc0 = 3;
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_6BPC);
+ misc0 = 0;
break;
}
/* set dynamic range and YCbCr range */
- if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) {
+ if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
REG_UPDATE_2(
- DP_PIXEL_FORMAT,
- DP_DYN_RANGE, 0,
- DP_YCBCR_RANGE, 0);
- } else {
- ASSERT(enc110->se_mask->DP_DYN_RANGE);
- ASSERT(enc110->se_mask->DP_YCBCR_RANGE);
- }
-}
+ DP_PIXEL_FORMAT,
+ DP_DYN_RANGE, 0,
+ DP_YCBCR_RANGE, 0);
+}
static void dce110_stream_encoder_set_stream_attribute_helper(
struct dce110_stream_encoder *enc110,
@@ -403,7 +441,7 @@ static void dce110_stream_encoder_set_mst_bandwidth(
/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
/* is reset to 0 (not pending) */
REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
- enc110->se_mask->DP_MSE_RATE_UPDATE_PENDING,
+ 1,
10, DP_MST_UPDATE_MAX_RETRY);
}
@@ -443,15 +481,15 @@ static void
dce110_stream_encoder_update_hdmi_info_packets(
HDMI_AVI_INFO_SEND, 0,
HDMI_AVI_INFO_CONT, 0);
}
- } else {
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_SEND);
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_CONT);
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_LINE);
}
- dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
- dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
- dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
+ if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
+ enc110->se_mask->HDMI_AVI_INFO_SEND) {
+ dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
+ dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
+ dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
+ }
+
}
static void dce110_stream_encoder_stop_hdmi_info_packets(
@@ -470,24 +508,13 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
/* stop generic packets 2 & 3 on HDMI */
REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
- HDMI_GENERIC2_CONT, 0,
- HDMI_GENERIC2_LINE, 0,
- HDMI_GENERIC2_SEND, 0,
- HDMI_GENERIC3_CONT, 0,
- HDMI_GENERIC3_LINE, 0,
- HDMI_GENERIC3_SEND, 0);
-
- /* stop AVI packet on HDMI */
- if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
- enc110->se_mask->HDMI_AVI_INFO_SEND) {
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0);
- REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
- HDMI_AVI_INFO_SEND, 0,
- HDMI_AVI_INFO_CONT, 0);
- } else {
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_SEND);
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_CONT);
- }
}
static void dce110_stream_encoder_update_dp_info_packets(
@@ -500,14 +527,14 @@ static void dce110_stream_encoder_update_dp_info_packets(
if (info_frame->vsc.valid)
dce110_update_generic_info_packet(
enc110,
- 0,
+ 0, /* packetIndex */
&info_frame->vsc);
/* enable/disable transmission of packet(s).
* If enabled, packet transmission begins on the next frame
*/
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE,
info_frame->vsc.valid);
- REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
/* This bit is the master enable bit.
* When enabling secondary stream engine,
* this master bit must also be set.
@@ -535,16 +562,8 @@ static void dce110_stream_encoder_stop_dp_info_packets(
DP_SEC_AVI_ENABLE, 0,
DP_SEC_MPG_ENABLE, 0,
DP_SEC_STREAM_ENABLE, 0);
- } else {
- ASSERT(enc110->se_mask->DP_SEC_AVI_ENABLE);
- REG_SET_6(DP_SEC_CNTL, 0,
- DP_SEC_GSP0_ENABLE, 0,
- DP_SEC_GSP1_ENABLE, 0,
- DP_SEC_GSP2_ENABLE, 0,
- DP_SEC_GSP3_ENABLE, 0,
- DP_SEC_MPG_ENABLE, 0,
- DP_SEC_STREAM_ENABLE, 0);
}
+
/* this register shared with audio info frame.
* therefore we need to keep master enabled
* if at least one of the fields is not 0 */
@@ -558,7 +577,6 @@ static void dce110_stream_encoder_dp_blank(
struct stream_encoder *enc)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- uint32_t value;
uint32_t retries = 0;
uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
@@ -586,19 +604,9 @@ static void dce110_stream_encoder_dp_blank(
* Poll for DP_VID_STREAM_STATUS == 0
*/
- do {
- value = REG_READ(DP_VID_STREAM_CNTL);
-
- if (!get_reg_field_value(
- value,
- DP_VID_STREAM_CNTL,
- DP_VID_STREAM_STATUS))
- break;
-
- udelay(10);
-
- ++retries;
- } while (retries < max_retries);
+ REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
+ 1,
+ 10, max_retries);
ASSERT(retries <= max_retries);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index c6bb95888cc0..88ef2a1f2a43 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -97,7 +97,6 @@
SE_COMMON_REG_LIST_DCE_BASE(id), \
SRI(AFMT_CNTL, DIG, id)
-
#define SE_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -115,12 +114,6 @@
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_CONT, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_SEND, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_LINE, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_CONT, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_SEND, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_LINE, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
@@ -222,18 +215,31 @@ struct dce_stream_encoder_shift {
uint8_t AFMT_GENERIC_HB1;
uint8_t AFMT_GENERIC_HB2;
uint8_t AFMT_GENERIC_HB3;
+ uint8_t AFMT_GENERIC_LOCK_STATUS;
+ uint8_t AFMT_GENERIC_CONFLICT;
+ uint8_t AFMT_GENERIC_CONFLICT_CLR;
+ uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC0_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC1_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC2_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC3_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC4_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC5_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC6_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC7_FRAME_UPDATE;
uint8_t HDMI_GENERIC0_CONT;
uint8_t HDMI_GENERIC0_SEND;
uint8_t HDMI_GENERIC0_LINE;
uint8_t HDMI_GENERIC1_CONT;
uint8_t HDMI_GENERIC1_SEND;
uint8_t HDMI_GENERIC1_LINE;
- uint8_t HDMI_GENERIC2_CONT;
- uint8_t HDMI_GENERIC2_SEND;
- uint8_t HDMI_GENERIC2_LINE;
- uint8_t HDMI_GENERIC3_CONT;
- uint8_t HDMI_GENERIC3_SEND;
- uint8_t HDMI_GENERIC3_LINE;
uint8_t DP_PIXEL_ENCODING;
uint8_t DP_COMPONENT_DEPTH;
uint8_t DP_DYN_RANGE;
@@ -262,6 +268,10 @@ struct dce_stream_encoder_shift {
uint8_t DP_SEC_GSP1_ENABLE;
uint8_t DP_SEC_GSP2_ENABLE;
uint8_t DP_SEC_GSP3_ENABLE;
+ uint8_t DP_SEC_GSP4_ENABLE;
+ uint8_t DP_SEC_GSP5_ENABLE;
+ uint8_t DP_SEC_GSP6_ENABLE;
+ uint8_t DP_SEC_GSP7_ENABLE;
uint8_t DP_SEC_AVI_ENABLE;
uint8_t DP_SEC_MPG_ENABLE;
uint8_t DP_VID_STREAM_DIS_DEFER;
@@ -307,6 +317,19 @@ struct dce_stream_encoder_shift {
uint8_t AFMT_AUDIO_CLOCK_EN;
uint8_t TMDS_PIXEL_ENCODING;
uint8_t TMDS_COLOR_FORMAT;
+ uint8_t DP_DB_DISABLE;
+ uint8_t DP_MSA_MISC0;
+ uint8_t DP_MSA_HTOTAL;
+ uint8_t DP_MSA_VTOTAL;
+ uint8_t DP_MSA_HSTART;
+ uint8_t DP_MSA_VSTART;
+ uint8_t DP_MSA_HSYNCWIDTH;
+ uint8_t DP_MSA_HSYNCPOLARITY;
+ uint8_t DP_MSA_VSYNCWIDTH;
+ uint8_t DP_MSA_VSYNCPOLARITY;
+ uint8_t DP_MSA_HWIDTH;
+ uint8_t DP_MSA_VHEIGHT;
+ uint8_t HDMI_DB_DISABLE;
};
struct dce_stream_encoder_mask {
@@ -317,18 +340,31 @@ struct dce_stream_encoder_mask {
uint32_t AFMT_GENERIC_HB1;
uint32_t AFMT_GENERIC_HB2;
uint32_t AFMT_GENERIC_HB3;
+ uint32_t AFMT_GENERIC_LOCK_STATUS;
+ uint32_t AFMT_GENERIC_CONFLICT;
+ uint32_t AFMT_GENERIC_CONFLICT_CLR;
+ uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC0_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC1_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC2_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC3_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC4_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC5_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC6_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC7_FRAME_UPDATE;
uint32_t HDMI_GENERIC0_CONT;
uint32_t HDMI_GENERIC0_SEND;
uint32_t HDMI_GENERIC0_LINE;
uint32_t HDMI_GENERIC1_CONT;
uint32_t HDMI_GENERIC1_SEND;
uint32_t HDMI_GENERIC1_LINE;
- uint32_t HDMI_GENERIC2_CONT;
- uint32_t HDMI_GENERIC2_SEND;
- uint32_t HDMI_GENERIC2_LINE;
- uint32_t HDMI_GENERIC3_CONT;
- uint32_t HDMI_GENERIC3_SEND;
- uint32_t HDMI_GENERIC3_LINE;
uint32_t DP_PIXEL_ENCODING;
uint32_t DP_COMPONENT_DEPTH;
uint32_t DP_DYN_RANGE;
@@ -357,6 +393,10 @@ struct dce_stream_encoder_mask {
uint32_t DP_SEC_GSP1_ENABLE;
uint32_t DP_SEC_GSP2_ENABLE;
uint32_t DP_SEC_GSP3_ENABLE;
+ uint32_t DP_SEC_GSP4_ENABLE;
+ uint32_t DP_SEC_GSP5_ENABLE;
+ uint32_t DP_SEC_GSP6_ENABLE;
+ uint32_t DP_SEC_GSP7_ENABLE;
uint32_t DP_SEC_AVI_ENABLE;
uint32_t DP_SEC_MPG_ENABLE;
uint32_t DP_VID_STREAM_DIS_DEFER;
@@ -402,6 +442,19 @@ struct dce_stream_encoder_mask {
uint32_t AFMT_AUDIO_CLOCK_EN;
uint32_t TMDS_PIXEL_ENCODING;
uint32_t TMDS_COLOR_FORMAT;
+ uint32_t DP_DB_DISABLE;
+ uint32_t DP_MSA_MISC0;
+ uint32_t DP_MSA_HTOTAL;
+ uint32_t DP_MSA_VTOTAL;
+ uint32_t DP_MSA_HSTART;
+ uint32_t DP_MSA_VSTART;
+ uint32_t DP_MSA_HSYNCWIDTH;
+ uint32_t DP_MSA_HSYNCPOLARITY;
+ uint32_t DP_MSA_VSYNCWIDTH;
+ uint32_t DP_MSA_VSYNCPOLARITY;
+ uint32_t DP_MSA_HWIDTH;
+ uint32_t DP_MSA_VHEIGHT;
+ uint32_t HDMI_DB_DISABLE;
};
struct dce110_stream_enc_registers {
@@ -421,6 +474,7 @@ struct dce110_stream_enc_registers {
uint32_t AFMT_GENERIC_HDR;
uint32_t AFMT_INFOFRAME_CONTROL0;
uint32_t AFMT_VBI_PACKET_CONTROL;
+ uint32_t AFMT_VBI_PACKET_CONTROL1;
uint32_t AFMT_AUDIO_PACKET_CONTROL;
uint32_t AFMT_AUDIO_PACKET_CONTROL2;
uint32_t AFMT_AUDIO_SRC_CONTROL;
@@ -443,6 +497,8 @@ struct dce110_stream_enc_registers {
uint32_t HDMI_GC;
uint32_t HDMI_GENERIC_PACKET_CONTROL0;
uint32_t HDMI_GENERIC_PACKET_CONTROL1;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL2;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL3;
uint32_t HDMI_INFOFRAME_CONTROL0;
uint32_t HDMI_INFOFRAME_CONTROL1;
uint32_t HDMI_VBI_PACKET_CONTROL;
@@ -455,6 +511,14 @@ struct dce110_stream_enc_registers {
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t TMDS_CNTL;
+ uint32_t DP_DB_CNTL;
+ uint32_t DP_MSA_MISC;
+ uint32_t DP_MSA_COLORIMETRY;
+ uint32_t DP_MSA_TIMING_PARAM1;
+ uint32_t DP_MSA_TIMING_PARAM2;
+ uint32_t DP_MSA_TIMING_PARAM3;
+ uint32_t DP_MSA_TIMING_PARAM4;
+ uint32_t HDMI_DB_CONTROL;
};
struct dce110_stream_encoder {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index a6679a95694e..249438456f73 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -855,7 +855,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_enc->funcs->dp_set_stream_attribute(
pipe_ctx->stream_enc,
- &stream->public.timing);
+ &stream->public.timing,
+ stream->public.output_color_space);
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute(
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
index 83c246c558a5..9caf2b365420 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
@@ -55,7 +55,8 @@ struct stream_encoder {
struct stream_encoder_funcs {
void (*dp_set_stream_attribute)(
struct stream_encoder *enc,
- struct dc_crtc_timing *crtc_timing);
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space);
void (*hdmi_set_stream_attribute)(
struct stream_encoder *enc,
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
index ef652abcd276..4c1286dc3bdb 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
@@ -69,38 +69,50 @@
#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
REG_SET_N(reg, 3, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3)
#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
REG_SET_N(reg, 4, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3,\
- FD(reg##__##f4), v4)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4)
#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
f5, v5, f6, v6) \
REG_SET_N(reg, 6, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3,\
- FD(reg##__##f4), v4,\
- FD(reg##__##f5), v5,\
- FD(reg##__##f6), v6)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4,\
+ FN(reg, f5), v5,\
+ FN(reg, f6), v6)
#define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
f5, v5, f6, v6, f7, v7) \
REG_SET_N(reg, 7, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3,\
- FD(reg##__##f4), v4,\
- FD(reg##__##f5), v5,\
- FD(reg##__##f6), v6,\
- FD(reg##__##f7), v7)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4,\
+ FN(reg, f5), v5,\
+ FN(reg, f6), v6,\
+ FN(reg, f7), v7)
+#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5,
f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
+ REG_SET_N(reg, 10, init_value, \
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2, \
+ FN(reg, f3), v3, \
+ FN(reg, f4), v4, \
+ FN(reg, f5), v5, \
+ FN(reg, f6), v6, \
+ FN(reg, f7), v7, \
+ FN(reg, f8), v8, \
+ FN(reg, f9), v9, \
+ FN(reg, f10), v10)
/* macro to get register fields
* read given register and fill in field value in output parameter */
@@ -196,15 +208,28 @@
#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7,
v7, f8, v8, f9, v9) \
REG_UPDATE_N(reg, 9, \
- FN(reg, f1), val1,\
- FN(reg, f2), val2, \
- FN(reg, f3), val3, \
- FN(reg, f4), val4, \
- FN(reg, f5), val5, \
- FN(reg, f6), val6, \
- FN(reg, f7), val7, \
- FN(reg, f8), val8, \
- FN(reg, f9), val9)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2, \
+ FN(reg, f3), v3, \
+ FN(reg, f4), v4, \
+ FN(reg, f5), v5, \
+ FN(reg, f6), v6, \
+ FN(reg, f7), v7, \
+ FN(reg, f8), v8, \
+ FN(reg, f9), v9)
+
+#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7,
v7, f8, v8, f9, v9, f10, v10) \
+ REG_UPDATE_N(reg, 10, \
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2, \
+ FN(reg, f3), v3, \
+ FN(reg, f4), v4, \
+ FN(reg, f5), v5, \
+ FN(reg, f6), v6, \
+ FN(reg, f7), v7, \
+ FN(reg, f8), v8, \
+ FN(reg, f9), v9, \
+ FN(reg, f10), v10)
/* macro to update a register field to specified values in given sequences.
* useful when toggling bits
diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
index 30d07efb4ee7..8de21d9a8079 100644
--- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
@@ -28,7 +28,8 @@
static void virtual_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
- struct dc_crtc_timing *crtc_timing) {}
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space) {}
static void virtual_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
--
2.10.1
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