From: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>

Signed-off-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 110 +++++++++++++++++++++
 .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   5 +-
 drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |   1 +
 3 files changed, 115 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c 
b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
index 8e669971b321..5247543dc6c1 100644
--- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
@@ -2294,6 +2294,116 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
                dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
                dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
                break;
+       case BW_CALCS_VERSION_STONEY:
+               vbios.memory_type = bw_def_gddr5;
+               vbios.dram_channel_width_in_bits = 64;
+               vbios.number_of_dram_channels = 1;
+               vbios.number_of_dram_banks = 8;
+               vbios.high_yclk = bw_int_to_fixed(1866);
+               vbios.mid_yclk = bw_int_to_fixed(1866);
+               vbios.low_yclk = bw_int_to_fixed(1333);
+               vbios.low_sclk = bw_int_to_fixed(200);
+               vbios.mid1_sclk = bw_int_to_fixed(600);
+               vbios.mid2_sclk = bw_int_to_fixed(600);
+               vbios.mid3_sclk = bw_int_to_fixed(600);
+               vbios.mid4_sclk = bw_int_to_fixed(600);
+               vbios.mid5_sclk = bw_int_to_fixed(600);
+               vbios.mid6_sclk = bw_int_to_fixed(600);
+               vbios.high_sclk = bw_int_to_fixed(800);
+               vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
+               vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
+               vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
+               vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
+               vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
+               vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
+               vbios.data_return_bus_width = bw_int_to_fixed(32);
+               vbios.trc = bw_int_to_fixed(50);
+               vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
+               vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(158, 
10);
+               vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
+               vbios.nbp_state_change_latency = bw_frc_to_fixed(208, 10);
+               vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
+               vbios.scatter_gather_enable = true;
+               vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
+               vbios.cursor_width = 32;
+               vbios.average_compression_rate = 4;
+               vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel 
= 256;
+               vbios.blackout_duration = bw_int_to_fixed(18); /* us */
+               vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
+
+               dceip.large_cursor = false;
+               dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
+               dceip.dmif_pipe_en_fbc_chunk_tracker = false;
+               dceip.cursor_max_outstanding_group_num = 1;
+               dceip.lines_interleaved_into_lb = 2;
+               dceip.chunk_width = 256;
+               dceip.number_of_graphics_pipes = 2;
+               dceip.number_of_underlay_pipes = 1;
+               dceip.low_power_tiling_mode = 0;
+               dceip.display_write_back_supported = false;
+               dceip.argb_compression_support = false;
+               dceip.underlay_vscaler_efficiency6_bit_per_component =
+                       bw_frc_to_fixed(35556, 10000);
+               dceip.underlay_vscaler_efficiency8_bit_per_component =
+                       bw_frc_to_fixed(34286, 10000);
+               dceip.underlay_vscaler_efficiency10_bit_per_component =
+                       bw_frc_to_fixed(32, 10);
+               dceip.underlay_vscaler_efficiency12_bit_per_component =
+                       bw_int_to_fixed(3);
+               dceip.graphics_vscaler_efficiency6_bit_per_component =
+                       bw_frc_to_fixed(35, 10);
+               dceip.graphics_vscaler_efficiency8_bit_per_component =
+                       bw_frc_to_fixed(34286, 10000);
+               dceip.graphics_vscaler_efficiency10_bit_per_component =
+                       bw_frc_to_fixed(32, 10);
+               dceip.graphics_vscaler_efficiency12_bit_per_component =
+                       bw_int_to_fixed(3);
+               dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
+               dceip.max_dmif_buffer_allocated = 2;
+               dceip.graphics_dmif_size = 12288;
+               dceip.underlay_luma_dmif_size = 19456;
+               dceip.underlay_chroma_dmif_size = 23552;
+               dceip.pre_downscaler_enabled = true;
+               dceip.underlay_downscale_prefetch_enabled = true;
+               dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
+               dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
+               dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
+               dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
+                       bw_int_to_fixed(0);
+               dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
+                       82176);
+               dceip.underlay420_chroma_lb_size_per_component =
+                       bw_int_to_fixed(164352);
+               dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
+                       82176);
+               dceip.cursor_chunk_width = bw_int_to_fixed(64);
+               dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
+               dceip.underlay_maximum_width_efficient_for_tiling =
+                       bw_int_to_fixed(1920);
+               dceip.underlay_maximum_height_efficient_for_tiling =
+                       bw_int_to_fixed(1080);
+               
dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display
 =
+                       bw_frc_to_fixed(3, 10);
+               
dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
+                       bw_int_to_fixed(25);
+               dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
+                       2);
+               dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
+                       bw_int_to_fixed(128);
+               dceip.limit_excessive_outstanding_dmif_requests = true;
+               dceip.linear_mode_line_request_alternation_slice =
+                       bw_int_to_fixed(64);
+               dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
+                       32;
+               dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
+               dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
+               dceip.request_efficiency = bw_frc_to_fixed(8, 10);
+               dceip.dispclk_per_request = bw_int_to_fixed(2);
+               dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
+               dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 
100);
+               dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
+               dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
+               break;
        default:
                break;
        }
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 8a840d3b86d7..cac8a19f28ed 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -1325,7 +1325,10 @@ static bool construct(
        if (!dce110_hw_sequencer_construct(dc))
                goto res_create_fail;
 
-       bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_CARRIZO);
+       if (ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev))
+               bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, 
BW_CALCS_VERSION_STONEY);
+       else
+               bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, 
BW_CALCS_VERSION_CARRIZO);
 
        bw_calcs_data_update_from_pplib(dc);
 
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h 
b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
index 6fb38c718d2d..f9b871b6199b 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
@@ -39,6 +39,7 @@ enum bw_calcs_version {
        BW_CALCS_VERSION_CARRIZO,
        BW_CALCS_VERSION_POLARIS10,
        BW_CALCS_VERSION_POLARIS11,
+       BW_CALCS_VERSION_STONEY,
 };
 
 
/*******************************************************************************
-- 
2.10.1

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