Re: [PATCH v2] drm/amdgpu: flush TLB if valid PDE turns into PTE

Am 12.05.21 um 20:43 schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping t

Re: [PATCH v2] drm/amdgpu: flush TLB if valid PDE turns into PTE

Am 2021-05-12 um 2:43 p.m. schrieb Philip Yang: > Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. > If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this > requires TLB flush, otherwise page table walker will not read updated > PDE0. > > Change page table upda

[PATCH v2] drm/amdgpu: flush TLB if valid PDE turns into PTE

Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping to return free_table flag to indicate the previo