[PATCH v2 11/15] drm/amdgpu: use vram_type instead of checking mem_gddr5 flag

[Huang Rui]

For current design, it would better use vram_type member to check if
current vram is GDDR5. So remove the old mem_gddr5 flag.

Signed-off-by: Huang Rui <ray.hu...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ece2527..e1b2ab5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4375,7 +4375,7 @@ static u8 si_get_strobe_mode_settings(struct 
amdgpu_device *adev, u32 mclk)
        if (mclk <= pi->mclk_strobe_mode_threshold)
                strobe_mode = true;
 
-       if (pi->mem_gddr5)
+       if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
                result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
        else
                result = si_get_ddr3_mclk_frequency_ratio(mclk);
@@ -4965,7 +4965,7 @@ static int si_populate_smc_initial_state(struct 
amdgpu_device *adev,
 
        table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
 
-       if (pi->mem_gddr5) {
+       if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                table->initialState.levels[0].strobeMode =
                        si_get_strobe_mode_settings(adev,
                                                    
initial_state->performance_levels[0].mclk);
@@ -5237,7 +5237,7 @@ static int si_init_smc_table(struct amdgpu_device *adev)
        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
                table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
 
-       if (pi->mem_gddr5)
+       if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
                table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
 
        if (adev->pm.dpm.platform_caps & 
ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
@@ -5414,7 +5414,7 @@ static int si_populate_mclk_value(struct amdgpu_device 
*adev,
        mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
        mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
 
-       if (pi->mem_gddr5) {
+       if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
                mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
                        YCLK_POST_DIV(mpll_param.post_div);
@@ -5426,7 +5426,7 @@ static int si_populate_mclk_value(struct amdgpu_device 
*adev,
                u32 tmp;
                u32 reference_clock = adev->clock.mpll.reference_freq;
 
-               if (pi->mem_gddr5)
+               if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
                        freq_nom = memory_clock * 4;
                else
                        freq_nom = memory_clock * 2;
@@ -5518,7 +5518,7 @@ static int si_convert_power_level_to_smc(struct 
amdgpu_device *adev,
                        level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
        }
 
-       if (pi->mem_gddr5) {
+       if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                if (pl->mclk > pi->mclk_edc_enable_threshold)
                        level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
 
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx