Re: GART write flush error on SI w/ amdgpu

2019-11-27 Thread Dave Airlie
On Wed, 21 Jun 2017 at 00:03, Marek Olšák wrote: > > On Tue, Jun 20, 2017 at 1:46 PM, Christian König > wrote: > > Am 20.06.2017 um 12:34 schrieb Marek Olšák: > >> > >> BTW, I noticed the flush sequence in the kernel is wrong. The correct > >> flush sequence should be: > >> > >> 1)

Re: GART write flush error on SI w/ amdgpu

2017-06-20 Thread Marek Olšák
On Tue, Jun 20, 2017 at 1:46 PM, Christian König wrote: > Am 20.06.2017 um 12:34 schrieb Marek Olšák: >> >> BTW, I noticed the flush sequence in the kernel is wrong. The correct >> flush sequence should be: >> >> 1) EVENT_WRITE_EOP - CACHE_FLUSH_AND_INV_TS - write a dword

Re: GART write flush error on SI w/ amdgpu

2017-06-20 Thread Marek Olšák
On Tue, Jun 20, 2017 at 1:49 PM, Nicolai Hähnle wrote: > On 20.06.2017 12:34, Marek Olšák wrote: >> >> BTW, I noticed the flush sequence in the kernel is wrong. The correct >> flush sequence should be: >> >> 1) EVENT_WRITE_EOP - CACHE_FLUSH_AND_INV_TS - write a dword to

Re: GART write flush error on SI w/ amdgpu

2017-06-20 Thread Nicolai Hähnle
On 20.06.2017 12:34, Marek Olšák wrote: BTW, I noticed the flush sequence in the kernel is wrong. The correct flush sequence should be: 1) EVENT_WRITE_EOP - CACHE_FLUSH_AND_INV_TS - write a dword to memory, but no fence/interrupt. 2) WAIT_REG_MEM on the dword to wait for idle before

Re: GART write flush error on SI w/ amdgpu

2017-06-20 Thread Christian König
Am 20.06.2017 um 12:34 schrieb Marek Olšák: BTW, I noticed the flush sequence in the kernel is wrong. The correct flush sequence should be: 1) EVENT_WRITE_EOP - CACHE_FLUSH_AND_INV_TS - write a dword to memory, but no fence/interrupt. 2) WAIT_REG_MEM on the dword to wait for idle before

Re: GART write flush error on SI w/ amdgpu

2017-06-20 Thread Marek Olšák
BTW, I noticed the flush sequence in the kernel is wrong. The correct flush sequence should be: 1) EVENT_WRITE_EOP - CACHE_FLUSH_AND_INV_TS - write a dword to memory, but no fence/interrupt. 2) WAIT_REG_MEM on the dword to wait for idle before SURFACE_SYNC. 3) SURFACE_SYNC (TC, K$, I$) 4) Write

Re: GART write flush error on SI w/ amdgpu

2017-05-26 Thread Marek Olšák
On Tue, May 9, 2017 at 2:13 PM, Nicolai Hähnle wrote: > Hi all, > > I'm seeing some very strange errors on Verde with CPU readback from GART, > and am pretty much out of ideas. Some help would be very much appreciated. > > The error manifests with the >

GART write flush error on SI w/ amdgpu

2017-05-09 Thread Nicolai Hähnle
Hi all, I'm seeing some very strange errors on Verde with CPU readback from GART, and am pretty much out of ideas. Some help would be very much appreciated. The error manifests with the GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo test on amdgpu, but *not* on radeon. Here's what