anathan, Harish ; Sakhnovitch,
Elena (Elen)
Subject: RE: [PATCH v3 4/8] drm/amd/pm: Add navi1x throttler translation
[AMD Official Use Only]
Thanks Lijo and Graham. Yes, I know that only some specific ASICs support
VR_MEM1 and LIQUID1.
However, the problem is about the design:
1. should we just l
Kasiviswanathan, Harish ;
> Sakhnovitch, Elena (Elen)
> Subject: RE: [PATCH v3 4/8] drm/amd/pm: Add navi1x throttler
> translation
>
> [AMD Official Use Only]
>
> VR_*0/1 reflect the throttle status of separate voltage rails -
> availability of both depends on board and FW capabi
t;
> -Original Message-
> From: Sider, Graham
> Sent: Thursday, June 3, 2021 6:41 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Lazar, Lijo ; Kasiviswanathan, Harish
> ; Sakhnovitch, Elena (Elen)
>
> Subject: RE: [PATCH v3 4/8] drm/amd/pm: Add navi1x throt
-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Kasiviswanathan, Harish
; Sakhnovitch, Elena (Elen)
Subject: RE: [PATCH v3 4/8] drm/amd/pm: Add navi1x throttler translation
Some ASICs use a single VR_MEM bit, whereas others split it into VR_MEM0 and
VR_MEM1. To avoid confusion, we've combine
une 2, 2021 12:37 AM
To: Sider, Graham ; amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Kasiviswanathan, Harish
; Sider, Graham ;
Sakhnovitch, Elena (Elen)
Subject: RE: [PATCH v3 4/8] drm/amd/pm: Add navi1x throttler translation
[AMD Official Use Only]
> -Original Message-
> Fr
[AMD Official Use Only]
> -Original Message-
> From: amd-gfx On Behalf Of
> Graham Sider
> Sent: Wednesday, June 2, 2021 2:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Lazar, Lijo ; Kasiviswanathan, Harish
> ; Sider, Graham
> ; Sakhnovitch, Elena (Elen)
>
> Subject: [PATCH v3 4/8] d
