答复: [PATCH 11/23] drm/amdgpu: implement context save area(CSA) feature

the CSA is used for world switch, and each amdgpu device should have one and only one CSA, and this CSA will pined, and mapped to each virtual memory /process. CP/RLCV will use this CSA buffer when preemption occurred, and will write some hardware status into this CSA buffer, within the

RE: [PATCH 01/23] drm/amdgpu: add support kernel interface queue(KIQ)

> -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Tuesday, December 20, 2016 7:11 AM > To: Yu, Xiangliang > Cc: amd-gfx list ; > dl.SRDC_SW_GPUVirtualization > ; Liu,

RE: [PATCH 12/23] drm/amdgpu: Insert meta data during submitting IB

> -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Tuesday, December 20, 2016 7:23 AM > To: Yu, Xiangliang > Cc: amd-gfx list ; > dl.SRDC_SW_GPUVirtualization > ;

RE: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization

Thank monk’s comments. From: Liu, Monk Sent: Tuesday, December 20, 2016 12:09 PM To: Alex Deucher ; Yu, Xiangliang Cc: amd-gfx list ; dl.SRDC_SW_GPUVirtualization ; Min, Frank

RE: [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox communication

> -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Tuesday, December 20, 2016 7:25 AM > To: Yu, Xiangliang > Cc: amd-gfx list ; > dl.SRDC_SW_GPUVirtualization > ;

RE: [PATCH 06/23] drm/amdgpu/gfx8: correct KIQ hdp flush

> -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Tuesday, December 20, 2016 7:14 AM > To: Yu, Xiangliang > Cc: amd-gfx list ; > dl.SRDC_SW_GPUVirtualization >

RE: [PATCH 15/23] drm/amdgpu/mxgpu: implement register access function with KIQ

> -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Tuesday, December 20, 2016 7:27 AM > To: Yu, Xiangliang > Cc: amd-gfx list ; > dl.SRDC_SW_GPUVirtualization > ;

RE: [PATCH 11/23] drm/amdgpu: implement context save area(CSA) feature

Thank monk’s detail expanation. And I think this patch is only support virtualization world switch, not touch whole amdpgu preemption. Thanks! Xiangliang Yu From: Liu, Monk Sent: Tuesday, December 20, 2016 11:58 AM To: Alex Deucher ; Yu, Xiangliang

答复: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization

Hi Alex I agree with you that this patch's GOLDEN setting programming should be put in VI.C, but I found a hardware issue : original linux logic is that we set golden setting registers separately within each IP's hw init routine, but for TONGA VF, it is really strange that we must set all

答复: 转发: [PATCH 02/23] drm/amdgpu: add kiq into compiling

Hi Christian, the CSA VA update should be correct, we pin it after it allocated per device during init stage, and we map it upon each process creates their vm page tables, since this CSA is pined, I assume there is no need to validate it prior to submission please correct me if I missed

RE: [PATCH 19/23] drm/amdgpu/mxgpu: add implementation of GPU virtualization of VI

> -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Tuesday, December 20, 2016 7:35 AM > To: Yu, Xiangliang > Cc: amd-gfx list ; > dl.SRDC_SW_GPUVirtualization >

Re: [RFC] Mechanism for high priority scheduling in amdgpu

On Dec 19, 2016 6:48 AM, Serguei Sagalovitch wrote: > If compute queue is occupied only by you, the efficiency > is equal with setting job queue to high priority I think. The only risk is the situation when graphics will take all needed CUs. But in any case it

Re: [PATCH 2/8] dal: remove some unused wrappers

Hi Emil, On 2016-12-19 07:46 AM, Emil Velikov wrote: Hi Harry, On 14 December 2016 at 16:26, Harry Wentland wrote: They are still used all over the place (e.g. dc/dce110/dce110_resource.c:413). We should at least do an spatch to use kzalloc/krealloc/kfree across the

Re: [PATCH] drm/amdgpu: Don't save new cursor size before updating CUR_SIZE register.

On Sun, Dec 18, 2016 at 8:46 AM, Daniel Vetter wrote: > On Sat, Dec 17, 2016 at 04:35:09PM +, 'Liviu Dudau' wrote: >> On Fri, Dec 16, 2016 at 07:16:25PM +, Deucher, Alexander wrote: >> > > -Original Message- >> > > From: Liviu Dudau [mailto:li...@dudau.co.uk] >> >

[PATCH 1/3] drm/amd/amdgpu: add Polaris12 support (v2)

From: Junwei Zhang v2: agd: squash in various fixes Signed-off-by: Junwei Zhang Reviewed-by: Alex Deucher Reviewed-by: Christian König Reviewed-by: Ken Wang Signed-off-by:

[PATCH 3/3] drm/amd/amdgpu: add Polaris12 PCI ID

From: Junwei Zhang Signed-off-by: Junwei Zhang Reviewed-by: Alex Deucher Reviewed-by: Christian König Reviewed-by: Ken Wang Signed-off-by: Alex Deucher

[PATCH 2/2] drm/amdgpu: cleanup useless extern functions

Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/vi_dpm.h | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h index fc120ba..c43e03f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h +++

RE: [PATCH] drm/amd/powerplay: fix request smc_sk firmware case

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Huang Rui > Sent: Monday, December 19, 2016 2:16 AM > To: amd-gfx@lists.freedesktop.org > Cc: Huang, Ray > Subject: [PATCH] drm/amd/powerplay: fix request smc_sk firmware case > > This patch

[PATCH] MAINTAINERS: Update mailing list for radeon and amdgpu

amdgpu and radeon development has moved to this list. Signed-off-by: Alex Deucher --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 1a7a7731..3e21c61 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@

[PATCH 2/3] drm/amdgpu/powerplay: add Polaris12 support

From: Junwei Zhang Signed-off-by: Junwei Zhang Reviewed-by: Alex Deucher Reviewed-by: Christian König Reviewed-by: Ken Wang Signed-off-by: Alex Deucher

[PATCH 0/3] amdgpu: Add support for Polaris 12

This patch set adds support for Polaris 12 GPUs. Junwei Zhang (3): drm/amd/amdgpu: add Polaris12 support (v2) drm/amdgpu/powerplay: add Polaris12 support drm/amd/amdgpu: add Polaris12 PCI ID drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 6 +

RE: [RFC] Mechanism for high priority scheduling in amdgpu

Hey Guys, One particular piece I'd like to discuss is how to get around the below issue: > Known current obstacles: > > > The SQ is currently programmed to disregard the HQD priorities, and instead > it picks > jobs at random. Settings from the shader itself are also

Re: [PATCH 01/23] drm/amdgpu: add support kernel interface queue(KIQ)

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > KIQ is queue-memory based initialization method: setup KIQ queue > firstly, then send command to KIQ to setup other queues, without > accessing registers. > > For virtualization, need KIQ to access virtual function

Re: [PATCH 06/23] drm/amdgpu/gfx8: correct KIQ hdp flush

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > KIQ has some behavior as compute ring. > > Signed-off-by: Xiangliang Yu Should be squashed into patch 5. Alex > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 ++- > 1 file changed, 2

Re: [PATCH 09/23] drm/amdgpu: enable virtualization feature for FIJI/TONGA

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > According to chip device id to set VF flag, and call virtual > interface to setup all realted IP blocks. > > Signed-off-by: Xiangliang Yu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5

Re: [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox communication

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > GPU guest driver send mailbox messages to hyperverisor to request > full access to all of registers and release it when access is done. > > Signed-off-by: Xiangliang Yu > Signed-off-by:

Re: [PATCH 15/23] drm/amdgpu/mxgpu: implement register access function with KIQ

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > One of important role of KIQ is provide one way to access VF > registers. This patch implement the feature and export interfaces. > > Signed-off-by: Monk Liu > Signed-off-by: Xiangliang Yu

Re: [PATCH 17/23] drm/amdgpu: export vi common ip block

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > GPU virtualization component need vim common ip block and the > block was also public before. Export it again. > > Signed-off-by: Xiangliang Yu > --- > drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- >

Re: [PATCH 19/23] drm/amdgpu/mxgpu: add implementation of GPU virtualization of VI

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > Different chips will have different virtual behaviors, so need to > implemnt different virtual feature according to hardware design. > > This patch will implemnt Vi family virtualization, it will call > CSA, mailbox

Re: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu wrote: > GPU virtualization has different sequence from normal, change it. > > Signed-off-by: Frank Min > Signed-off-by: Monk Liu > Signed-off-by: Xiangliang Yu >

Re: 转发: [PATCH 02/23] drm/amdgpu: add kiq into compiling

On Mon, Dec 19, 2016 at 6:17 AM, Christian König wrote: > Yeah, agree totally with Monk here. > > If you find that you need some KIQ helpers which are independent of the > hardware generation you can put them into amdgpu_kiq.c. > > Monk, David or maybe even Michel and

RE: [PATCH 20/23] drm/amdgpu/mxgpu: enable VI virtualization

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Xiangliang Yu > Sent: Saturday, December 17, 2016 11:17 AM > To: amd-gfx@lists.freedesktop.org; dl.SRDC_SW_GPUVirtualization > Cc: Yu, Xiangliang > Subject: [PATCH 20/23] drm/amdgpu/mxgpu:

Re: [PATCH 2/8] dal: remove some unused wrappers

Hi Harry, On 14 December 2016 at 16:26, Harry Wentland wrote: > They are still used all over the place (e.g. > dc/dce110/dce110_resource.c:413). > > We should at least do an spatch to use kzalloc/krealloc/kfree across the > board if the wrappers are an issue. > > NAKed >