On 27 October 2017 at 01:15, Andrey Grodzovsky
wrote:
> Change-Id: I7eafb85c1ca96d6d255f0183bed0ce4129746fe0
> Signed-off-by: Andrey Grodzovsky
> ---
> amdgpu/Makefile.sources | 1 +
> amdgpu/amdgpu.h | 20 +++
>
Hi Harry,
actually it's best practice that you only ignore ERESTARTSYS here, see
other code in the driver as well.
EINTR means that the IOCTL was interrupted and can't be restarted
because of some problem.
EAGAIN mean the we can't do this operation right now, but might be able
to do it at
Am 27.10.2017 um 09:22 schrieb Christian König:
Am 26.10.2017 um 20:54 schrieb Felix Kuehling:
On 2017-10-26 02:11 PM, Christian König wrote:
But now reading the patch there is something else which I stumbled
over:
- WARN_ON(atomic_read(>mm->mm_count) <= 0);
+ /*
+ * This cast should
Am 26.10.2017 um 20:54 schrieb Felix Kuehling:
On 2017-10-26 02:11 PM, Christian König wrote:
But now reading the patch there is something else which I stumbled over:
- WARN_ON(atomic_read(>mm->mm_count) <= 0);
+ /*
+ * This cast should be safe here because we grabbed a
+ *
Am 27.10.2017 um 02:15 schrieb Andrey Grodzovsky:
Change-Id: I7eafb85c1ca96d6d255f0183bed0ce4129746fe0
Signed-off-by: Andrey Grodzovsky
---
amdgpu/Makefile.sources | 1 +
amdgpu/amdgpu.h | 20 +++
amdgpu/amdgpu_vm.c | 52
The following commit:
[root@fx6 linux]# git bisect good
aa7187c5c640559ebc02caa0191c0db46b55b4a6 is the first bad commit
commit aa7187c5c640559ebc02caa0191c0db46b55b4a6
Author: Christian König
Date: Thu Oct 26 12:00:36 2017 +0200
drm/amd/display: enable GPU VM
Looks like the DC code can't correctly take care of the difference
between CZ and Tonga.
Harry how should we handle this? Either not set the bit on older
hardware or fix DC to just ignore it there?
To be honest I would prefer not to set a bit at all and just always
program the relevant bits
> -Original Message-
> From: S, Shirish
> Sent: Thursday, October 26, 2017 11:26 PM
> To: amd-gfx@lists.freedesktop.org; Wentland, Harry; Deucher, Alexander
> Subject: [PATCH] drm/amd/display: check if modeset is required before
> adding plane
>
>
> From: Shirish S
>
On 10/27/2017 04:52 AM, Emil Velikov wrote:
On 27 October 2017 at 01:15, Andrey Grodzovsky
wrote:
Change-Id: I7eafb85c1ca96d6d255f0183bed0ce4129746fe0
Signed-off-by: Andrey Grodzovsky
---
amdgpu/Makefile.sources | 1 +
Hi Christian,
thanks for clarifying the semantics. I wasn't fully clear on that. What you say
makes sense. I'll respin the patch.
Harry
On 2017-10-27 03:46 AM, Christian König wrote:
> Hi Harry,
>
> actually it's best practice that you only ignore ERESTARTSYS here, see other
> code in the
From: Christian König
The GTT manager handles the GART address space anyway, so it is
completely pointless to keep the same information around twice.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 --
From: Christian König
Just allocate the GART space and fill it.
This prevents forcing the BO to be idle.
v2: don't unbind/bind at all, just fill the allocated GART space
Signed-off-by: Christian König
---
From: Christian König
We actually don't bind here, but rather allocate GART space if necessary.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
From: Christian König
Rename amdgpu_gtt_mgr_is_allocated() to amdgpu_gtt_mgr_has_gart_addr() and use
that instead.
v2: rename the function as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +++---
From: Christian König
On CZ and newer APUs we can pin the fb into GART as well as VRAM.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 13
On 27/10/17 04:48 PM, Christian König wrote:
> Am 27.10.2017 um 16:37 schrieb Harry Wentland:
>> On 2017-10-26 12:06 PM, Christian König wrote:
>>> From: Christian König
>>>
>>> Just set the bit so that DC does the hardware programming.
>>>
>>> Signed-off-by: Christian
On 2017-10-26 12:06 PM, Christian König wrote:
> From: Christian König
>
> Just set the bit so that DC does the hardware programming.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
> 1
Am 27.10.2017 um 16:37 schrieb Harry Wentland:
On 2017-10-26 12:06 PM, Christian König wrote:
From: Christian König
Just set the bit so that DC does the hardware programming.
Signed-off-by: Christian König
---
On 27/10/17 10:48 AM, Christian König wrote:
Am 27.10.2017 um 16:37 schrieb Harry Wentland:
On 2017-10-26 12:06 PM, Christian König wrote:
From: Christian König
Just set the bit so that DC does the hardware programming.
Signed-off-by: Christian König
Am 27.10.2017 um 16:58 schrieb Michel Dänzer:
On 27/10/17 04:48 PM, Christian König wrote:
Am 27.10.2017 um 16:37 schrieb Harry Wentland:
On 2017-10-26 12:06 PM, Christian König wrote:
From: Christian König
Just set the bit so that DC does the hardware programming.
From: Andrey Grodzovsky
The test will Reserve a VMID, submit a command and
unreserve the VMID.
v2:
Wrappers names were changed.
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/Makefile.am | 3 +-
tests/amdgpu/amdgpu_test.c | 7 +++
From: Andrey Grodzovsky
v2:
Rename wrappers to match the IOCTL naming, fix
identation and fix make check error.
Signed-off-by: Andrey Grodzovsky
---
amdgpu/Makefile.sources| 1 +
amdgpu/amdgpu-symbol-check | 2 ++
amdgpu/amdgpu.h
Am 27.10.2017 um 17:09 schrieb Andrey Grodzovsky:
From: Andrey Grodzovsky
v2:
Rename wrappers to match the IOCTL naming, fix
identation and fix make check error.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
v2: Also don't print for ERESTARTSYS or EAGAIN
v3: Best practice is to only ignore ERESTARTSYS
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On 2017-10-26 11:25 PM, S, Shirish wrote:
>
> From: Shirish S
>
> Adding affected planes without checking if modeset is requested from the user
> space causes performance regression in video p/b scenarios when full screen
> p/b is not composited.
>
> Hence add a check
On 2017-10-27 10:48 AM, Christian König wrote:
> Am 27.10.2017 um 16:37 schrieb Harry Wentland:
>> On 2017-10-26 12:06 PM, Christian König wrote:
>>> From: Christian König
>>>
>>> Just set the bit so that DC does the hardware programming.
>>>
>>> Signed-off-by: Christian
Am 27.10.2017 um 17:40 schrieb Harry Wentland:
On 2017-10-27 10:48 AM, Christian König wrote:
Am 27.10.2017 um 16:37 schrieb Harry Wentland:
On 2017-10-26 12:06 PM, Christian König wrote:
From: Christian König
Just set the bit so that DC does the hardware
Am 27.10.2017 um 17:51 schrieb Harry Wentland:
v2: Also don't print for ERESTARTSYS or EAGAIN
v3: Best practice is to only ignore ERESTARTSYS
Signed-off-by: Harry Wentland
Reviewed-by: Christian König .
---
crtc is dereferenced from within drm_atomic_get_new_crtc_state, so
check for NULL before initializing new_crtc_state.
Signed-off-by: Drew Davenport
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
On 2017-10-27 03:41 AM, Christian König wrote:
> Am 27.10.2017 um 09:22 schrieb Christian König:
>> Am 26.10.2017 um 20:54 schrieb Felix Kuehling:
>>> On 2017-10-26 02:11 PM, Christian König wrote:
But now reading the patch there is something else which I stumbled
over:
> -
On 2017-10-27 02:34 PM, Drew Davenport wrote:
> crtc is dereferenced from within drm_atomic_get_new_crtc_state, so
> check for NULL before initializing new_crtc_state.
>
> Signed-off-by: Drew Davenport
Reviewed-by: Harry Wentland
Harry
> ---
>
ASIC temperature reading from HOTSPOT to ASIC edge.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
On 2017-10-26 10:51 PM, Andrey Grodzovsky wrote:
>
>
> On 2017-10-26 02:35 PM, Harry Wentland wrote:
>> We need to avoid calling reset after detection.
>
> Could you explain why please ?
Reset creates new, clean atomic_state objects. In this case we want to attach
the freesync_capable
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Eric Huang
> Sent: Friday, October 27, 2017 3:31 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, JinHuiEric
> Subject: [PATCH] drm/amd/powerplay: change ASIC temperature reading on
>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Drew Davenport
> Sent: Saturday, October 28, 2017 12:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Drew Davenport
>
This speeds up signal lookup when the IH ring entry includes a
valid context ID or partial context ID. Only if the context ID is
found to be invalid, fall back to an exhaustive search of all
signaled events.
Signed-off-by: Felix Kuehling
Acked-by: Oded Gabbay
From: Andres Rodriguez
In systems under heavy load the IH work may experience significant
scheduling delays.
Under load + system workqueue:
Max Latency: 7.023695 ms
Avg Latency: 0.263994 ms
Under load + high priority workqueue:
Max Latency: 1.162568 ms
When an event with pending waiters is destroyed, those waiters may
end up sleeping forever unless they are notified and woken up.
Implement the notification by clearing the waiter->event pointer,
which becomes invalid anyway, when the event is freed, and waking
up the waiting tasks.
Waiters on an
From: Andres Rodriguez
Replace our implementation of a lockless ring buffer with the standard
linux kernel kfifo.
We shouldn't maintain our own version of a standard data structure.
Signed-off-by: Andres Rodriguez
Signed-off-by: Felix
The first event page is always big enough to handle all events.
Handling of multiple events pages is not supported by user mode, and
not necessary.
Signed-off-by: Yong Zhao
Signed-off-by: Felix Kuehling
Acked-by: Oded Gabbay
---
Use standard wait queues for waiting and waking up waiting threads
instead of inventing our own. We still have our own wait loop
because the HSA event semantics require the ability to have one
thread waiting on multiple wait queues (events) at the same time.
Signed-off-by: Kent Russell
From: Andres Rodriguez
A larger buffer will let us accommodate applications with a large amount
of semi-simultaneous event signals.
Signed-off-by: Andres Rodriguez
Signed-off-by: Felix Kuehling
Acked-by: Oded Gabbay
This allows increasing the KFD_SIGNAL_EVENT_LIMIT in kfd_ioctl.h
without breaking processes built with older kfd_ioctl.h versions.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 25 +++--
Signal slots are identical to event IDs.
Replace the used_slot_bitmap and events hash table with an IDR to
allocate and lookup event IDs and signal slots more efficiently.
Signed-off-by: Felix Kuehling
Acked-by: Oded Gabbay
---
From: Andres Rodriguez
We don't need to wait for all work to complete in the IH exit function.
We only need to make sure the interrupt_work has finished executing to
guarantee that ih_kfifo is no longer in use.
Signed-off-by: Andres Rodriguez
This always identical with the index of the event_waiter in the array.
No need to store it in the waiter record.
Signed-off-by: Felix Kuehling
Reviewed-by: Oded Gabbay
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 9 +++--
1 file changed, 3
Cleaned up the code while resolving some potential bugs and
inconsistencies in the process.
Clean-ups:
* Remove enum kfd_event_wait_result, which duplicates
KFD_IOC_EVENT_RESULT definitions
* alloc_event_waiters can be called without holding p->event_mutex
* Return an error code from
The kfd_process doesn't own a reference to the mm_struct, so it can
disappear without warning even while the kfd_process still exists.
Therefore, avoid dereferencing the kfd_process.mm pointer and make
it opaque. Use get_task_mm to get a temporary reference to the mm
when it's needed.
v2:
From: Sean Keely
If kfd_wait_on_events can return immediately, we don't need to populate
the wait list and don't need to enter the sleep-loop.
Signed-off-by: Sean Keely
Signed-off-by: Felix Kuehling
Acked-by: Oded Gabbay
This patch series improves interrupt handling latency, signal event
processing overhead and replaces some custom data structures with
standard kernel data structures (idr, kfifo, waitqueue).
It also increases the capacity of the number of signals that can be
processed from 256 to 4096. This
From: Besar Wicaksono
This enables SDMA signalling with event interrupt.
Signed-off-by: Besar Wicaksono
Signed-off-by: Felix Kuehling
Reviewed-by: Oded Gabbay
---
From: Sean Keely
Signed-off-by: Sean Keely
Signed-off-by: Felix Kuehling
Acked-by: Oded Gabbay
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 13 -
1 file changed, 12 insertions(+), 1
From: Shirish S
While setting cursor position in case of mpo, input_pixel_processor is not
available for underlay, hence add check of the same to avoid null pointer
access issue.
Signed-off-by: Shirish S
Reviewed-by: Harry Wentland
On 10/27/2017 03:33 PM, Harry Wentland wrote:
On 2017-10-26 10:51 PM, Andrey Grodzovsky wrote:
On 2017-10-26 02:35 PM, Harry Wentland wrote:
We need to avoid calling reset after detection.
Could you explain why please ?
Reset creates new, clean atomic_state objects. In this case we want
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