AMDGPU_FW_LOAD_DIRECT is used for bring up.
Now it don't work any more. so remove the support.
v2: Add warning message if user select
AMDGPU_FW_LOAD_DIRECT/AMDGPU_FW_LOAD_PSP on VI.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 7 +-
Same comment as for v1
Regards,
Leo
On 10/02/2018 04:35 PM, James Zhu wrote:
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++
Am 28.09.2018 um 09:42 schrieb Rex Zhu:
1. make uvd_v7_0_enc_get_destroy_msg static
2. drop a function variable that always true
Signed-off-by: Rex Zhu
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 10 +++---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 12
Thanks for keeping working on this.
Series is Reviewed-by: Christian König as well.
Do you now have commit rights?
Christian.
Am 02.10.2018 um 22:47 schrieb Marek Olšák:
For the series:
Reviewed-by: Marek Olšák
Marek
On Fri, Sep 28, 2018 at 10:46 AM Andrey Grodzovsky
wrote:
Seems like
Acked-by: Leo Liu
On 10/02/2018 01:18 PM, James Zhu wrote:
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8
2
Feel free to add an Acked-by: Christian König
as well if that helps.
Christian.
Am 03.10.2018 um 14:17 schrieb Kuehling, Felix:
Hi Alex,
If it's not too late, I'd like to get this into 4.19. Sorry I missed this fix
earlier.
Regards,
Felix
From:
Am 28.09.2018 um 09:36 schrieb Huang, Ray:
-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Thursday, September 27, 2018 7:26 PM
To: Huang, Ray
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 01/12] drm/amdgpu: add missing error handling
Am
1. only call late_init when hw_init successful,
so check status.hw instand of status.valid in late_init.
2. set status.late_initialized true if late_init was not implemented.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/cik.c | 17 +
drivers/gpu/drm/amd/amdgpu/si.c | 13 +++--
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
Hi Alex,
If it's not too late, I'd like to get this into 4.19. Sorry I missed this fix
earlier.
Regards,
Felix
From: Kuehling, Felix
Sent: Tuesday, October 2, 2018 6:41:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: oded.gab...@gmail.com; Kuehling, Felix
Am 29.09.2018 um 11:48 schrieb Emily Deng:
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the sdma engine hang.
So limit the mc address to AMDGPU_VA_HOLE_START.
Well NAK, but that's what I've done initially as well :)
That
Acked-by: Leo Liu
On 10/02/2018 01:35 PM, James Zhu wrote:
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +++---
ucode bo is needed by request_smu_load_fw,
the request_smu_load_fw maybe called by gfx/sdma
before smu hw init.
so move amdgpu_ucode_bo_init to request_smu_lowd_fw
from smu hw init.
Reviewed-by: Evan Quan
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
gfx and sdma can be initialized before smu.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
with this interface, gfx/sdma can be initialized
before smu.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/vi.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
driver don't release the ucode memory when suspend. so don't
need to allocate bo when resume back.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
we are suggested to initialize gfx/sdma before power
feature enabled. and On Vi, the gfx/sdma fw will be loaded
by smu, Export load_firmware interface to
gfx/sdma, so gfx/sdma can trigger fw loading if they were
initialized before smu.
Rex Zhu (5):
drm/amdgpu: Don't reallocate ucode bo when
On 10/02/2018 01:20 PM, James Zhu wrote:
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 +++-
2 files changed, 12 insertions(+), 7
Fix cg/pg unexpected set in hw init failed case.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index
From: Pratik Vishwakarma
[Why]
1. We never submit IBs to KIQ.
2. Ring test pass without KIQ's ring also.
3. By skipping we see an improvement of around 500ms
in the amdgpu's resume time.
[How]
skip IB tests for KIQ ring type.
Signed-off-by: Shirish S
Signed-off-by: Pratik Vishwakarma
---
Yes, Andrey has commit rights.
Marek
On Wed, Oct 3, 2018 at 10:34 AM Christian König
wrote:
>
> Thanks for keeping working on this.
>
> Series is Reviewed-by: Christian König as well.
>
> Do you now have commit rights?
>
> Christian.
>
> Am 02.10.2018 um 22:47 schrieb Marek Olšák:
> > For the
On Wed, Oct 3, 2018 at 1:41 AM Felix Kuehling wrote:
>
> This mm_struct pointer should never be dereferenced. If running in
> a user thread, just use current->mm. If running in a kernel worker
> use get_task_mm to get a safe reference to the mm_struct.
>
> Signed-off-by: Felix Kuehling
> ---
>
Hi Christian,
Yes, I agree. I am working on patch 2 to replace get_user_page with HMM.
One problem is in current gfx path, we check if mmu_invalidation
multiple times in amdgpu_cs_ioctl() path after get_user_page(),
amdgpu_cs_parser_bos(), amdgpu_cs_list_validate(), and
amdgpu_cs_submit().
On Wed, Oct 03, 2018 at 10:41:20AM +0200, Daniel Vetter wrote:
> On Tue, Oct 02, 2018 at 10:49:17AM -0400, Harry Wentland wrote:
> >
> >
> > On 2018-10-01 03:15 AM, Daniel Vetter wrote:
> > > On Mon, Sep 24, 2018 at 02:15:34PM -0400, Nicholas Kazlauskas wrote:
> > >> These patches are part of a
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 +++-
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 24
The following WREG32_SOC15_DPG_MODE will overwrite register
mmUVD_CGC_CTRL. This code can be removed.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
Reviewed-by: Leo Liu
On 10/02/2018 09:20 AM, James Zhu wrote:
The following WREG32_SOC15_DPG_MODE will overwrite register
mmUVD_CGC_CTRL. This code can be removed.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git
On Wed, Oct 3, 2018 at 7:11 AM Rex Zhu wrote:
>
> driver don't release the ucode memory when suspend. so don't
> need to allocate bo when resume back.
>
> Signed-off-by: Rex Zhu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
On Wed, Oct 3, 2018 at 7:11 AM Rex Zhu wrote:
>
> gfx and sdma can be initialized before smu.
>
> Signed-off-by: Rex Zhu
I think sdma_v2_4.c needs a similar update for iceland. With that fixed:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++
>
On Wed, Oct 3, 2018 at 6:56 AM Rex Zhu wrote:
>
> Fix cg/pg unexpected set in hw init failed case.
>
> Signed-off-by: Rex Zhu
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
On Wed, Oct 3, 2018 at 7:11 AM Rex Zhu wrote:
>
> with this interface, gfx/sdma can be initialized
> before smu.
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git
On Wed, Oct 3, 2018 at 7:11 AM Rex Zhu wrote:
>
> ucode bo is needed by request_smu_load_fw,
> the request_smu_load_fw maybe called by gfx/sdma
> before smu hw init.
> so move amdgpu_ucode_bo_init to request_smu_lowd_fw
> from smu hw init.
>
> Reviewed-by: Evan Quan
> Signed-off-by: Rex Zhu
On Wed, Oct 3, 2018 at 11:15 AM Shirish S wrote:
>
> From: Pratik Vishwakarma
>
> [Why]
> 1. We never submit IBs to KIQ.
> 2. Ring test pass without KIQ's ring also.
> 3. By skipping we see an improvement of around 500ms
>in the amdgpu's resume time.
>
> [How]
> skip IB tests for KIQ ring
Hi
I'm curious to know whether this will/could work over PRIME
If the discrete card is rendering slower than the display's frequency could
the frequency be dropped on integrated display? I think there are laptops
that have freesync now
Cheers
Mike
On Mon, 1 Oct 2018 at 08:15 Daniel Vetter
On Tue, Oct 02, 2018 at 10:49:17AM -0400, Harry Wentland wrote:
>
>
> On 2018-10-01 03:15 AM, Daniel Vetter wrote:
> > On Mon, Sep 24, 2018 at 02:15:34PM -0400, Nicholas Kazlauskas wrote:
> >> These patches are part of a proposed new interface for supporting variable
> >> refresh rate via DRM
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