Unfortunately, not. I sent this patch to the reporter to try and it didn't
work.
- Roman
From: amd-gfx On Behalf Of Deucher,
Alexander
Sent: Thursday, November 29, 2018 11:27 AM
To: Li, Sun peng (Leo) ; amd-gfx@lists.freedesktop.org
Cc: Wu, Hersen
Subject: Re: [PATCH 09/16] drm/amd/display:
Hersen confirmed 4k60 works fine over DP. The problem here are really just
USB-C ports and associated dongles. We've never supported USB-C dongles on
CZ/ST before.
Harry
On 2018-11-27 1:49 p.m., S, Shirish wrote:
> This is for the devices with type-c ports.
>
> Wherein the signal type is same
Does this patch help you?
https://patchwork.freedesktop.org/patch/264781/
The easiest way to test it would be to build and try the amd-staging-drm-next
branch from https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
Which monitors are you using and how are they connected (DP,
XGMI hive has some resources allocted on device init which
needs to be deallocated when the device is unregistered.
Add per hive wq to allow all the nodes in hive to run resets
concurently - this should speed up the total reset time to avoid
breaching the PSP FW timeout.
Signed-off-by: Andrey
Use per hive wq to concurrently send reset commands to all nodes
in the hive.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +++---
2 files changed, 32 insertions(+), 3
On Wed, Nov 28, 2018 at 3:12 AM Christian König
wrote:
>
> Maybe drop patch #2 when you refactor that code in patch #3 and #4 anyway.
>
> On patch #3 I would put the new helper into amdgpu_ctx.c instead because
> that is rather how rings map to userspace queues.
>
> Apart from that it looks good
Looks like it was missed when setting support was added.
Signed-off-by: Alex Deucher
---
This is a legit bug fix. the rest of this series needs more work.
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
Am 29.11.18 um 09:08 schrieb zhoucm1:
On 2018年11月28日 22:50, Christian König wrote:
For a lot of use cases we need 64bit sequence numbers. Currently drivers
overload the dma_fence structure to store the additional bits.
Stop doing that and make the sequence number in the dma_fence always
On 21.11.2018 19:19, Laurent Pinchart wrote:
> Hi Ville,
>
> Thank you for the patch.
>
> On Tuesday, 20 November 2018 18:13:42 EET Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Make life easier for drivers by simply passing the connector
>> to drm_hdmi_avi_infoframe_from_display_mode() and
On 2018年11月28日 22:50, Christian König wrote:
For a lot of use cases we need 64bit sequence numbers. Currently drivers
overload the dma_fence structure to store the additional bits.
Stop doing that and make the sequence number in the dma_fence always
64bit.
For compatibility with hardware
Quite late, hopefully not too late.
On 21.11.2018 12:51, Ville Syrjälä wrote:
> On Wed, Nov 21, 2018 at 01:40:43PM +0200, Jani Nikula wrote:
>>
>>> return;
>>> diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c
>>> b/drivers/gpu/drm/bridge/sil-sii8620.c
>>> index
Could you move this one to dma-fence as you said? Which will be used in
other place as well.
-David
On 2018年11月28日 22:50, Christian König wrote:
Extract of useful code from the timeline work. Let's use just a single
stub fence instance instead of allocating a new one all the time.
On 2018年11月28日 22:50, Christian König wrote:
From: Chunming Zhou
v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
amdgpu/amdgpu-symbol-check | 2 ++
amdgpu/amdgpu.h|
Looks very very good, and I applied them in my local, and tested by
./amdgpu_test -s 9 and synobj_basic/wait of IGT today.
+Daniel, Chris, Eric, Could you also have a look as well?
-David
On 2018年11月28日 22:50, Christian König wrote:
Tested this patch set more extensively in the last two
Quoting Christian König (2018-11-28 14:50:12)
> +/**
> + * dma_fence_chain_for_each - iterate over all fences in chain
> + * @fence: starting point as well as current fence
> + *
> + * Iterate over all fences in the chain. We keep a reference to the current
> + * fence while inside the loop which
On 2018年11月28日 22:50, Christian König wrote:
From: Chunming Zhou
v2: drop export/import
Signed-off-by: Chunming Zhou
---
xf86drm.c | 44
xf86drm.h | 8
2 files changed, 52 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index
Am 29.11.18 um 10:28 schrieb zhoucm1:
On 2018年11月28日 22:50, Christian König wrote:
From: Chunming Zhou
v2: drop export/import
Signed-off-by: Chunming Zhou
---
xf86drm.c | 44
xf86drm.h | 8
2 files changed, 52 insertions(+)
diff
[Why]
If the "max bpc" isn't explicitly set in the atomic state then it
have a value of 0. This has the correct behavior of limiting a panel
to 8bpc in the case where the panel supports 8bpc. In the case of eDP
panels this isn't a true assumption - there are panels that can only
do 6bpc.
Banding
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Nicholas
Kazlauskas
Sent: Thursday, November 29, 2018 10:44:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kazlauskas, Nicholas
Subject: [PATCH] drm/amd/display: Fix unintialized max_bpc state values
[Why]
If
From: abdoulaye berthe
[Why]
Failure to read Detailed Capabilities Info.
[How]
Read Detailed Capbilities Info 80h-08Fh.
Signed-off-by: abdoulaye berthe
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Harmanprit Tatla
* Use provided infopacket in stream (if valid) instead of reconstructing
in set_vendor_info_packet()
* Use proper format for enums
* Use dc info packet struct instead
Signed-off-by: Harmanprit Tatla
Reviewed-by: Anthony Koo
Acked-by: Krunoslav Kovac
Acked-by: Leo Li
From: David Francis
[Why]
Tracing is a useful and cheap debug functionality
[How]
This creates a new trace system amdgpu_dm, currently with
three trace events
amdgpu_dc_rreg and amdgpu_dc_wreg report the address and value
of any dc register reads and writes
amdgpu_dc_performance requires at
From: David Francis
[Why]
There are a lot of unintuitive parts of the dm-dc interface.
It would help us if these were documented to provide
a common understanding of what they are supposed to do
[How]
Most of this documentation is stubs, to be filled out more
thoroughly by the experts
Not
From: Chiawen Huang
[why]
add customizable log with a message input, which is for adding
test log in debugging as printf function in ETW.
[Usage]
EVENT_LOG_CUST_MSG1("TestLog","Hello World %d=0x%x", 123, pDC);
Signed-off-by: Chiawen Huang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Krunoslav Kovac
Use axis instead of axix
Signed-off-by: Krunoslav Kovac
Reviewed-by: Aric Cyr
Acked-by: Anthony Koo
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git
From: Yogesh Mohan Marimuthu
[why]
When there are multiple aux transaction in parallel, it is sometime
sporadically the aux transaction starts to continuously fail. The
aux transaction was failing because the busy bit for the given gpio
pin was always set. The busy bit was alway set because the
From: Nicholas Kazlauskas
[Why]
When running igt@kms_plane@pixel-format-pipe-* tests the CRC read will
time out and the test will fail.
This is because the CRTC is duplicated but the crc_enabled parameter
isn't copied over to the new dm_crtc_state. CRC reads will time out
because
From: Nevenko Stupar
For more clear usage in future
Signed-off-by: Nevenko Stupar
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
From: Leo Li
Summary of change:
* Initial documentation of DC
* Implement tracing in DC
* Fix AUX transaction race
Chiawen Huang (1):
drm/amd/display: Add customizable tracing event
David Francis (3):
drm/amd/display: Start documentation of DC
drm/amd/display: Add tracing to dc
From: hersen wu
[WHY] fbc is within the data path from memory to dce. while
re-configure mc dmif, fbc should be enabled. otherwise, fbc
may not be enabled properly.
[HOW] before re-configure mc dmif, disable fbc, only after
dmif re-configuration fully done, enable fbc again.
From: SivapiriyanKumarasamy
Dithering needs to be enabled or disabled as requested. If
dc_stream_update->dither_option is non-null, program the FMT blocks.
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Reviewed-by: Krunoslav Kovac
Acked-by: Leo Li
---
From: Fatemeh Darbehani
[Why]
To prepare for clock debug logging. With the exception of removing
max_supported_dppclk_khz from logs, there are no functional changes.
[How]
Add clk_bypass struct and clean up buffer logic
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Yongqiang Sun
Acked-by: Su
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Shahin Khayyer
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
Am 29.11.18 um 16:52 schrieb sunpeng...@amd.com:
From: David Francis
[Why]
Tracing is a useful and cheap debug functionality
[How]
This creates a new trace system amdgpu_dm, currently with
three trace events
amdgpu_dc_rreg and amdgpu_dc_wreg report the address and value
of any dc register
[Why]
When preferred_mode is NULL a null pointer dereference can occur
when trying to get the preferred refresh in create_stream_for_sink.
[How]
Only query preferred_refresh when preferred_mode is not NULL. Consider
preferred_refresh if it is since it's only being used to compare to
the previous
From: David Francis
dce100 was set to always pass safe_to_lower = false
to the clock manager
Thus, on suspend the clocks were not being set to 0
which is incorrect behaviour
This was causing s3 resume to blackscreen on intel
CPUs with dce100 GPUs attached
(Note that the hash in this Fixes:
On 2018-11-29 10:44 a.m., Nicholas Kazlauskas wrote:
> [Why]
> If the "max bpc" isn't explicitly set in the atomic state then it
> have a value of 0. This has the correct behavior of limiting a panel
> to 8bpc in the case where the panel supports 8bpc. In the case of eDP
> panels this isn't a true
Acked-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Thursday, November 29, 2018 11:20:12 AM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: mar...@gmail.com
Subject: [PATCH] drm/ttm: fix LRU handling in
Do you think this will fix this bug?
https://bugs.freedesktop.org/show_bug.cgi?id=108577
If so, we can re-enable fbc.
Alex
From: amd-gfx on behalf of
sunpeng...@amd.com
Sent: Thursday, November 29, 2018 10:52:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wu,
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