Hi Yanik,
I just sent out several patches(with you in the CC list) and I believe the 1st
patch may fix your issue(raise SOCCLK with mclk).
Regards,
Evan
From: Yanik Yiannakis
Sent: 2019年5月6日 18:56
To: Quan, Evan ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander
Subject: Re: Bug Report:
Am 07.05.19 um 03:47 schrieb Evan Quan:
Negative lockup timeout is valid and will be treated as
'infinite timeout'.
- V2: use msecs_to_jiffies for negative values
Change-Id: I0d8387956a9c744073c0281ef2e1a547d4f16dec
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20
Avoid that we ping/pong the buffers when we stop to pin DMA-buf
exports by using the allowed domains for exported buffers.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Pipeline removal of the BOs backing store when no placement is given
during validation.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index
On the exporter side we add optional explicit pinning callbacks. If those
callbacks are implemented the framework no longer caches sg tables and the
map/unmap callbacks are always called with the lock of the reservation object
held.
On the importer side we add an optional invalidate callback.
That is now done by the DMA-buf helpers instead.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_prime.c | 76 -
1 file changed, 16 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index
Instead of relying on the DRM functions just implement our own import
functions. This prepares support for taking care of unpinned DMA-buf.
v2: enable for all exporters, not just amdgpu, fix invalidation
handling, lock reservation object while setting callback
v3: change to new dma_buf attach
To allow a smooth transition from pinning buffer objects to dynamic
invalidation we first start to cache the sg_table for an attachment.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 24
include/linux/dma-buf.h | 14 ++
2 files changed, 38
This way we can even pipeline imported BO evictions.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index
Allow for invalidation of imported DMA-bufs.
v2: add dma_buf_pin/dma_buf_unpin support
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 29 -
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +
2 files changed, 34 insertions(+), 1
The caching of SGT's is actually quite harmful and should probably removed
altogether when all drivers are audited.
Start by providing a separate DMA-buf export implementation in amdgpu. This is
also a prerequisite of unpinned DMA-buf handling.
v2: fix unintended recursion, remove debugging
On Mon, May 06, 2019 at 04:50:20PM -0300, Jason Gunthorpe wrote:
> On Mon, May 06, 2019 at 06:30:59PM +0200, Andrey Konovalov wrote:
> > This patch is a part of a series that extends arm64 kernel ABI to allow to
> > pass tagged user pointers (with the top byte set to something else other
> > than
No need to enable or disable AVFS if it's already in wanted
state.
Change-Id: I862c0c3d642e6a0dc7bb34e04c5a59f17b6b8deb
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4
1 file changed, 4 insertions(+)
diff --git
With user specified voltage(DPMTABLE_OD_UPDATE_VDDC), the AVFS
will be disabled. However, the buggy code makes this actually not
working as expected.
Change-Id: Ifa83a6255bb3f6fa4bdb4de616521cb7bab6830a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 +--
Update Vega10 top performance level power state accordingly
on OD.
Change-Id: Iaadeefb2904222bf5f4d54b39d7179ce53f92ac0
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 59 +++
1 file changed, 59 insertions(+)
diff --git
This may affects the Vega10 MCLK OD functionality.
Change-Id: Icd685187501b4ec8867fb3c5077ea2664edbd114
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 35 +--
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git
We intentionally didn't do this to make sure that the commands are
ignored by the PSP firmware.
I have no strong opinion on if we should do this or not, but the PSP
firmware guys might have.
Christian.
Am 07.05.19 um 06:08 schrieb Trigger Huang:
IH re-route is not supported on Vega SR-IOV,
Hi Christian,
On Vega10 SR-IOV VF, I injected a 'real' VMC page fault from user space, using
the modified amdgpu_test.
[ 19.127874] amdgpu :00:08.0: [gfxhub] no-retry page fault (src_id:0
ring:174 vmid:1 pasid:32768, for process amdgpu_test pid 1071 thread
amdgpu_test pid 1071)
[
On 5/7/19 1:24 PM, Christian König wrote:
Am 07.05.19 um 13:22 schrieb zhoucm1:
On 2019年05月07日 19:13, Koenig, Christian wrote:
Am 07.05.19 um 13:08 schrieb zhoucm1:
On 2019年05月07日 18:53, Koenig, Christian wrote:
Am 07.05.19 um 11:36 schrieb Chunming Zhou:
heavy gpu job could occupy
Am 07.05.19 um 13:37 schrieb Thomas Hellstrom:
> [CAUTION: External Email]
>
> On 5/7/19 1:24 PM, Christian König wrote:
>> Am 07.05.19 um 13:22 schrieb zhoucm1:
>>>
>>>
>>> On 2019年05月07日 19:13, Koenig, Christian wrote:
Am 07.05.19 um 13:08 schrieb zhoucm1:
>
> On 2019年05月07日 18:53,
On 2019年05月07日 18:53, Koenig, Christian wrote:
Am 07.05.19 um 11:36 schrieb Chunming Zhou:
heavy gpu job could occupy memory long time, which lead other user fail to get
memory.
basically pick up Christian idea:
1. Reserve the BO in DC using a ww_mutex ticket (trivial).
2. If we then run
Hi Trigger,
And see this interrupt is still from IH0 amdgpu_irq_handler, which can prove
this feature is not working under SR-IOV.
In this case this change is a clear NAK.
I suggest to remove this feature from SR-IOV, as my concern is, some weird
bugs may be cased by it in the
Am 07.05.19 um 13:08 schrieb zhoucm1:
>
>
> On 2019年05月07日 18:53, Koenig, Christian wrote:
>> Am 07.05.19 um 11:36 schrieb Chunming Zhou:
>>> heavy gpu job could occupy memory long time, which lead other user
>>> fail to get memory.
>>>
>>> basically pick up Christian idea:
>>>
>>> 1. Reserve the
heavy gpu job could occupy memory long time, which lead other user fail to get
memory.
basically pick up Christian idea:
1. Reserve the BO in DC using a ww_mutex ticket (trivial).
2. If we then run into this EBUSY condition in TTM check if the BO we need
memory for (or rather the ww_mutex of
add ticket for display bo, so that it can preempt busy bo.
Change-Id: I9f031cdcc8267de00e819ae303baa0a52df8ebb9
Signed-off-by: Chunming Zhou
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ++-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git
Am 07.05.19 um 11:36 schrieb Chunming Zhou:
> add ticket for display bo, so that it can preempt busy bo.
>
> Change-Id: I9f031cdcc8267de00e819ae303baa0a52df8ebb9
> Signed-off-by: Chunming Zhou
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ++-
> 1 file changed, 17
Am 07.05.19 um 13:22 schrieb zhoucm1:
On 2019年05月07日 19:13, Koenig, Christian wrote:
Am 07.05.19 um 13:08 schrieb zhoucm1:
On 2019年05月07日 18:53, Koenig, Christian wrote:
Am 07.05.19 um 11:36 schrieb Chunming Zhou:
heavy gpu job could occupy memory long time, which lead other user
fail to
On 2019年05月07日 19:13, Koenig, Christian wrote:
Am 07.05.19 um 13:08 schrieb zhoucm1:
On 2019年05月07日 18:53, Koenig, Christian wrote:
Am 07.05.19 um 11:36 schrieb Chunming Zhou:
heavy gpu job could occupy memory long time, which lead other user
fail to get memory.
basically pick up
OK, thanks for the detailed background, before I didn't know the limitation
in the hardware.
Thanks & Best Wishes,
Trigger Huang
-Original Message-
From: Christian König
Sent: Tuesday, May 07, 2019 5:04 PM
To: Huang, Trigger ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
Am 07.05.19 um 11:36 schrieb Chunming Zhou:
> heavy gpu job could occupy memory long time, which lead other user fail to
> get memory.
>
> basically pick up Christian idea:
>
> 1. Reserve the BO in DC using a ww_mutex ticket (trivial).
> 2. If we then run into this EBUSY condition in TTM check if
On Tue, May 7, 2019 at 2:09 AM Evan Quan wrote:
>
> Update Vega10 top performance level power state accordingly
> on OD.
>
> Change-Id: Iaadeefb2904222bf5f4d54b39d7179ce53f92ac0
> Signed-off-by: Evan Quan
Series is:
Acked-by: Alex Deucher
> ---
> .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c
Add EDC counter register to support gfx9 gpr EDC workaround to
clear all EDC counters.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
.../drm/amd/include/asic_reg/gc/gc_9_0_offset.h| 31 ++
1 file changed, 31 insertions(+)
diff --git
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and
resets EDC error counts. This is done in late_init, before
RAS TA GFX enable.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 245 ++
Am 07.05.19 um 19:30 schrieb Messinger, Ori:
Firmware versions can be found as separate sysfs files at:
/sys/class/drm/cardX/device/ (where X is the card number)
The firmware versions are displayed in hexadecimal.
Change-Id: I10cae4c0ca6f1b6a9ced07da143426e1d011e203
Signed-off-by: Ori Messinger
The debugfs won't have anything in it that this interface won't provide. It
does FW+VBIOS, and there will be separate files for each of those components.
From a housekeeping standpoint, should we make a subfolder called fw_version to
dump the files into, or are they fine in the base sysfs tree?
On 2019-05-06 12:30 p.m., Andrey Konovalov wrote:
> [CAUTION: External Email]
>
> This patch is a part of a series that extends arm64 kernel ABI to allow to
> pass tagged user pointers (with the top byte set to something else other
> than 0x00) as syscall arguments.
>
> In
On 2019-05-06 12:30 p.m., Andrey Konovalov wrote:
> [CAUTION: External Email]
>
> This patch is a part of a series that extends arm64 kernel ABI to allow to
> pass tagged user pointers (with the top byte set to something else other
> than 0x00) as syscall arguments.
>
> In
Firmware versions can be found as separate sysfs files at:
/sys/class/drm/cardX/device/ (where X is the card number)
The firmware versions are displayed in hexadecimal.
Change-Id: I10cae4c0ca6f1b6a9ced07da143426e1d011e203
Signed-off-by: Ori Messinger
---
Reviewed-by: Harish Kasiviswanathan
On 2019-05-06 4:23 p.m., Kuehling, Felix wrote:
> [CAUTION: External Email]
>
> Need to reserve space for the shared eviction fence when initializing
> a KFD VM.
>
> Signed-off-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4
On Wed, Mar 13, 2019 at 09:20:26PM -0300, Helen Koike wrote:
> In the case of a normal sync update, the preparation of framebuffers (be
> it calling drm_atomic_helper_prepare_planes() or doing setups with
> drm_framebuffer_get()) are performed in the new_state and the respective
> cleanups are
Use unsigned long for number of pages.
Check that pfns are valid after hmm_vma_fault. If they are not,
return an error instead of continuing with invalid page pointers and
PTEs.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 22 ++
1 file
Under Vega10 SR-IOV, with new RLC's new feature, VF should call RLC
to program some registers if supported
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 30 +++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 100 +++---
New feature for RLC, some registers can be programmed by
RLC interface under SR-IOV VF:
WREG32_SOC15_RLC_SHADOW:
1, for GRBM_GFX_CNTL, firstly the new register value should be be
programmed to SCRATCH_REG2
1, for GRBM_GFX_INDEX, firstly the new register value
To support new Vega10 SR-IOV L1 security, KMD need some modifications
1: Due to the new features supported in FW(PSP, RLC, etc),
for register access during initialization, we have more
modes:
1), request PSP to program
2), request RLC
call psp to progrm ih cntl in SR-IOV if supported
Change-Id: I466dd66926221e764cbcddca48b1f0fe5cd798b4
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 91 ++
1 file changed, 82 insertions(+), 9 deletions(-)
diff --git
For Vega10 SR-IOV VF, skip setting some regs due to:
1, host will program thme
2, avoid VF register programming violations
Change-Id: Id43e7fca7775035be47696c67a74ad418403036b
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 --
Add VMR ring support for Vega10 SR-IOV VF if PSP supported
Change-Id: I1990e4c9babdac95d9797e7870569c1c6f630585
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 131 +-
1 file changed, 99 insertions(+), 32 deletions(-)
diff --git
Add new PSP command GFX_CMD_ID_PROG_REG definition
Change-Id: I685baa2a219cac60417c2aa609cd3d6b9ff2b0cf
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
Add implementation to program regs by PSP, currently the following
IH registers are supported:
IH_RB_CNTL
IH_RB_CNTL_RING1
IH_RB_CNTL_RING2
Change-Id: I8e777f1080043066843d3962d3635e7075ecf21b
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 28
Set different register access mode according to the features
provided by firmware
Change-Id: Ia03e25a5a3b188f66363a0af487edfa21aafefc5
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 43
In order to support new PSP feature that PSP may provide interface
to program IH CNTL register, initialize PSP before IH under Vega10
SR-IOV VF
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 24
add badpages node.
it will output badpages list in format
page : size : flags
page is PFN.
flags can be R, P, F.
example
0x : 0x1000 : R
0x0001 : 0x1000 : R
0x0002 : 0x1000 : R
0x0003 : 0x1000 : R
0x0004 : 0x1000 : R
0x0005 : 0x1000 : R
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