RE: [PATCH] drm/amdgpu: Need to set the baco cap before baco reset

Thanks Emily, this fixed the issue. Verified-By: Kent Russell Kent -Original Message- From: Deng, Emily Sent: Sunday, June 16, 2019 11:53 PM To: Yang, Philip ; Russell, Kent ; Quan, Evan ; amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amdgpu: Need to set the baco cap before

Re: [PATCH] drm/amd/display: include missing linux/delay.h

Hi Arnd. On Mon, Jun 17, 2019 at 02:38:55PM +0200, Arnd Bergmann wrote: > Some randconfig builds fail to compile the dcn10 code because of > a missing declaration: > > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In > function 'dcn10_apply_ctx_for_surface': >

Re: [PATCH] drm/amd/display: include missing linux/delay.h

On Mon, Jun 17, 2019 at 4:41 PM Sam Ravnborg wrote: > On Mon, Jun 17, 2019 at 02:38:55PM +0200, Arnd Bergmann wrote: > > Some randconfig builds fail to compile the dcn10 code because of > > a missing declaration: > > > > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In > >

RE: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init

Thanks Alex, I am testing it out now. Kent -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Monday, June 17, 2019 10:45 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init We need the

[PATCH 5/6] drm/amdgpu: add independent DMA-buf export v6

The caching of SGT's is actually quite harmful and should probably removed altogether when all drivers are audited. Start by providing a separate DMA-buf export implementation in amdgpu. This is also a prerequisite of unpinned DMA-buf handling. v2: fix unintended recursion, remove debugging

[PATCH 1/6] dma-buf: add dynamic DMA-buf handling v10

On the exporter side we add optional explicit pinning callbacks. If those callbacks are implemented the framework no longer caches sg tables and the map/unmap callbacks are always called with the lock of the reservation object held. On the importer side we add an optional invalidate callback.

[PATCH 2/6] drm/ttm: remove the backing store if no placement is given

Pipeline removal of the BOs backing store when no placement is given during validation. Signed-off-by: Christian König --- drivers/gpu/drm/ttm/ttm_bo.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index

[PATCH 4/6] drm/amdgpu: use allowed_domains for exported DMA-bufs

Avoid that we ping/pong the buffers when we stop to pin DMA-buf exports by using the allowed domains for exported buffers. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[PATCH 6/6] drm/amdgpu: add independent DMA-buf import v6

Instead of relying on the DRM functions just implement our own import functions. This prepares support for taking care of unpinned DMA-buf. v2: enable for all exporters, not just amdgpu, fix invalidation handling, lock reservation object while setting callback v3: change to new dma_buf attach

[PATCH 3/6] drm/ttm: use the parent resv for ghost objects v2

This way we can even pipeline imported BO evictions. v2: Limit this to only cases when the parent object uses a separate reservation object as well. This fixes another OOM problem. Signed-off-by: Christian König --- drivers/gpu/drm/ttm/ttm_bo_util.c | 20 +++- 1 file

Re: [PATCH] drm/amd/display: Add missing newline at end of file

On Mon, Jun 17, 2019 at 10:45 AM Geert Uytterhoeven wrote: > > "git diff" says: > > \ No newline at end of file > > after modifying the file. > > Signed-off-by: Geert Uytterhoeven Applied. thanks! Alex > --- > drivers/gpu/drm/amd/display/modules/power/Makefile | 2 +- > 1 file changed,

RE: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init

Thanks, I need to get familiar with all of the tags  Kent From: Deucher, Alexander Sent: Monday, June 17, 2019 11:24 AM To: Russell, Kent ; Alex Deucher ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init I'll make that a

[PATCH] drm/amd/display: Delete a redundant memory setting in amdgpu_dm_irq_register_interrupt()

From: Markus Elfring Date: Mon, 17 Jun 2019 13:56:39 +0200 The memory was set to zero already by a call of the function “kzalloc”. Thus remove an extra call of the function “memset” for this purpose. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring ---

[PATCH] drm/amd/display: include missing linux/delay.h

Some randconfig builds fail to compile the dcn10 code because of a missing declaration: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function 'dcn10_apply_ctx_for_surface': drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2378:3: error: implicit

[PATCH] drm/amdgpu: fix error handling in df_v3_6_pmc_start

When df_v3_6_pmc_get_ctrl_settings() fails for some reason, we store uninitialized data in a register, as gcc points out: drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function 'df_v3_6_pmc_start': drivers/gpu/drm/amd/amdgpu/amdgpu.h:1012:29: error: 'lo_val' may be used uninitialized in this function

[PATCH] drm/amd/display: Add missing newline at end of file

"git diff" says: \ No newline at end of file after modifying the file. Signed-off-by: Geert Uytterhoeven --- drivers/gpu/drm/amd/display/modules/power/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile

Re: [PATCH] drm/amdgpu: fix error handling in df_v3_6_pmc_start

On Mon, Jun 17, 2019 at 8:57 AM Arnd Bergmann wrote: > > When df_v3_6_pmc_get_ctrl_settings() fails for some reason, we > store uninitialized data in a register, as gcc points out: > > drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function 'df_v3_6_pmc_start': >

RE: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init

This also worked. I don't think that I'm qualified enough to RB it, but you can add my Verified-By: Kent Russell Kent -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Monday, June 17, 2019 10:45 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject:

Re: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init

I'll make that a tested-by. Thanks! Alex From: Russell, Kent Sent: Monday, June 17, 2019 11:14 AM To: Alex Deucher; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: RE: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init This also

Re: [PATCH v17 03/15] arm64: Introduce prctl() options to control the tagged user addresses ABI

On Wed, Jun 12, 2019 at 01:43:20PM +0200, Andrey Konovalov wrote: > From: Catalin Marinas > > It is not desirable to relax the ABI to allow tagged user addresses into > the kernel indiscriminately. This patch introduces a prctl() interface > for enabling or disabling the tagged ABI with a global

RE: [PATCH] drm/amdgpu: Need to set the baco cap before baco reset

The issue was limited to one specific model of MI25, I'll see if I can get access to that later today and try your patch out. Thank you Emily! Kent -Original Message- From: Deng, Emily Sent: Sunday, June 16, 2019 11:53 PM To: Yang, Philip ; Russell, Kent ; Quan, Evan ;

[PATCH 116/459] drm/amdgpu: add JPEG2.0 decode ring ib test

From: Leo Liu Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 000/459] amdgpu support for Navi10

Hi, This patch set adds support for Navi10 asics to amdgpu. This includes support for: - Core driver support - Displays (DCN2) - GFX and compute (GFX10) - System DMA (SDMA 5) - Multimedia decode and encode (VCN2) - Power management The new register headers are huge, so I have not sent them out.

[PATCH 108/459] drm/amdgpu: disable concurrent flushes for Navi10 v2

From: Christian König Navi10 have a bug in the SDMA which can theoretically cause memory corruption with concurrent VMID flushes v2: explicitely check Navi10 Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 7

[PATCH 102/459] drm/amdgpu/discovery: fix hwid for nbio

From: Xiaojie Yuan Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

[PATCH 116/459] drm/amdgpu: add JPEG2.0 decode ring ib test

From: Leo Liu Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 105/459] drm/amdgpu/discovery: stop converting the units of base addresses

From: Xiaojie Yuan the unit is already in dword Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH 114/459] drm/amdgpu: add VCN2.0 decode ib test

From: Leo Liu Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +-

[PATCH 101/459] drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZE

From: Xiaojie Yuan register base offset of nbio is not known before IP Discovery table is parsed, so hardcode this value. Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 12 ++-- 1 file changed, 6

[PATCH 103/459] drm/amdgpu/discovery: stop taking psp header into account

From: Xiaojie Yuan psp will write a header to vram, but the value exposed in RCC_CONFIG_MEMSIZE does not include the memory that this header is written to. Therefore, the interpretation of the table does not need to take the psp header into account. Signed-off-by: Xiaojie Yuan Reviewed-by:

[PATCH 104/459] drm/amdgpu/discovery: update definition for struct die_header

From: Xiaojie Yuan Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/discovery.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/discovery.h

[PATCH 117/459] drm/amdgpu: add initial VCN2.0 support (v2)

From: Leo Liu VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Reviewed-by: James Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile |

Re: [PATCH] drm/amd/amdgpu: cast mem->num_pages to 64-bits when shifting

Reviewed-by: Christian König Am 17.06.19 um 20:21 schrieb Tom St Denis: ping? On Fri, Jun 14, 2019 at 12:51 PM StDenis, Tom > wrote: On 32-bit hosts mem->num_pages is 32-bits and can overflow when shifted.  Add a cast to avoid this. Signed-off-by:

[PATCH 312/459] drm/amd/powerplay: notify smu with active display count

From: hersen wu when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by: hersen wu Reviewed-by: Huang Rui Acked-by: Alex Deucher Signed-off-by: Alex Deucher ---

[PATCH 327/459] drm/amd/display: Add DCN2 DPP

From: Harry Wentland Add support to program the DCN2 DPP (Multiple pipe and plane combine) HW Blocks: ++ | DPP | ++ | v ++ | MPC | ++ | v +---+ | OPP | +---+ | v

[PATCH 331/459] drm/amd/display: Add DCN2 IPP

From: Harry Wentland Add support to program DCN2 cursor (IPP) Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 24 +++ .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 43 +++ 2 files changed, 67

[PATCH 320/459] drm/amd/display: Add DCN2 IRQ handling

From: Harry Wentland Add support to program DCN2 IRQ handling Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 + .../display/dc/irq/dcn20/irq_service_dcn20.c | 361 ++

[PATCH 316/459] drm/amd/display: Add DCN2 and NV ASIC ID

From: Harry Wentland DCN2.0 (Display Core Next) is the display block in Navi10. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/include/dal_asic_id.h | 25 +++ .../gpu/drm/amd/display/include/dal_types.h | 3 +++ 2 files changed, 28

[PATCH 319/459] drm/amd/display: Add DCN2 BIOS parsing

From: Harry Wentland Handle BIOS parsing for DCN2 Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 4 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 6 ++ 2 files changed, 10 insertions(+)

[PATCH 339/459] drm/amd/display: updates for dcn20_update_bandwidth

Pass extra parameter to validate_bandwidth() callback. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

[PATCH 334/459] drm/amd/display: Add DC core changes for DCN2

From: Harry Wentland Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/Makefile | 6 + drivers/gpu/drm/amd/display/dc/core/dc.c | 141 - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-

[PATCH 340/459] drm/amd/display: update dcn2 dc_plane_cap

To deal with rebasing the code. Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 21 --- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

[PATCH 337/459] drm/amd/display: hook navi10 pplib functions

From: hersen wu during bring up time, before window dc-ppplib interface design, linux dc use raven dc-pplib interface. now nvai10 dc-pplib-smu interface is changed and verified under window, navi10 need its specific dc-pplib-smu interface. todo: hook set_hard_min_uclk_by_freq,

[PATCH 338/459] drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth

To deal with changes from rebasing. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git

[PATCH 342/459] drm/amdgpu: Enable DC support for Navi10

From: Harry Wentland Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ drivers/gpu/drm/amd/amdgpu/nv.c| 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

[PATCH 341/459] drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)

From: Harry Wentland Enable DCN2 support in DM (Display Manager). v2: fix spurious raven change (Alex) Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig| 9 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14

[PATCH 325/459] drm/amd/display: Add DCN2 OPP

From: Harry Wentland Add support to program the DCN2 OPP (Output Plane Processing) HW Blocks: +---+ | OPP | +---+ | v ++ | OPTC | ++ | v ++ ++ | DIO | | DCCG |

[PATCH 318/459] drm/amd/display: Add GPIO support for DCN2

From: Harry Wentland Adding support to program GPIO HW block of DCN2 Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 + .../display/dc/gpio/dcn20/hw_factory_dcn20.c | 212 ++

[PATCH 336/459] drm/amd/powerplay: add interface to get uclk dpm table

From: hersen wu dc needs get uclk dpm table for bandwidth calculation Signed-off-by: hersen wu Acked-by: Alex Deucher Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 1 file changed, 4 insertions(+) diff --git

[PATCH 303/459] drm/amdgpu/gfx10: update to latest golden setting

Fix UTCL1_CGTT_CLK_CTRL Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index ae3d868de308..779597a6f33a 100644 ---

[PATCH 335/459] drm/amd/powrplay: add interface for dc to get max clock values

From: hersen wu dc (display component) needs maximum clock values of uclock, socclk, dcefclk, to calculate display bandwidth. Signed-off-by: hersen wu Acked-by: Alex Deucher Reviewed-by: Huang Rui --- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 4 +++

[PATCH 324/459] drm/amd/display: Add DCN2 OPTC

From: Harry Wentland Add support for programming the DCN2 OPTC (Output Timing Controller) HW Blocks: ++ | OPTC | ++ | v ++ ++ | DIO | | DCCG | ++ ++ Signed-off-by: Harry Wentland

[PATCH 346/459] drm/amd/display: Ensure DRR triggers in BP

From: Eryk Brol [Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove

[PATCH 349/459] drm/amd/display: Move link functions from dc to dc_link

From: Chris Park [Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by: Chris Park Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 +++ 1 file changed, 27

[PATCH 347/459] drm/amd/display: disable PSR/ABM before destroy DMCU struct

From: Paul Hsieh [Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should

[PATCH 366/459] drm/amd/display: Calculate link bandwidth in a common function

From: Nikola Cornij [why] Currently link bandwidth is calculated in various places using the same multi-step formula. Doing this in one common place makes sure the same formula will indeed be applied to all link bandwidth calculations. It also makes it possible to apply link-setting-specific

[PATCH 378/459] drm/amd/display: Make sure DSC slice height is divisible by 2 for 4:2:0 color format

From: Nikola Cornij [why] DSC spec requires this Signed-off-by: Nikola Cornij Reviewed-by: Wenjing Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git

[PATCH 362/459] drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()

From: Leo Li [Why] dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra lock unnecessary. In addition - during full plane updates - all necessary pipes should be locked/unlocked together when modifying hubp to avoid tearing in pipesplit setups. [How] Remove redundant locks,

[PATCH 384/459] drm/amd/display: Guard DML_FAIL_DSC_VALIDATION_FAILURE

From: Leo Li [Why] Usage of this enum is DSC-only. [How] Guard it with CONFIG_DRM_AMD_DC_DSC_SUPPORT. Signed-off-by: Leo Li Reviewed-by: Harry Wentland Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h | 2 ++ 1 file

[PATCH 363/459] drm/amd/display: fixed DCC corruption

From: Bob Yang [Description] swath_bytes_horz_wc should be 256/64/64 for 2160p 32bpp surface Signed-off-by: Bob Yang Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH 365/459] drm/amd/display: Add a flags union for 3dlut transformation matrix

From: Vitaly Prosyak [Why & How] When TM is enabled with 3dlut, we apply conversion to dcip3 in gamut remap matrix, if source area less than dcip3. If it is bigger, we remap to bt2020. The added flags will be used to facilitate this logic. Signed-off-by: Vitaly Prosyak Reviewed-by: Aric Cyr

[PATCH 369/459] drm/amd/display: fix dsc validation

From: Dmytro Laktyushkin Currently dsc is validated not taking the image width limitation into mind. This change addresses that, but due to previous design being limited to non odm dsc validation additional sequence changes are made. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Nikola

[PATCH 382/459] drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE failed.

From: Charlene Liu [Why] Can not turn on two displays at the same time with the asic having only one DSC. DC_DSC_RESOURCE allocation failed. [Solution] Only add_dsc if the timing is dsc capable based on diag_dc and num_dsc Signed-off-by: Charlene Liu Reviewed-by: Wesley Chalmers Acked-by:

[PATCH 353/459] drm/amd/display: Add writeback_config to VBA vars

From: Ilya Bakoulin Adding writeback_config enum to vba_vars_st, replacing old flag. Initialize to dm_normal. Signed-off-by: Ilya Bakoulin Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +

[PATCH 385/459] drm/amd/display: Properly guard display_mode_vba with DCN2

From: Leo Li [Why] display_mode_vba is for DCN2 and up. When building for upstream (DCN1 enabled only), there will be a build error, since display_mode_vba.c/h is stripped out. Note that building DCN1 only with internal dal-dev is still fine, since display_mode_vba.h is not stripped out

[PATCH 360/459] drm/amd/display: enable DSC support by default

From: Hawking Zhang Signed-off-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 9cb2211edf4c..33e7efbb4ef4

[PATCH 371/459] drm/amd/display: remove legacy DSC functions

From: Wenjing Liu [why] Clean up some dsc legacy functions that are no longer needed. [how] remove two dsc functions in dc_dsc, use dc_bandwidth_in_kbps_from_timing instead of calc_required_bandwidth_for_timing. Signed-off-by: Wenjing Liu Reviewed-by: Nikola Cornij Acked-by: Leo Li

[PATCH 372/459] drm/amd/display: remove target_dpp hack for dsc

From: Wenjing Liu Remove dc_dsc hack for MST policy Signed-off-by: Wenjing Liu Reviewed-by: Nikola Cornij Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 27 + 1 file changed, 6 insertions(+), 21 deletions(-)

[PATCH 364/459] drm/amd/display: clean up validation failure log spam

From: Dmytro Laktyushkin Currently dcn2+ validation will unconditionally print a failure reason before validation completes. This change categorizes the failure reason as a warning log and only prints at the end of validation resolving false positives. Signed-off-by: Dmytro Laktyushkin

[PATCH 377/459] drm/amd/display: Use 1/8th DSC target bitrate precision for N4:2:2 and 4:2:0 formats

From: Nikola Cornij [why] On at least some of the devices (e.g. Realtek scaler) we get a black screen if 1/16th precision is used. [how] Work around it by reducing precision to 1/8th for N4:2:2 and 4:2:0 color formats. This is a safe workaround and would have a very mild impact on the

[PATCH 379/459] drm/amd/display: Add some tm3dlut flags

From: Vitaly Prosyak Move flags from color_gamma.h to mod_shared.h and add more options and setting structures Signed-off-by: Vitaly Prosyak Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher ---

[PATCH 373/459] drm/amd/display: fix fpga fclk programming

From: Dmytro Laktyushkin We shouldnt need overhead on top of dppclk when setting fclk. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Eric Bernstein Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 ++--- 1 file

[PATCH 380/459] drm/amd/display: DCN2 reg refactors

From: Yongqiang Sun Added some regs and exposed some functions for future use Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 +-

[PATCH 375/459] drm/amd/display: Remove additional FEC link bandwidth reduction

From: Nikola Cornij [why] This is now done in the original link bandwidth calculation and DSC must not do this anymore. [how] Remove the line of code that should have been removed when transition to correctly applying FEC overhead was made. Signed-off-by: Nikola Cornij Reviewed-by: Wenjing

[PATCH 359/459] drm/amd/display: navi10 bring up skip dsc encoder config

From: hersen wu Signed-off-by: hersen wu Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c

[PATCH 368/459] drm/amd/display: Properly set u clock

From: Aidan Wood [Why] u clk set request was being sent in units of mts, when it needed to be in units of Mhz [How] add a division by 16 to convert from mts to Mhz Signed-off-by: Aidan Wood Reviewed-by: Jun Lei Acked-by: Leo Li Signed-off-by: Alex Deucher ---

[PATCH 376/459] drm/amd/display: isolate global double buffer lock programming

From: Wenjing Liu [why] Global optic double buffer lock is currently disabled due to incorrect programming sequence that affects non global lock. [how] Isolate global lock programming sequence out of non global lock programming sequence, so it can be enabled without affecting non global lock.

[PATCH 352/459] drm/amd/display: Refactor clk_mgr functions

From: Eric Yang [Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] - Pull get_active_display_cnt out to clk_mgr. - Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Leo Li Signed-off-by: Alex Deucher

[PATCH 367/459] drm/amd/display: Properly set DCF clock

From: Aidan Wood [Why] If num_states == 0 we did update_bound_box which doesn't updated any max clocks if num_states == 0, therefore we need to do cap_soc_clocks instead, also SMU cannot set DCF clock to a higher than or equal to freq than SOC clock [How] Add a num_states != 0 check for

[PATCH 348/459] drm/amd/display: update calculated bounding box logic for NV

From: Jun Lei [why] Current calculation of bounding box will cause DML to increase voltage state due to DPP or DISPCLK, this is unnecessary since from DML perspective we can max DPP/DISP can be supported at DPM0. This is because increasing voltage for DPP/DISP is done separately via actual

[PATCH 354/459] drm/amd/display: fix pstate allow handling in dcn2

From: Jun Lei [why] pstate allow/block is not being handled properly on DCN2 [how] DML needs to be updated to calculate pstate support at both min and max mpc combine rather than just min clock manager needs to update current to new pstate support before sending to pplib/smu Signed-off-by: Jun

[PATCH 356/459] drm/amd/display: disable dcn20 abm feature for bring up

From: hersen wu [WHY] dcn20 enable usb-c dp ALT mode in dmcu. There is bug when enable abm feature which cause system crash. dal team will debug this bug later. [HOW] disable dcn abm feature for dcn20. Signed-off-by: hersen wu Signed-off-by: Alex Deucher ---

[PATCH 344/459] drm/amd/display: Program VTG params after programming Global Sync for DCN2

From: Joshua Aberback [Why] VTG has a parameter FP2, which is defined as: if VSTARTUP is before VSYNC: FP2 = number of lines in between VSTARTUP and VSYNC else FP2 = 0 Currently, FP2 is only programmed during "program_timing". However, the position of VSTARTUP is affected

[PATCH 357/459] drm/amd/display: do not need otg lock if otg is not active

From: hersen wu [todo] need find caller bug. tempooariy fix Signed-off-by: hersen wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git

[PATCH 350/459] drm/amd/display: do not power on eDP power rail early

From: Anthony Koo [Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high.

[PATCH 370/459] drm/amd/display: Remove dependency on pipe->plane for immedaite flip status

From: Joshua Aberback [Why] dcn20_apply_ctx_for_surface can be called with 0 planes, which means we should blank the display. In this case when we get down to dcn20_setup_gsl_group_as_lock, pipe_ctx->plane_state is NULL, but we don't check for it. However, this function is only called by

[PATCH 381/459] drm/amd/display: Fix DCFCLK and SOCCLK not set

From: Ilya Bakoulin [Why] If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML calculations, which ended up causing an assert. [How] Initialize dcfclk_mhz and socclk_mhz values according to the voltage level. Signed-off-by: Ilya Bakoulin Reviewed-by: Dmytro Laktyushkin Acked-by:

[PATCH 374/459] drm/amd/display: move dsc clock from plane_resource to stream_resource

From: Tony Cheng Signed-off-by: Tony Cheng Reviewed-by: Dmytro Laktyushkin Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 ++--- 2 files changed, 3

[PATCH 361/459] drm/amd/display: Disconnect DCN2 mpcc when changing tg

From: Leo Li A previous fix was done for DCN1 that needed to be ported to DCN2: 60c677534e73 ("drm/amd/display: Disconnect mpcc when changing tg") Signed-off-by: Leo Li Acked-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 --- 1

[PATCH 358/459] drm/amd/display: skip dsc config for navi10 bring up

From: hersen wu [why] we meet a bug when program dsc register even dsc mode is not enabled. disable dsc config for now. we will re-visit this issue. Signed-off-by: hersen wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 +

[PATCH 031/459] drm/amdgpu: add nbio callbacks for vcn doorbell support

From: Leo Liu For Navi10 VCN2.0, the engine supports Doorbell Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h

[PATCH 030/459] drm/amdgpu: query vram_width from vram_info table

From: Hawking Zhang Driver will get channel_number and channel_width from vram_info table, then calculate vram_width by multiply channel_number by channel_width Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Reviewed-by: Jack Xiao Signed-off-by: Alex Deucher ---

[PATCH 032/459] drm/amdgpu: add nbio v2.3 for navi10 (v3)

From: Hawking Zhang nbio handles bus io functionality. v1: add place holder and initial basic nbio v2.3 functions (Ray) v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking) v3: squash in updates (Alex) Signed-off-by: Huang Rui Signed-off-by: Hawking Zhang

[PATCH 038/459] drm/amdgpu: add helper function for gfx queue/bitmap transition

From: Hawking Zhang Signed-off-by: Hawking Zhang Reviewed-by: Jack Xiao Reviewed-by: Alex Deucher Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 42 ++

[PATCH 025/459] drm/amdgpu: add v10 structs header (v2)

From: Huang Rui Header for CP structures (MQD, etc.) V2: squash in updates Signed-off-by: Huang Rui Acked-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/v10_structs.h | 1258 + 1 file changed, 1258 insertions(+) create mode 100644

[PATCH 028/459] drm/amdgpu: add navi pm4 header

From: Hawking Zhang A pm4 header for Navi. PM4 is the packet format used by the compute and gfx engines. Signed-off-by: Huang Rui Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nvd.h | 418

[PATCH 043/459] drm/amdgpu/gfx10: add special unmap_queues packet for preemption

From: Jack Xiao CP introduced a special unmap_queues packet for gfx preemtion. Acked-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Jack Xiao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 11

[PATCH 051/459] drm/amdgpu: correct pte mtype field for navi

From: Hawking Zhang The MTYPE filed moves from bits 58:57 to 50:48 for NV10 And the size of MTYPE field is now 3bits Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 9 +++--

[PATCH 042/459] drm/amdgpu: Move common code to amdgpu_gfx.c

From: Hawking Zhang move common code to amdgpu_gfx_enable_kcq,so this function can be shared with gfx8 and gfx9 Signed-off-by: Hawking Zhang Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

[PATCH 047/459] drm/amdgpu: create mqd for gfx queues on navi10

From: Hawking Zhang Signed-off-by: Hawking Zhang Reviewed-by: Jack Xiao Reviewed-by: Alex Deucher Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 35 - 1 file changed, 34 insertions(+), 1 deletion(-) diff --git

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