RE: [PATCH] drm/amd/powerplay: clear VBIOS scratchs on baco exit

[Quan, Evan]

Hi Xiaojie,

This was reported by Zhigang team.  Under their special use case, scratch 
register 7 has be to 0 to perform asic init(@Luo, Zhigang right?).
And considering old asics(vega20/10) also applied this change.
So, I think it's reasonable(and recommend by SMU fw team) to apply this on the 
new ASICs also.

Regards,
Evan
> -Original Message-
> From: Yuan, Xiaojie 
> Sent: Friday, December 6, 2019 12:20 PM
> To: Quan, Evan 
> Cc: amd-gfx@lists.freedesktop.org; Luo, Zhigang 
> Subject: Re: [PATCH] drm/amd/powerplay: clear VBIOS scratchs on baco exit
> 
> Hi Evan,
> 
> Just out of curiosity, may I know what issue are you trying to fix?
> I used to see vbios post failure (hangs in atombios init table) after baco 
> exit
> occasionally on navi.
> 
> BR,
> Xiaojie
> 
> > On Dec 6, 2019, at 11:37 AM, Evan Quan  wrote:
> >
> > This is needed for coming asic init on performing gpu reset.
> >
> > Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
> > Signed-off-by: Evan Quan 
> > ---
> > drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> > index 39ec06aee809..ab809df7bc35 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> > @@ -1659,6 +1659,12 @@ int smu_v11_0_baco_set_state(struct
> smu_context *smu, enum smu_baco_state state)
> >}
> >} else {
> >ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
> > +if (ret)
> > +goto out;
> > +
> > +WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_6, 0);
> > +WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_7, 0);
> > +
> >bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
> >BIF_DOORBELL_INT_CNTL,
> >DOORBELL_INTERRUPT_DISABLE, 0);
> > --
> > 2.24.0
> >
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[PATCH 3/3] tests/amdgpu: Fix buffer overflow

[Luben Tuikov]

This patch fixes the following warning:
-Wformat-overflow=

Signed-off-by: Luben Tuikov 
---
 tests/amdgpu/meson.build |  1 +
 tests/amdgpu/ras_tests.c | 41 
 2 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 2a48b43f..faaf0ee6 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -28,6 +28,7 @@ if dep_cunit.found()
 ),
 dependencies : [dep_cunit, dep_threads],
 include_directories : [inc_root, inc_drm, 
include_directories('../../amdgpu')],
+link_args : ['-lbsd'],
 link_with : [libdrm, libdrm_amdgpu],
 install : with_install_tests,
   )
diff --git a/tests/amdgpu/ras_tests.c b/tests/amdgpu/ras_tests.c
index 4c395382..9c206e40 100644
--- a/tests/amdgpu/ras_tests.c
+++ b/tests/amdgpu/ras_tests.c
@@ -30,6 +30,10 @@
 #include 
 #include 
 #include "xf86drm.h"
+#include 
+#include 
+
+#define PATH_SIZE PATH_MAX
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
@@ -498,7 +502,7 @@ static int get_file_contents(char *file, char *buf, int 
size);
 
 static int amdgpu_ras_lookup_id(drmDevicePtr device)
 {
-   char path[1024];
+   char path[PATH_SIZE];
char str[128];
drmPciBusInfo info;
int i;
@@ -525,8 +529,8 @@ static int amdgpu_ras_lookup_id(drmDevicePtr device)
 //helpers
 
 static int test_card;
-static char sysfs_path[1024];
-static char debugfs_path[1024];
+static char sysfs_path[PATH_SIZE];
+static char debugfs_path[PATH_SIZE];
 static uint32_t ras_mask;
 static amdgpu_device_handle device_handle;
 
@@ -605,10 +609,11 @@ static int amdgpu_ras_is_feature_supported(enum 
amdgpu_ras_block block)
 
 static int amdgpu_ras_invoke(struct ras_debug_if *data)
 {
-   char path[1024];
+   char path[PATH_SIZE];
int ret;
 
-   sprintf(path, "%s%s", get_ras_debugfs_root(), "ras_ctrl");
+   snprintf(path, sizeof(path), "%s", get_ras_debugfs_root());
+   strlcpy(path, "ras_ctrl", sizeof(path));
 
ret = set_file_contents(path, (char *)data, sizeof(*data))
- sizeof(*data);
@@ -619,14 +624,16 @@ static int amdgpu_ras_query_err_count(enum 
amdgpu_ras_block block,
unsigned long *ue, unsigned long *ce)
 {
char buf[64];
-   char name[1024];
+   char name[PATH_SIZE];
 
*ue = *ce = 0;
 
if (amdgpu_ras_is_feature_supported(block) <= 0)
return -1;
 
-   sprintf(name, "%s%s%s", get_ras_sysfs_root(), ras_block_str(block), 
"_err_count");
+   snprintf(name, sizeof(name), "%s", get_ras_sysfs_root());
+   strlcpy(name, ras_block_str(block), sizeof(name));
+   strlcpy(name, "_err_count", sizeof(name));
 
if (is_file_ok(name, O_RDONLY))
return 0;
@@ -839,7 +846,7 @@ static void amdgpu_ras_basic_test(void)
int i;
int j;
uint32_t features;
-   char path[1024];
+   char path[PATH_SIZE];
 
ret = is_file_ok("/sys/module/amdgpu/parameters/ras_mask", O_RDONLY);
CU_ASSERT_EQUAL(ret, 0);
@@ -851,11 +858,15 @@ static void amdgpu_ras_basic_test(void)
sizeof(features), );
CU_ASSERT_EQUAL(ret, 0);
 
-   sprintf(path, "%s%s", get_ras_debugfs_root(), "ras_ctrl");
+   snprintf(path, sizeof(path), "%s", get_ras_debugfs_root());
+   strlcpy(path, "ras_ctrl", sizeof(path));
+
ret = is_file_ok(path, O_WRONLY);
CU_ASSERT_EQUAL(ret, 0);
 
-   sprintf(path, "%s%s", get_ras_sysfs_root(), "features");
+   snprintf(path, sizeof(path), "%s", get_ras_sysfs_root());
+   strlcpy(path, "features", sizeof(path));
+
ret = is_file_ok(path, O_RDONLY);
CU_ASSERT_EQUAL(ret, 0);
 
@@ -867,11 +878,17 @@ static void amdgpu_ras_basic_test(void)
if (!((1 << j) & ras_block_mask_basic))
continue;
 
-   sprintf(path, "%s%s%s", get_ras_sysfs_root(), 
ras_block_str(j), "_err_count");
+   snprintf(path, sizeof(path), "%s", 
get_ras_sysfs_root());
+   strlcpy(path, ras_block_str(j), sizeof(path));
+   strlcpy(path, "_err_count", sizeof(path));
+
ret = is_file_ok(path, O_RDONLY);
CU_ASSERT_EQUAL(ret, 0);
 
-   sprintf(path, "%s%s%s", get_ras_debugfs_root(), 
ras_block_str(j), "_err_inject");
+   snprintf(path, sizeof(path), "%s", 
get_ras_debugfs_root());
+   strlcpy(path, ras_block_str(j), sizeof(path));
+   strlcpy(path, "_err_inject", sizeof(path));
+
ret = is_file_ok(path, O_WRONLY);
CU_ASSERT_EQUAL(ret, 0);
}
-- 
2.24.0.155.gd9f6f3b619

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[PATCH 2/3] tests/amdgpu: Fix unused function warning

[Luben Tuikov]

This patch fixes:
-Wunused-function

Signed-off-by: Luben Tuikov 
---
 tests/amdgpu/ras_tests.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/ras_tests.c b/tests/amdgpu/ras_tests.c
index d714be73..4c395382 100644
--- a/tests/amdgpu/ras_tests.c
+++ b/tests/amdgpu/ras_tests.c
@@ -709,6 +709,7 @@ static void amdgpu_ras_disable_test(void)
}
 }
 
+#ifdef AMDGPU_RAS_TEST
 static void amdgpu_ras_enable_test(void)
 {
int i;
@@ -717,6 +718,7 @@ static void amdgpu_ras_enable_test(void)
amdgpu_ras_features_test(1);
}
 }
+#endif
 
 static void __amdgpu_ras_ip_inject_test(const struct ras_inject_test_config 
*ip_test,
uint32_t size)
@@ -881,7 +883,7 @@ CU_TestInfo ras_tests[] = {
{ "ras query test", amdgpu_ras_query_test },
{ "ras inject test",amdgpu_ras_inject_test },
{ "ras disable test",   amdgpu_ras_disable_test },
-#if 0
+#ifdef AMDGPU_RAS_TEST
{ "ras enable test",amdgpu_ras_enable_test },
 #endif
CU_TEST_INFO_NULL,
-- 
2.24.0.155.gd9f6f3b619

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[PATCH 1/3] tests/amdgpu: Fix various warnings

[Luben Tuikov]

This patch fixes the following warnings:
-Wformat=
-Wmaybe-uninitialized
-Wmisleading-indentation
-Wstringop-truncation
-Wunused-function
-Wunused-variable

It also removes forward declarations and moves
global functions to the bottom, keeping locals
at the top, in ras_tests.c.

Signed-off-by: Luben Tuikov 
---
 amdgpu/amdgpu_bo.c   |   2 -
 tests/amdgpu/basic_tests.c   |   7 +-
 tests/amdgpu/bo_tests.c  |   9 +-
 tests/amdgpu/cs_tests.c  |   1 +
 tests/amdgpu/ras_tests.c | 241 +--
 tests/amdgpu/syncobj_tests.c |   2 +-
 6 files changed, 124 insertions(+), 138 deletions(-)

diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index c54687ed..d6ea0e74 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -396,7 +396,6 @@ unlock:
 drm_public int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id)
 {
drmModeResPtr mode_res;
-   int count_crtcs;
drmModeCrtcPtr mode_crtc;
int current_id = 0;
int r = 0;
@@ -421,7 +420,6 @@ drm_public int amdgpu_get_fb_id(amdgpu_device_handle dev, 
unsigned int *fb_id)
if (!mode_res)
return EFAULT;
 
-   count_crtcs = mode_res->count_crtcs;
for (i = 0; i < mode_res->count_crtcs; i++) {
mode_crtc = drmModeGetCrtc(fd, mode_res->crtcs[i]);
if (mode_crtc) {
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index c3c09702..cce0640a 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -3231,7 +3231,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle 
device_handle,
int bo_cmd_size = 4096;
struct amdgpu_cs_request ibs_request = {0};
struct amdgpu_cs_ib_info ib_info= {0};
-   uint32_t hang_state, hangs, expired;
+   uint32_t expired;
amdgpu_bo_list_handle bo_list;
struct amdgpu_cs_fence fence_status = {0};
 
@@ -3479,10 +3479,11 @@ amdgpu_direct_gma_bo_alloc_and_map(amdgpu_device_handle 
dev, amdgpu_device_handl
goto error_va_map;
}
 
-   if (cpu)
+   if (cpu) {
r = amdgpu_bo_cpu_map(buf_handle_import, cpu);
if(r)
goto error_va_map;
+   }
 
*bo = buf_handle;
*bo_peer = buf_handle_import;
@@ -3610,7 +3611,7 @@ static void amdgpu_direct_gma_mmap(amdgpu_device_handle 
dev,
amdgpu_bo_handle *buf_handle_import;
volatile uint8_t **ptr;
struct drm_amdgpu_capability cap;
-   uint64_t size = 4096, phys_addr, remain;
+   uint64_t size = 4096, remain;
int i, j, r, tst_loop = 20;
 
buf_handle = calloc(tst_loop, sizeof(*buf_handle));
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 27048c88..7fcabb85 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -325,8 +325,7 @@ static void amdgpu_bo_find_by_cpu_mapping(void)
 }
 static void amdgpu_get_fb_id_and_handle(void)
 {
-   uint32_t *ptr;
-   int i, r;
+   int r;
unsigned int fb_id;
struct amdgpu_bo_import_result output;
 
@@ -352,7 +351,7 @@ static void amdgpu_bo_ssg(void)
int i, j, fd;
uint64_t pattern = 0xdeadbeef12345678, out;
void *buf;
-   bool write_is_ok;
+   bool write_is_ok = false;
 
CU_ASSERT(!amdgpu_query_capability(device_handle, ));
if(!(cap.flag & AMDGPU_CAPABILITY_SSG_FLAG)) {
@@ -363,7 +362,7 @@ static void amdgpu_bo_ssg(void)
if (buf_size > cap.direct_gma_size << 20)
buf_size = cap.direct_gma_size << 20;
 
-   printf("SSG read/write block size 0x%x\n", buf_size);
+   printf("SSG read/write block size 0x%lx\n", buf_size);
 
CU_ASSERT((fd = open(in_file, O_WRONLY | O_CREAT, S_IRWXU)) >= 0);
for (i = 0; i < buf_size; i += sizeof(pattern)) {
@@ -413,7 +412,7 @@ static void amdgpu_bo_ssg(void)
for (i = 0; i < 3; i++) {
struct timespec ts1, ts2;
double a, b, c;
-   bool write_is_same;
+   bool write_is_same = false;
 
CU_ASSERT((fd = open(out_file, O_WRONLY | O_CREAT | O_DIRECT, 
S_IRWXU)) >= 0);
 
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index c0903a2a..10124c15 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -362,6 +362,7 @@ static void amdgpu_cs_uvd_decode(void)
bs_addr = fb_addr + 4*1024;
dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 
+   ctx_addr = 0;
if (family_id >= AMDGPU_FAMILY_VI) {
if ((family_id == AMDGPU_FAMILY_AI) ||
(chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
diff --git a/tests/amdgpu/ras_tests.c b/tests/amdgpu/ras_tests.c
index c1c543c1..d714be73 100644
--- a/tests/amdgpu/ras_tests.c
+++ b/tests/amdgpu/ras_tests.c
@@ -522,124 +522,6 @@ static int amdgpu_ras_lookup_id(drmDevicePtr device)
return -1;
 }
 
-CU_BOOL 

Re: [PATCH v8 04/17] drm/dp_mst: Fill branch->num_ports

[Harry Wentland]

On 2019-12-03 9:35 a.m., mikita.lip...@amd.com wrote:
> From: David Francis 
> 
> This field on drm_dp_mst_branch was never filled
> 
> It is initialized to zero when the port is kzallocced.
> When a port is added to the list, increment num_ports,
> and when a port is removed from the list, decrement num_ports.
> 
> v2: remember to decrement on port removal
> v3: don't explicitly init to 0
> 
> Reviewed-by: Lyude Paul 
> Reviewed-by: Harry Wentland 
> Signed-off-by: David Francis 
> Signed-off-by: Mikita Lipski 
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 06aae9b52e8a..d74b767d0fe1 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -2129,6 +2129,7 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch 
> *mstb,
>   build_mst_prop_path(mstb, port->port_num, proppath, sizeof(proppath));
>   port->connector = mgr->cbs->add_connector(mgr, port, proppath);
>   if (!port->connector) {
> + mstb->num_ports--;
>   ret = -ENOMEM;
>   goto error;
>   }
> @@ -2256,6 +2257,7 @@ drm_dp_mst_handle_link_address_port(struct 
> drm_dp_mst_branch *mstb,
>   mutex_lock(>lock);
>   drm_dp_mst_topology_get_port(port);
>   list_add(>next, >ports);
> + mstb->num_ports++;
>   mutex_unlock(>lock);
>   }
>  

Did you drop the num_ports-- when we do list_del() by accident?

See https://patchwork.freedesktop.org/patch/325600/

Harry

> 
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Re: [PATCH] drm/amd/powerplay: clear VBIOS scratchs on baco exit

[Yuan, Xiaojie]

Hi Evan,

Just out of curiosity, may I know what issue are you trying to fix?
I used to see vbios post failure (hangs in atombios init table) after baco exit 
occasionally on navi.

BR,
Xiaojie

> On Dec 6, 2019, at 11:37 AM, Evan Quan  wrote:
> 
> This is needed for coming asic init on performing gpu reset.
> 
> Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
> Signed-off-by: Evan Quan 
> ---
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
> 1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 39ec06aee809..ab809df7bc35 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1659,6 +1659,12 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
> enum smu_baco_state state)
>}
>} else {
>ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
> +if (ret)
> +goto out;
> +
> +WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_6, 0);
> +WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_7, 0);
> +
>bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
>BIF_DOORBELL_INT_CNTL,
>DOORBELL_INTERRUPT_DISABLE, 0);
> -- 
> 2.24.0
> 
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[PATCH] drm/amd/powerplay: clear VBIOS scratchs on baco exit

[Evan Quan]

This is needed for coming asic init on performing gpu reset.

Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 39ec06aee809..ab809df7bc35 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1659,6 +1659,12 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
enum smu_baco_state state)
}
} else {
ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
+   if (ret)
+   goto out;
+
+   WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_6, 0);
+   WREG32_SOC15(NBIO, 0, mmBIOS_SCRATCH_7, 0);
+
bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
BIF_DOORBELL_INT_CNTL,
DOORBELL_INTERRUPT_DISABLE, 0);
-- 
2.24.0

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RE: [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* Waiting for fences timed out or interrupted!

[Liu, Zhan]

I've seen a few people reported this issue on Freedesktop/Bugzilla. For example:
https://bugs.freedesktop.org/show_bug.cgi?id=24.

They all experienced this issue while playing games. The higher GPU clock is, 
the more frequent issue can be reproduced.

Also, some Reddit users pointed out all these games are Vulkan based. It could 
be a Vulkan specific issue.

Thanks,
Zhan

> -Original Message-
> From: amd-gfx  On Behalf Of
> Christian Pernegger
> Sent: 2019/December/05, Thursday 6:15 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
> Waiting for fences timed out or interrupted!
> 
> Hello,
> 
> one of my computers has been crashing while gaming rather a lot lately, with
> kernel messages pointing to amdgpu. First line see subject, rest in the
> attached log.
> SSH still works, attempts to shutdown/reboot don't quite finish.
> 
> Radeon VII in an Asus Pro WS X570-Ace. Ubuntu 18.04.3 HWE, mesa-aco.
> This one was with kernel 5.3.0-24-generic [hwe-edge], mesa
> 19.3.0+aco+git1575452833-3409c06e26d-1bionic1, vesa20_* from linux-
> firmware-20191022, running Ori and the Blind Forest: Definitive Edition via
> Proton/WINED3D11 under Steam Remote Play. I've had similar crashes
> sporadically even with 5.0 [plain hwe] and linux-firmware completely stock,
> and with native games (e.g. Crusader Kings II) running locally.
> It used to be maybe once every other week, though, that was tolerable, now
> Ori usually triggers it in under an hour. Turning off ACO via
> RADV_PERFTEST=llvm makes it worse (not bad enough to make it trigger
> quickly and reliably. though), going back to kernel 5.0 helps (as in an hour 
> or
> two might go by without a crash, but the performance impact is severe).
> 
> All very vague. Which is why this isn't pretending to be a bug report, just a
> "has anyone seen this?" kind of shout-out. If it's worthy of following up, I'd
> be happy to provide further info, just tell me what.
> 
> Cheers,
> C.
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RE: [PATCH] drm/amdgpu: Fix BACO entry failure in NAVI10.

[Quan, Evan]

Reviewed-by: Evan Quan 

> -Original Message-
> From: amd-gfx  On Behalf Of Andrey
> Grodzovsky
> Sent: Friday, December 6, 2019 3:30 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Grodzovsky, Andrey
> 
> Subject: [PATCH] drm/amdgpu: Fix BACO entry failure in NAVI10.
> 
> BACO feature must be kept enabled to allow entry into BACO state in SMU
> during runtime suspend.
> 
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c30f9a2..678 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1383,7 +1383,7 @@ static int smu_suspend(void *handle)
>   if (ret)
>   return ret;
> 
> - if (adev->in_gpu_reset && baco_feature_is_enabled) {
> + if (baco_feature_is_enabled) {
>   ret = smu_feature_set_enabled(smu,
> SMU_FEATURE_BACO_BIT, true);
>   if (ret) {
>   pr_warn("set BACO feature enabled failed,
> return %d\n", ret);
> --
> 2.7.4
> 
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Re: [PATCH v8 01/17] drm/dp_mst: Add PBN calculation for DSC modes

[kbuild test robot]

Hi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20191203]
[cannot apply to drm-intel/for-linux-next linus/master v5.4-rc8 
drm-exynos/exynos-drm-next v5.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:
https://github.com/0day-ci/linux/commits/mikita-lipski-amd-com/DSC-MST-support-for-DRM-and-AMDGPU/20191204-020604
base:1ab75b2e415a29dba9aec94f203c6f88dbfc0ba0
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-91-g817270f-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot 


sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c:28:43: sparse: sparse: 
>> not enough arguments for function drm_dp_calc_pbn_mode

vim +28 drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c

7cbce45d624322 Lyude Paul 2019-09-03  13  
7cbce45d624322 Lyude Paul 2019-09-03  14  int igt_dp_mst_calc_pbn_mode(void 
*ignored)
7cbce45d624322 Lyude Paul 2019-09-03  15  {
7cbce45d624322 Lyude Paul 2019-09-03  16int pbn, i;
7cbce45d624322 Lyude Paul 2019-09-03  17const struct {
7cbce45d624322 Lyude Paul 2019-09-03  18int rate;
7cbce45d624322 Lyude Paul 2019-09-03  19int bpp;
7cbce45d624322 Lyude Paul 2019-09-03  20int expected;
7cbce45d624322 Lyude Paul 2019-09-03  21} test_params[] = {
7cbce45d624322 Lyude Paul 2019-09-03  22{ 154000, 30, 689 },
7cbce45d624322 Lyude Paul 2019-09-03  23{ 234000, 30, 1047 },
7cbce45d624322 Lyude Paul 2019-09-03  24{ 297000, 24, 1063 },
7cbce45d624322 Lyude Paul 2019-09-03  25};
7cbce45d624322 Lyude Paul 2019-09-03  26  
7cbce45d624322 Lyude Paul 2019-09-03  27for (i = 0; i < 
ARRAY_SIZE(test_params); i++) {
7cbce45d624322 Lyude Paul 2019-09-03 @28pbn = 
drm_dp_calc_pbn_mode(test_params[i].rate,
7cbce45d624322 Lyude Paul 2019-09-03  29
   test_params[i].bpp);
7cbce45d624322 Lyude Paul 2019-09-03  30FAIL(pbn != 
test_params[i].expected,
7cbce45d624322 Lyude Paul 2019-09-03  31 "Expected PBN %d 
for clock %d bpp %d, got %d\n",
7cbce45d624322 Lyude Paul 2019-09-03  32 
test_params[i].expected, test_params[i].rate,
7cbce45d624322 Lyude Paul 2019-09-03  33 
test_params[i].bpp, pbn);
7cbce45d624322 Lyude Paul 2019-09-03  34}
7cbce45d624322 Lyude Paul 2019-09-03  35  
7cbce45d624322 Lyude Paul 2019-09-03  36return 0;
7cbce45d624322 Lyude Paul 2019-09-03  37  }
2f015ec6eab693 Lyude Paul 2019-09-03  38  

:: The code at line 28 was first introduced by commit
:: 7cbce45d6243225914b5c967b4ee927a2327842a drm/dp_mst: Move 
test_calc_pbn_mode() into an actual selftest

:: TO: Lyude Paul 
:: CC: Lyude Paul 

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org Intel Corporation
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Re: [PATCH] drm/amdgpu/display: add fallthrough comment

[Harry Wentland]

On 2019-12-05 5:16 p.m., Liu, Zhan wrote:
> 
> 
>> -Original Message-
>> From: Alex Deucher 
>> Sent: 2019/December/05, Thursday 5:13 PM
>> To: Liu, Zhan 
>> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
>> 
>> Subject: Re: [PATCH] drm/amdgpu/display: add fallthrough comment
>>
>> On Thu, Dec 5, 2019 at 5:10 PM Liu, Zhan  wrote:
>>>
>>>
>>>
 -Original Message-
 From: amd-gfx  On Behalf Of
 Alex Deucher
 Sent: 2019/December/05, Thursday 4:39 PM
 To: amd-gfx@lists.freedesktop.org
 Cc: Deucher, Alexander 
 Subject: [PATCH] drm/amdgpu/display: add fallthrough comment

 To avoid a compiler warning.

 Signed-off-by: Alex Deucher 
 ---
  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
  1 file changed, 1 insertion(+)

 diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
 b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
 index 191b68b8163a..f1a5d2c6aa37 100644
 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
 +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
 @@ -645,6 +645,7 @@ bool dce_aux_transfer_with_retries(struct
 ddc_service *ddc,
   case AUX_TRANSACTION_REPLY_AUX_DEFER:
   case
 AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
   retry_on_defer = true;
 + /* fall through */
>>>
>>> I am a bit confusing here. Why a comment can avoid a compiler warning?
>>
>> The kernel enables fall through warnings, so unless there is a comment
>> mentioning that are are expecting to fall through here, we get a warning.
>> The idea is to find missing breaks in switch code.
>>
>> Alex
> 
> Got you. Thank you for your explanation.
> 
> Reviewed-by: Zhan Liu 
> 

Interesting. It's described at [1] (search for
-Wimplicit-fallthrough=3). Never knew that.

This is also
Reviewed-by: Harry Wentland 

[1]
https://developers.redhat.com/blog/2017/03/10/wimplicit-fallthrough-in-gcc-7/

Harry

>>
>>>
   case
 AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
   if (++aux_defer_retries >=
 AUX_MAX_DEFER_RETRIES) {
   goto fail;
 --
 2.23.0

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Re: amdgpu: Enable full DCN support on POWER

[Timothy Pearson]

- Original Message -
> From: "Harry Wentland" 
> To: "Liu, Zhan" , "Timothy Pearson" 
> , "amd-gfx"
> 
> Sent: Thursday, December 5, 2019 5:19:22 PM
> Subject: Re: amdgpu: Enable full DCN support on POWER

> On 2019-12-05 6:02 p.m., Liu, Zhan wrote:
>> 
>> 
>>> -Original Message-
>>> From: amd-gfx  On Behalf Of
>>> Timothy Pearson
>>> Sent: 2019/December/05, Thursday 4:58 PM
>>> To: amd-gfx 
>>> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
>>>
>>> DCN requires floating point support to operate.  Add the appropriate
>>> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
>>>
>>> Signed-off-by: Timothy Pearson 
>>> ---
>>>  drivers/gpu/drm/amd/display/Kconfig   |   8 +-
>>>  drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
>>>  drivers/gpu/drm/amd/display/dc/calcs/Makefile |   8 +
>>>  .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
>>>  drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   8 +
>>>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
>>>  drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   8 +
>>>  .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
>>>  drivers/gpu/drm/amd/display/dc/dml/Makefile   |   9 +
>>>  drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   8 +
>>>  drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
>>>  11 files changed, 263 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
>>> b/drivers/gpu/drm/amd/display/Kconfig
>>> index 313183b80032..c73a63f3e245 100644
>>> --- a/drivers/gpu/drm/amd/display/Kconfig
>>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>>> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>>> bool "AMD DC - Enable new display engine"
>>> default y
>>> select SND_HDA_COMPONENT if SND_HDA_CORE
>>> -   select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
>>> && KCOV_ENABLE_COMPARISONS)
>>> +   select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
>>> && !(KCOV_INSTRUMENT_ALL &&
>>> +KCOV_ENABLE_COMPARISONS)
>>> help
>>>   Choose this option if you want to use the new display engine
>>>   support for AMDGPU. This adds required support for Vega and @@
>>> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0  config
>>> DRM_AMD_DC_DCN2_0
>>> bool "DCN 2.0 family"
>>> default y
>>> -   depends on DRM_AMD_DC && X86
>>> +   depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN1_0
>>> help
>>>   Choose this option if you want to have @@ -28,7 +28,7 @@ config
>>> DRM_AMD_DC_DCN2_0
>>>
>>>  config DRM_AMD_DC_DCN2_1
>>> bool "DCN 2.1 family"
>>> -   depends on DRM_AMD_DC && X86
>>> +   depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN2_0
>>> help
>>>   Choose this option if you want to have @@ -37,7 +37,7 @@ config
>>> DRM_AMD_DC_DCN2_1  config DRM_AMD_DC_DSC_SUPPORT
>>> bool "DSC support"
>>> default y
>>> -   depends on DRM_AMD_DC && X86
>>> +   depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN1_0
>>> depends on DRM_AMD_DC_DCN2_0
>>> help
>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/Makefile
>>> index a160512a2f04..3e026a969386 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>>> @@ -1,5 +1,6 @@
>>>  #
>>>  # Copyright 2017 Advanced Micro Devices, Inc.
>>> +# Copyright 2019 Raptor Engineering, LLC
>> 
>> NAK.
>> 
>> IANAL, but I don't think you can add your company's name by modifying part of
>> the code. The copyright notice shows the authors of the original work.
>> 
>> When modifying the code, you are required to agree with that copyright 
>> notice.
>> That's the purpose of that copyright notice piece.
>> 
> 
> I always thought these copyright notices are nearly meaningless.
> 
> That said, this patch doesn't have any change in this file. I don't
> think it warrants an additional copyright notice.
> 
> Harry

Agreed -- looks like that snuck in with the other changes.  I can back this one 
out, however in general regardless of the notice having any actual legal 
meaning (the GIT commit history has the actual legal teeth from what I 
understand as it establishes shared ownership), our general policy per 
recommendations is to add the copyright line.  It helps anyone looking at the 
file know at a glance that there is more than one corporate author, and 
therefore e.g. the only terms it can be used on without a complex multi-party 
license renegotiation is (in this case) the GPL v2.

I'll wait for comments on the actual technical parts of the patch, and will 
make sure to remove this one spurious line in the final patch series.

Thanks!

> 
>>>  #
>>>  # Permission is hereby granted, free of charge, to any person obtaining a  
>>> #
>>> copy of this software and associated documentation files (the "Software"),
>>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> index 

Re: [GIT PULL] Please pull hmm changes

[John Hubbard]

On 12/2/19 6:42 PM, Jason Gunthorpe wrote:
...
> Regarding the ugly names.. Naming has been really hard here because
> currently everything is a 'mmu notifier' and the natural abberviations
> from there are crummy. Here is the basic summary:
> 
> struct mmu_notifier_mm (ie the mm->mmu_notifier_mm)
>-> mmn_mm
> struct mm_struct 
>-> mm
> struct mmu_notifier (ie the user subscription to the mm_struct)
>-> mn
> struct mmu_interval_notifier (the other kind of user subscription)
>-> mni
> struct mmu_notifier_range (ie the args to invalidate_range)
>-> range
> 
> I can send a patch to switch mmn_mm to mmu_notifier_mm, which is the
> only pre-existing name for this value. But IIRC, it is a somewhat ugly
> with long line wrapping. 'mni' is a pain, I have to reflect on that.
> (honesly, I dislike mmu_notififer_mm quite a lot too)
> 
> I think it would be overall nicer with better names for the original
> structs. Perhaps:
> 
>  mmn_* - MMU notifier prefix
>  mmn_state <- struct mmu_notifier_mm
>  mmn_subscription (mmn_sub) <- struct mmu_notifier
>  mmn_range_subscription (mmn_range_sub) <- struct mmu_interval_notifier
>  mmn_invalidate_desc <- struct mmu_notifier_range
> 
> At least this is how I describe them in my mind..  This is a lot of
> churn, and spreads through many drivers. This is why I kept the names
> as-is and we ended up with the also quite bad 'mmu_interval_notifier'
> 
> Maybe just switch mmu_notifier_mm for mmn_state and leave the drivers
> alone?
> 
> Anyone on the CC list have advice?
> 
> Jason

No advice, just a naming idea similar in spirit to Jerome's suggestion
(use a longer descriptive word, and don't try to capture the entire phrase):
use "notif" in place of the unloved "mmn". So partially, approximately like 
this:

notif_*<- MMU notifier prefix
notif_state<- struct mmu_notifier_mm
notif_subscription (notif_sub) <- struct mmu_notifier
notif_invalidate_desc  <- struct mmu_notifier_range*
notif_range_subscription (notif_range_sub) <- struct mmu_interval_notifier



thanks,
-- 
John Hubbard
NVIDIA
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Re: amdgpu: Enable full DCN support on POWER

[Harry Wentland]

On 2019-12-05 6:02 p.m., Liu, Zhan wrote:
> 
> 
>> -Original Message-
>> From: amd-gfx  On Behalf Of
>> Timothy Pearson
>> Sent: 2019/December/05, Thursday 4:58 PM
>> To: amd-gfx 
>> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
>>
>> DCN requires floating point support to operate.  Add the appropriate
>> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
>>
>> Signed-off-by: Timothy Pearson 
>> ---
>>  drivers/gpu/drm/amd/display/Kconfig   |   8 +-
>>  drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
>>  drivers/gpu/drm/amd/display/dc/calcs/Makefile |   8 +
>>  .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
>>  drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   8 +
>>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
>>  drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   8 +
>>  .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
>>  drivers/gpu/drm/amd/display/dc/dml/Makefile   |   9 +
>>  drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   8 +
>>  drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
>>  11 files changed, 263 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
>> b/drivers/gpu/drm/amd/display/Kconfig
>> index 313183b80032..c73a63f3e245 100644
>> --- a/drivers/gpu/drm/amd/display/Kconfig
>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>>  bool "AMD DC - Enable new display engine"
>>  default y
>>  select SND_HDA_COMPONENT if SND_HDA_CORE
>> -select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
>> && KCOV_ENABLE_COMPARISONS)
>> +select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
>> && !(KCOV_INSTRUMENT_ALL &&
>> +KCOV_ENABLE_COMPARISONS)
>>  help
>>Choose this option if you want to use the new display engine
>>support for AMDGPU. This adds required support for Vega and @@
>> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0  config
>> DRM_AMD_DC_DCN2_0
>>  bool "DCN 2.0 family"
>>  default y
>> -depends on DRM_AMD_DC && X86
>> +depends on DRM_AMD_DC && (X86 || PPC64)
>>  depends on DRM_AMD_DC_DCN1_0
>>  help
>>Choose this option if you want to have @@ -28,7 +28,7 @@ config
>> DRM_AMD_DC_DCN2_0
>>
>>  config DRM_AMD_DC_DCN2_1
>>  bool "DCN 2.1 family"
>> -depends on DRM_AMD_DC && X86
>> +depends on DRM_AMD_DC && (X86 || PPC64)
>>  depends on DRM_AMD_DC_DCN2_0
>>  help
>>Choose this option if you want to have @@ -37,7 +37,7 @@ config
>> DRM_AMD_DC_DCN2_1  config DRM_AMD_DC_DSC_SUPPORT
>>  bool "DSC support"
>>  default y
>> -depends on DRM_AMD_DC && X86
>> +depends on DRM_AMD_DC && (X86 || PPC64)
>>  depends on DRM_AMD_DC_DCN1_0
>>  depends on DRM_AMD_DC_DCN2_0
>>  help
>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>> b/drivers/gpu/drm/amd/display/dc/Makefile
>> index a160512a2f04..3e026a969386 100644
>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>> @@ -1,5 +1,6 @@
>>  #
>>  # Copyright 2017 Advanced Micro Devices, Inc.
>> +# Copyright 2019 Raptor Engineering, LLC
> 
> NAK.
> 
> IANAL, but I don't think you can add your company's name by modifying part of 
> the code. The copyright notice shows the authors of the original work.
> 
> When modifying the code, you are required to agree with that copyright 
> notice. That's the purpose of that copyright notice piece.
> 

I always thought these copyright notices are nearly meaningless.

That said, this patch doesn't have any change in this file. I don't
think it warrants an additional copyright notice.

Harry

>>  #
>>  # Permission is hereby granted, free of charge, to any person obtaining a  #
>> copy of this software and associated documentation files (the "Software"),
>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> index 26c6d735cdc7..20c88aff930a 100644
>> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> @@ -24,7 +24,13 @@
>>  # It calculates Bandwidth and Watermarks values for HW programming  #
>>
>> +ifdef CONFIG_X86_64
>>  calcs_ccflags := -mhard-float -msse
>> +endif
>> +
>> +ifdef CONFIG_PPC64
>> +calcs_ccflags := -mhard-float -maltivec endif
>>
>>  ifdef CONFIG_CC_IS_GCC
>>  ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +38,7 @@ IS_OLD_GCC =
>> 1  endif  endif
>>
>> +ifdef CONFIG_X86_64
>>  ifdef IS_OLD_GCC
>>  # Stack alignment mismatch, proceed with caution.
>>  # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>> boundary=3 @@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-
>> boundary=4  else  calcs_ccflags += -msse2  endif
>> +endif
>>
>>  CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
>> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags) diff -
>> -git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>> 

[drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* Waiting for fences timed out or interrupted!

[Christian Pernegger]

Hello,

one of my computers has been crashing while gaming rather a lot
lately, with kernel messages pointing to amdgpu. First line see
subject, rest in the attached log.
SSH still works, attempts to shutdown/reboot don't quite finish.

Radeon VII in an Asus Pro WS X570-Ace. Ubuntu 18.04.3 HWE, mesa-aco.
This one was with kernel 5.3.0-24-generic [hwe-edge], mesa
19.3.0+aco+git1575452833-3409c06e26d-1bionic1, vesa20_* from
linux-firmware-20191022, running Ori and the Blind Forest: Definitive
Edition via Proton/WINED3D11 under Steam Remote Play. I've had similar
crashes sporadically even with 5.0 [plain hwe] and linux-firmware
completely stock, and with native games (e.g. Crusader Kings II)
running locally.
It used to be maybe once every other week, though, that was tolerable,
now Ori usually triggers it in under an hour. Turning off ACO via
RADV_PERFTEST=llvm makes it worse (not bad enough to make it trigger
quickly and reliably. though), going back to kernel 5.0 helps (as in
an hour or two might go by without a crash, but the performance impact
is severe).

All very vague. Which is why this isn't pretending to be a bug report,
just a "has anyone seen this?" kind of shout-out. If it's worthy of
following up, I'd be happy to provide further info, just tell me what.

Cheers,
C.


amdgpu.journal
Description: Binary data
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RE: amdgpu: Enable full DCN support on POWER

[Liu, Zhan]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Timothy Pearson
> Sent: 2019/December/05, Thursday 4:58 PM
> To: amd-gfx 
> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
> 
> DCN requires floating point support to operate.  Add the appropriate
> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
> 
> Signed-off-by: Timothy Pearson 
> ---
>  drivers/gpu/drm/amd/display/Kconfig   |   8 +-
>  drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
>  drivers/gpu/drm/amd/display/dc/calcs/Makefile |   8 +
>  .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
>  drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   8 +
>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
>  drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   8 +
>  .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
>  drivers/gpu/drm/amd/display/dc/dml/Makefile   |   9 +
>  drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   8 +
>  drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
>  11 files changed, 263 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index 313183b80032..c73a63f3e245 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>   bool "AMD DC - Enable new display engine"
>   default y
>   select SND_HDA_COMPONENT if SND_HDA_CORE
> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
> && KCOV_ENABLE_COMPARISONS)
> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
> && !(KCOV_INSTRUMENT_ALL &&
> +KCOV_ENABLE_COMPARISONS)
>   help
> Choose this option if you want to use the new display engine
> support for AMDGPU. This adds required support for Vega and @@
> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0  config
> DRM_AMD_DC_DCN2_0
>   bool "DCN 2.0 family"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   help
> Choose this option if you want to have @@ -28,7 +28,7 @@ config
> DRM_AMD_DC_DCN2_0
> 
>  config DRM_AMD_DC_DCN2_1
>   bool "DCN 2.1 family"
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN2_0
>   help
> Choose this option if you want to have @@ -37,7 +37,7 @@ config
> DRM_AMD_DC_DCN2_1  config DRM_AMD_DC_DSC_SUPPORT
>   bool "DSC support"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   depends on DRM_AMD_DC_DCN2_0
>   help
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index a160512a2f04..3e026a969386 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -1,5 +1,6 @@
>  #
>  # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC

NAK.

IANAL, but I don't think you can add your company's name by modifying part of 
the code. The copyright notice shows the authors of the original work.

When modifying the code, you are required to agree with that copyright notice. 
That's the purpose of that copyright notice piece.

>  #
>  # Permission is hereby granted, free of charge, to any person obtaining a  #
> copy of this software and associated documentation files (the "Software"),
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 26c6d735cdc7..20c88aff930a 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -24,7 +24,13 @@
>  # It calculates Bandwidth and Watermarks values for HW programming  #
> 
> +ifdef CONFIG_X86_64
>  calcs_ccflags := -mhard-float -msse
> +endif
> +
> +ifdef CONFIG_PPC64
> +calcs_ccflags := -mhard-float -maltivec endif
> 
>  ifdef CONFIG_CC_IS_GCC
>  ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +38,7 @@ IS_OLD_GCC =
> 1  endif  endif
> 
> +ifdef CONFIG_X86_64
>  ifdef IS_OLD_GCC
>  # Stack alignment mismatch, proceed with caution.
>  # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
> boundary=3 @@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-
> boundary=4  else  calcs_ccflags += -msse2  endif
> +endif
> 
>  CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags) diff -
> -git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 9b2cb57bf2ba..236e852ea60b 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -1,5 +1,6 @@
>  /*
>   * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
>   *
>   * 

RE: [PATCH] drm/amdgpu/display: add fallthrough comment

[Liu, Zhan]

> -Original Message-
> From: Alex Deucher 
> Sent: 2019/December/05, Thursday 5:13 PM
> To: Liu, Zhan 
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> 
> Subject: Re: [PATCH] drm/amdgpu/display: add fallthrough comment
> 
> On Thu, Dec 5, 2019 at 5:10 PM Liu, Zhan  wrote:
> >
> >
> >
> > > -Original Message-
> > > From: amd-gfx  On Behalf Of
> > > Alex Deucher
> > > Sent: 2019/December/05, Thursday 4:39 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander 
> > > Subject: [PATCH] drm/amdgpu/display: add fallthrough comment
> > >
> > > To avoid a compiler warning.
> > >
> > > Signed-off-by: Alex Deucher 
> > > ---
> > >  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > index 191b68b8163a..f1a5d2c6aa37 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > @@ -645,6 +645,7 @@ bool dce_aux_transfer_with_retries(struct
> > > ddc_service *ddc,
> > >   case AUX_TRANSACTION_REPLY_AUX_DEFER:
> > >   case
> > > AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
> > >   retry_on_defer = true;
> > > + /* fall through */
> >
> > I am a bit confusing here. Why a comment can avoid a compiler warning?
> 
> The kernel enables fall through warnings, so unless there is a comment
> mentioning that are are expecting to fall through here, we get a warning.
> The idea is to find missing breaks in switch code.
> 
> Alex

Got you. Thank you for your explanation.

Reviewed-by: Zhan Liu 

> 
> >
> > >   case
> > > AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
> > >   if (++aux_defer_retries >=
> > > AUX_MAX_DEFER_RETRIES) {
> > >   goto fail;
> > > --
> > > 2.23.0
> > >
> > > ___
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> > > freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> > >
> gfxdata=02%7C01%7Czhan.liu%40amd.com%7C77d85a0275aa4c0a78
> > >
> 2f08d779cb9716%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> > >
> 37111788208702340sdata=3m%2FuNuNIgq82z%2BAeXJ9y7wn81kV%
> > > 2FiDt3AyC3CDiTRrc%3Dreserved=0
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Re: [PATCH] drm/amdgpu/display: add fallthrough comment

[Alex Deucher]

On Thu, Dec 5, 2019 at 5:10 PM Liu, Zhan  wrote:
>
>
>
> > -Original Message-
> > From: amd-gfx  On Behalf Of Alex
> > Deucher
> > Sent: 2019/December/05, Thursday 4:39 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander 
> > Subject: [PATCH] drm/amdgpu/display: add fallthrough comment
> >
> > To avoid a compiler warning.
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > index 191b68b8163a..f1a5d2c6aa37 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > @@ -645,6 +645,7 @@ bool dce_aux_transfer_with_retries(struct
> > ddc_service *ddc,
> >   case AUX_TRANSACTION_REPLY_AUX_DEFER:
> >   case
> > AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
> >   retry_on_defer = true;
> > + /* fall through */
>
> I am a bit confusing here. Why a comment can avoid a compiler warning?

The kernel enables fall through warnings, so unless there is a comment
mentioning that are are expecting to fall through here, we get a
warning.  The idea is to find missing breaks in switch code.

Alex

>
> >   case
> > AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
> >   if (++aux_defer_retries >=
> > AUX_MAX_DEFER_RETRIES) {
> >   goto fail;
> > --
> > 2.23.0
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> > freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> > gfxdata=02%7C01%7Czhan.liu%40amd.com%7C77d85a0275aa4c0a78
> > 2f08d779cb9716%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> > 37111788208702340sdata=3m%2FuNuNIgq82z%2BAeXJ9y7wn81kV%
> > 2FiDt3AyC3CDiTRrc%3Dreserved=0
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RE: [PATCH] drm/amdgpu/display: add fallthrough comment

[Liu, Zhan]

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2019/December/05, Thursday 4:39 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/display: add fallthrough comment
> 
> To avoid a compiler warning.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> index 191b68b8163a..f1a5d2c6aa37 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> @@ -645,6 +645,7 @@ bool dce_aux_transfer_with_retries(struct
> ddc_service *ddc,
>   case AUX_TRANSACTION_REPLY_AUX_DEFER:
>   case
> AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
>   retry_on_defer = true;
> + /* fall through */

I am a bit confusing here. Why a comment can avoid a compiler warning?

>   case
> AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
>   if (++aux_defer_retries >=
> AUX_MAX_DEFER_RETRIES) {
>   goto fail;
> --
> 2.23.0
> 
> ___
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> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfxdata=02%7C01%7Czhan.liu%40amd.com%7C77d85a0275aa4c0a78
> 2f08d779cb9716%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> 37111788208702340sdata=3m%2FuNuNIgq82z%2BAeXJ9y7wn81kV%
> 2FiDt3AyC3CDiTRrc%3Dreserved=0
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[PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER

[Timothy Pearson]

DCN requires floating point support to operate.  Add the appropriate
x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/display/Kconfig   |   8 +-
 drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
 drivers/gpu/drm/amd/display/dc/calcs/Makefile |   8 +
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   8 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   8 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |   9 +
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   8 +
 drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
 11 files changed, 263 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 313183b80032..c73a63f3e245 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
-   select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
+   select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
help
  Choose this option if you want to use the new display engine
  support for AMDGPU. This adds required support for Vega and
@@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
 config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
help
  Choose this option if you want to have
@@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
 
 config DRM_AMD_DC_DCN2_1
bool "DCN 2.1 family"
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN2_0
help
  Choose this option if you want to have
@@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
 config DRM_AMD_DC_DSC_SUPPORT
bool "DSC support"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
depends on DRM_AMD_DC_DCN2_0
help
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index a160512a2f04..3e026a969386 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -1,5 +1,6 @@
 #
 # Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 26c6d735cdc7..20c88aff930a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,7 +24,13 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
+ifdef CONFIG_X86_64
 calcs_ccflags := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+calcs_ccflags := -mhard-float -maltivec
+endif
 
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +38,7 @@ IS_OLD_GCC = 1
 endif
 endif
 
+ifdef CONFIG_X86_64
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
 else
 calcs_ccflags += -msse2
 endif
+endif
 
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57bf2ba..236e852ea60b 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
 {
bool updated = false;
 
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+   if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+   preempt_disable();
+   enable_kernel_vsx();
+   } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+   preempt_disable();
+   enable_kernel_altivec();
+   } else if 

Re: [PATCH] [RFC] amdgpu: Enable full DCN support on POWER

[Timothy Pearson]

Sent this a bit too early, still running through checks.  Watch for a V2 
shortly.

- Original Message -
> From: "Timothy Pearson" 
> To: "amd-gfx" 
> Sent: Thursday, December 5, 2019 3:39:24 PM
> Subject: [PATCH] [RFC] amdgpu: Enable full DCN support on POWER

> DCN requires floating point support to operate.  Add the appropriate
> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
> 
> Signed-off-by: Timothy Pearson 
> ---
> drivers/gpu/drm/amd/display/Kconfig   |   8 +-
> drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
> drivers/gpu/drm/amd/display/dc/calcs/Makefile |   4 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
> drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   4 +
> .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
> drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   4 +
> .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
> drivers/gpu/drm/amd/display/dc/dml/Makefile   |   5 +
> drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   4 +
> drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
> 11 files changed, 243 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index 313183b80032..c73a63f3e245 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>   bool "AMD DC - Enable new display engine"
>   default y
>   select SND_HDA_COMPONENT if SND_HDA_CORE
> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL &&
> KCOV_ENABLE_COMPARISONS)
> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL &&
> KCOV_ENABLE_COMPARISONS)
>   help
> Choose this option if you want to use the new display engine
> support for AMDGPU. This adds required support for Vega and
> @@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
> config DRM_AMD_DC_DCN2_0
>   bool "DCN 2.0 family"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   help
> Choose this option if you want to have
> @@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
> 
> config DRM_AMD_DC_DCN2_1
>   bool "DCN 2.1 family"
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN2_0
>   help
> Choose this option if you want to have
> @@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
> config DRM_AMD_DC_DSC_SUPPORT
>   bool "DSC support"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   depends on DRM_AMD_DC_DCN2_0
>   help
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index a160512a2f04..3e026a969386 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -1,5 +1,6 @@
> #
> # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC
> #
> # Permission is hereby granted, free of charge, to any person obtaining a
> # copy of this software and associated documentation files (the "Software"),
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 26c6d735cdc7..0d46c37d6c95 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -24,7 +24,9 @@
> # It calculates Bandwidth and Watermarks values for HW programming
> #
> 
> +ifdef CONFIG_X86_64
> calcs_ccflags := -mhard-float -msse
> +endif
> 
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> @@ -32,6 +34,7 @@ IS_OLD_GCC = 1
> endif
> endif
> 
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and 
> -mpreferred-stack-boundary=3
> @@ -40,6 +43,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
> else
> calcs_ccflags += -msse2
> endif
> +endif
> 
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 9b2cb57bf2ba..5c913b585ac4 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -1,5 +1,6 @@
> /*
>  * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
>  *
>  * Permission is hereby granted, free of charge, to any person obtaining a
>  * copy of this software and associated documentation files (the "Software"),
> @@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
> {
>   bool updated = false;
> 
> +#if defined(CONFIG_X86_64)
>   kernel_fpu_begin();
> +#elif 

[PATCH] drm/amdgpu/display: add fallthrough comment

[Alex Deucher]

To avoid a compiler warning.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 191b68b8163a..f1a5d2c6aa37 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -645,6 +645,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
case AUX_TRANSACTION_REPLY_AUX_DEFER:
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
retry_on_defer = true;
+   /* fall through */
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
if (++aux_defer_retries >= 
AUX_MAX_DEFER_RETRIES) {
goto fail;
-- 
2.23.0

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[PATCH] [RFC] amdgpu: Enable full DCN support on POWER

[Timothy Pearson]

DCN requires floating point support to operate.  Add the appropriate
x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.

Signed-off-by: Timothy Pearson 
---
 drivers/gpu/drm/amd/display/Kconfig   |   8 +-
 drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
 drivers/gpu/drm/amd/display/dc/calcs/Makefile |   4 +
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   4 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   4 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |   5 +
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   4 +
 drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
 11 files changed, 243 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 313183b80032..c73a63f3e245 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
-   select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
+   select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
help
  Choose this option if you want to use the new display engine
  support for AMDGPU. This adds required support for Vega and
@@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
 config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
help
  Choose this option if you want to have
@@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
 
 config DRM_AMD_DC_DCN2_1
bool "DCN 2.1 family"
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN2_0
help
  Choose this option if you want to have
@@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
 config DRM_AMD_DC_DSC_SUPPORT
bool "DSC support"
default y
-   depends on DRM_AMD_DC && X86
+   depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
depends on DRM_AMD_DC_DCN2_0
help
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index a160512a2f04..3e026a969386 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -1,5 +1,6 @@
 #
 # Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 26c6d735cdc7..0d46c37d6c95 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,7 +24,9 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
+ifdef CONFIG_X86_64
 calcs_ccflags := -mhard-float -msse
+endif
 
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +34,7 @@ IS_OLD_GCC = 1
 endif
 endif
 
+ifdef CONFIG_X86_64
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +43,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
 else
 calcs_ccflags += -msse2
 endif
+endif
 
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57bf2ba..5c913b585ac4 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
 {
bool updated = false;
 
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+   if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+   preempt_disable();
+   enable_kernel_vsx();
+   } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+   preempt_disable();
+   enable_kernel_altivec();
+   } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+   preempt_disable();
+ 

RE: [PATCH] drm/amdgpu: Fix BACO entry failure in NAVI10.

[Deucher, Alexander]

> -Original Message-
> From: Andrey Grodzovsky 
> Sent: Thursday, December 5, 2019 2:30 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Grodzovsky,
> Andrey 
> Subject: [PATCH] drm/amdgpu: Fix BACO entry failure in NAVI10.
> 
> BACO feature must be kept enabled to allow entry into BACO state in SMU
> during runtime suspend.
> 
> Signed-off-by: Andrey Grodzovsky 

Reviewed-by: Alex Deucher 
Tested-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c30f9a2..678 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1383,7 +1383,7 @@ static int smu_suspend(void *handle)
>   if (ret)
>   return ret;
> 
> - if (adev->in_gpu_reset && baco_feature_is_enabled) {
> + if (baco_feature_is_enabled) {
>   ret = smu_feature_set_enabled(smu,
> SMU_FEATURE_BACO_BIT, true);
>   if (ret) {
>   pr_warn("set BACO feature enabled failed, return
> %d\n", ret);
> --
> 2.7.4

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[PATCH] drm/amdgpu: Fix BACO entry failure in NAVI10.

[Andrey Grodzovsky]

BACO feature must be kept enabled to allow entry into
BACO state in SMU during runtime suspend.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c30f9a2..678 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1383,7 +1383,7 @@ static int smu_suspend(void *handle)
if (ret)
return ret;
 
-   if (adev->in_gpu_reset && baco_feature_is_enabled) {
+   if (baco_feature_is_enabled) {
ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
if (ret) {
pr_warn("set BACO feature enabled failed, return %d\n", 
ret);
-- 
2.7.4

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Re: [PATCH v8 12/17] drm/dp_mst: Add branch bandwidth validation to MST atomic check

[Harry Wentland]

On 2019-12-03 9:35 a.m., mikita.lip...@amd.com wrote:
> From: Mikita Lipski 
> 
> Adding PBN attribute to drm_dp_vcpi_allocation structure to
> keep track of how much bandwidth each Port requires.
> Adding drm_dp_mst_atomic_check_bw_limit to verify that
> state's bandwidth needs doesn't exceed available bandwidth.
> The funtion is called in drm_dp_mst_atomic_check after
> drm_dp_mst_atomic_check_topology_state to fully verify that
> the proposed topology is supported.
> 
> Cc: Jerry Zuo 
> Cc: Harry Wentland 
> Cc: Lyude Paul 
> Signed-off-by: Mikita Lipski 
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 67 ++-
>  include/drm/drm_dp_mst_helper.h   |  1 +
>  2 files changed, 66 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 5e549f48ffb8..76bcbb4cd8b4 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -4052,7 +4052,7 @@ int drm_dp_atomic_find_vcpi_slots(struct 
> drm_atomic_state *state,
>  {
>   struct drm_dp_mst_topology_state *topology_state;
>   struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> - int prev_slots, req_slots;
> + int prev_slots, prev_bw, req_slots, ret;
>  

'ret' is unused here.

Harry

>   topology_state = drm_atomic_get_mst_topology_state(state, mgr);
>   if (IS_ERR(topology_state))
> @@ -4063,6 +4063,7 @@ int drm_dp_atomic_find_vcpi_slots(struct 
> drm_atomic_state *state,
>   if (pos->port == port) {
>   vcpi = pos;
>   prev_slots = vcpi->vcpi;
> + prev_bw = vcpi->pbn;
>  
>   /*
>* This should never happen, unless the driver tries
> @@ -4078,8 +4079,10 @@ int drm_dp_atomic_find_vcpi_slots(struct 
> drm_atomic_state *state,
>   break;
>   }
>   }
> - if (!vcpi)
> + if (!vcpi) {
>   prev_slots = 0;
> + prev_bw = 0;
> + }
>  
>   if (pbn_div <= 0)
>   pbn_div = mgr->pbn_div;
> @@ -4089,6 +4092,9 @@ int drm_dp_atomic_find_vcpi_slots(struct 
> drm_atomic_state *state,
>   DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
>port->connector->base.id, port->connector->name,
>port, prev_slots, req_slots);
> + DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] PBN %d -> %d\n",
> +  port->connector->base.id, port->connector->name,
> +  port, prev_bw, pbn);
>  
>   /* Add the new allocation to the state */
>   if (!vcpi) {
> @@ -4101,6 +4107,7 @@ int drm_dp_atomic_find_vcpi_slots(struct 
> drm_atomic_state *state,
>   list_add(>next, _state->vcpis);
>   }
>   vcpi->vcpi = req_slots;
> + vcpi->pbn = pbn;
>  
>   return req_slots;
>  }
> @@ -4703,6 +4710,59 @@ static void drm_dp_mst_destroy_state(struct 
> drm_private_obj *obj,
>   kfree(mst_state);
>  }
>  
> +static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port 
> *port,
> +  struct drm_dp_mst_branch 
> *branch)
> +{
> + while (port->parent) {
> + if (port->parent == branch)
> + return true;
> +
> + if (port->parent->port_parent)
> + port = port->parent->port_parent;
> + else
> + break;
> + }
> + return false;
> +}
> +
> +static inline
> +int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,
> +  struct drm_dp_mst_topology_state 
> *mst_state)
> +{
> + struct drm_dp_mst_port *port;
> + struct drm_dp_vcpi_allocation *vcpi;
> + int pbn_limit = 0, pbn_used = 0;
> +
> + list_for_each_entry(port, >ports, next) {
> + if (port->mstb) {
> + if (drm_dp_mst_atomic_check_bw_limit(port->mstb, 
> mst_state))
> + return -EINVAL;
> + }
> + if (port->available_pbn > 0)
> + pbn_limit = port->available_pbn;
> + }
> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN available\n",
> +  branch,
> +  pbn_limit);
> +
> + list_for_each_entry(vcpi, _state->vcpis, next) {
> + if (!vcpi->pbn)
> + continue;
> +
> + if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))
> + pbn_used += vcpi->pbn;
> + }
> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
> +  branch,
> +  pbn_used);
> + if (pbn_used > pbn_limit) {
> + DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available bandwidth\n",
> +  branch);
> + return -EINVAL;
> + }
> + 

Re: [PATCH 5/5] drm/amdgpu: immedially invalidate PTEs

[Christian König]

Am 05.12.19 um 17:45 schrieb Felix Kuehling:

On 2019-12-05 8:39 a.m., Christian König wrote:

When a BO is evicted immedially invalidate the mapped PTEs.


I think you mentioned that this is just a proof of concept.


I also need this for immediately getting rid of mappings in DMA-buf 
based P2P.


I wouldn't submit the patch like this because it's overkill for VMs 
that don't want to use recoverable page faults and probably has a 
performance impact. I would do something specific to compute VMs in 
our MMU notifier.


I still need to test this, but I hope that it doesn't have that much 
impact on performance.


Regards,
Christian.



Regards,
  Felix



Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 -
  1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 839d6df394fc..e578113bfd55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2565,6 +2565,7 @@ void amdgpu_vm_bo_invalidate(struct 
amdgpu_device *adev,

   struct amdgpu_bo *bo, bool evicted)
  {
  struct amdgpu_vm_bo_base *bo_base;
+    int r;
    /* shadow bo doesn't have bo base, its validation needs its 
parent */

  if (bo->parent && bo->parent->shadow == bo)
@@ -2572,8 +2573,22 @@ void amdgpu_vm_bo_invalidate(struct 
amdgpu_device *adev,

    for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
  struct amdgpu_vm *vm = bo_base->vm;
+    struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+
+    if (bo->tbo.type != ttm_bo_type_kernel) {
+    struct amdgpu_bo_va *bo_va;
+
+    bo_va = container_of(bo_base, struct amdgpu_bo_va,
+ base);
+    r = amdgpu_vm_bo_update(adev, bo_va,
+    bo->tbo.base.resv != resv);
+    if (!r) {
+    amdgpu_vm_bo_idle(bo_base);
+    continue;
+    }
+    }
  -    if (evicted && bo->tbo.base.resv == 
vm->root.base.bo->tbo.base.resv) {

+    if (evicted && bo->tbo.base.resv == resv) {
  amdgpu_vm_bo_evicted(bo_base);
  continue;
  }


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Re: [PATCH 1/1] drm/amdkfd: Improve kfd_process lookup in kfd_ioctl

[Felix Kuehling]

On 2019-12-05 11:10 a.m., Philip Yang wrote:

One comment in line.

With it is fixed, this is reviewed by Philip Yang 

Philip

On 2019-12-04 11:13 p.m., Felix Kuehling wrote:
  diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c

index 8276601a122f..bb2f26532feb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -324,6 +324,8 @@ struct kfd_process *kfd_create_process(struct 
file *filep)

  (int)process->lead_thread->pid);
  }
  out:
+    if (process)

if (!IS_ERR_OR_NULL(process))


Thanks for catching that. I think !IS_ERR should be fine. Process should 
never be NULL here. Also the caller of this function only checks IS_ERR.


Regards,
  Felix





+    kref_get(>ref);
  mutex_unlock(_processes_mutex);
    return process;


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Re: reserving VRAM for page tables

[Christian König]

Yeah, but we should try to unify the memory management.

I mean we must have a common rational on how much memory page tables are 
going to use.


If we allow applications to oversubscribe or not is a completely 
different topic.


Regards,
Christian.

Am 05.12.19 um 18:05 schrieb Felix Kuehling:
I don't think this should go into amdgpu_vram_mgr. KFD tries to avoid 
running out of VRAM for page tables because we cannot oversubscribe 
memory within a process and we want to avoid compute processes 
evicting each other because that would mean thrashing. Those 
limitation don't apply to graphics contexts.


Regards,
  Felix


On 2019-12-05 5:50 a.m., Christian König wrote:


Sorry, just forgot to add the mailing list.

Am 05.12.19 um 11:49 schrieb Christian König:

Hi guys,

I've seen some patches flying by to change how much VRAM is reserved 
for page tables in the KFD.


Would it make sense to fully move that into amdgpu_vram_mgr.c?

Regards,
Christian.




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Re: reserving VRAM for page tables

[Felix Kuehling]

I don't think this should go into amdgpu_vram_mgr. KFD tries to avoid 
running out of VRAM for page tables because we cannot oversubscribe 
memory within a process and we want to avoid compute processes evicting 
each other because that would mean thrashing. Those limitation don't 
apply to graphics contexts.


Regards,
  Felix


On 2019-12-05 5:50 a.m., Christian König wrote:


Sorry, just forgot to add the mailing list.

Am 05.12.19 um 11:49 schrieb Christian König:

Hi guys,

I've seen some patches flying by to change how much VRAM is reserved 
for page tables in the KFD.


Would it make sense to fully move that into amdgpu_vram_mgr.c?

Regards,
Christian.



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Re: [PATCH 5/5] drm/amdgpu: immedially invalidate PTEs

[Felix Kuehling]

On 2019-12-05 8:39 a.m., Christian König wrote:

When a BO is evicted immedially invalidate the mapped PTEs.


I think you mentioned that this is just a proof of concept. I wouldn't 
submit the patch like this because it's overkill for VMs that don't want 
to use recoverable page faults and probably has a performance impact. I 
would do something specific to compute VMs in our MMU notifier.


Regards,
  Felix



Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 -
  1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 839d6df394fc..e578113bfd55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2565,6 +2565,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 struct amdgpu_bo *bo, bool evicted)
  {
struct amdgpu_vm_bo_base *bo_base;
+   int r;
  
  	/* shadow bo doesn't have bo base, its validation needs its parent */

if (bo->parent && bo->parent->shadow == bo)
@@ -2572,8 +2573,22 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
  
  	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {

struct amdgpu_vm *vm = bo_base->vm;
+   struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+
+   if (bo->tbo.type != ttm_bo_type_kernel) {
+   struct amdgpu_bo_va *bo_va;
+
+   bo_va = container_of(bo_base, struct amdgpu_bo_va,
+base);
+   r = amdgpu_vm_bo_update(adev, bo_va,
+   bo->tbo.base.resv != resv);
+   if (!r) {
+   amdgpu_vm_bo_idle(bo_base);
+   continue;
+   }
+   }
  
-		if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {

+   if (evicted && bo->tbo.base.resv == resv) {
amdgpu_vm_bo_evicted(bo_base);
continue;
}

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Re: [PATCH 3/5] drm/amdgpu: stop adding VM updates fences to the resv obj

[Felix Kuehling]

On 2019-12-05 8:39 a.m., Christian König wrote:

Don't add the VM update fences to the resv object and remove
the handling to stop implicitely syncing to them.

Ongoing updates prevent page tables from being evicted and we manually
block for all updates to complete before releasing PDs and PTS.

This way we can do updates even without the resv obj locked.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c|  6 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 30 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  4 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 11 +---
  4 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index f1e5fbef54d8..ae8bc766215c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -243,10 +243,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
/* VM updates are only interesting
 * for other VM updates and moves.


Thanks for updating the commit description. I think this comment should 
also be updated because "other VM updates" fences are no longer in the 
resv. Something like this: VM updates only sync with moves but not with 
user command submissions or KFD evictions fences. With that fixed, this 
patch is


Reviewed-by: Felix Kuehling 


 */
-   if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
-   (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
-   ((owner == AMDGPU_FENCE_OWNER_VM) !=
-(fence_owner == AMDGPU_FENCE_OWNER_VM)))
+   if (owner == AMDGPU_FENCE_OWNER_VM &&
+   fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED)
continue;
  
  			/* Ignore fence from the same owner and explicit one as

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a22bd57129d1..0d700e8154c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -562,8 +562,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
  {
entry->priority = 0;
entry->tv.bo = >root.base.bo->tbo;
-   /* One for the VM updates, one for TTM and one for the CS job */
-   entry->tv.num_shared = 3;
+   /* One for TTM and one for the CS job */
+   entry->tv.num_shared = 2;
entry->user_pages = NULL;
list_add(>tv.head, validated);
  }
@@ -2522,6 +2522,11 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
return false;
  
+	/* Don't evict VM page tables while they are updated */

+   if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
+   !dma_fence_is_signaled(bo_base->vm->last_delayed))
+   return false;
+
return true;
  }
  
@@ -2687,8 +2692,16 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,

   */
  long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
  {
-   return dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
-  true, true, timeout);
+   timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
+   true, true, timeout);
+   if (timeout <= 0)
+   return timeout;
+
+   timeout = dma_fence_wait_timeout(vm->last_direct, true, timeout);
+   if (timeout <= 0)
+   return timeout;
+
+   return dma_fence_wait_timeout(vm->last_delayed, true, timeout);
  }
  
  /**

@@ -2757,6 +2770,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
else
vm->update_funcs = _vm_sdma_funcs;
vm->last_update = NULL;
+   vm->last_direct = dma_fence_get_stub();
+   vm->last_delayed = dma_fence_get_stub();
  
  	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, );

if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
@@ -2807,6 +2822,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
vm->root.base.bo = NULL;
  
  error_free_delayed:

+   dma_fence_put(vm->last_direct);
+   dma_fence_put(vm->last_delayed);
drm_sched_entity_destroy(>delayed);
  
  error_free_direct:

@@ -3007,6 +3024,11 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct 
amdgpu_vm *vm)
vm->pasid = 0;
}
  
+	dma_fence_wait(vm->last_direct, false);

+   dma_fence_put(vm->last_direct);
+   dma_fence_wait(vm->last_delayed, false);
+   dma_fence_put(vm->last_delayed);
+
list_for_each_entry_safe(mapping, tmp, >freed, list) {
if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {

Re: [PATCH 2/5] drm/amdgpu: explicitely sync to VM updates v2

[Felix Kuehling]

On 2019-12-05 8:39 a.m., Christian König wrote:

Allows us to reduce the overhead while syncing to fences a bit.

v2: also drop adev parameter from the functions

Signed-off-by: Christian König 


Reviewed-by: Felix Kuehling 



---
  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  8 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 19 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c   | 13 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c  | 38 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h  |  8 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c   |  2 +-
  7 files changed, 51 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index b6d1958d514f..d8db5ecdf9c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -358,7 +358,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct 
amdgpu_sync *sync)
if (ret)
return ret;
  
-	return amdgpu_sync_fence(NULL, sync, vm->last_update, false);

+   return amdgpu_sync_fence(sync, vm->last_update, false);
  }
  
  static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)

@@ -751,7 +751,7 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
  
  	amdgpu_vm_clear_freed(adev, vm, _va->last_pt_update);
  
-	amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);

+   amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
  
  	return 0;

  }
@@ -770,7 +770,7 @@ static int update_gpuvm_pte(struct amdgpu_device *adev,
return ret;
}
  
-	return amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);

+   return amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
  }
  
  static int map_bo_to_gpuvm(struct amdgpu_device *adev,

@@ -2045,7 +2045,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, 
struct dma_fence **ef)
pr_debug("Memory eviction: Validate BOs failed. Try 
again\n");
goto validate_map_fail;
}
-   ret = amdgpu_sync_fence(NULL, _obj, bo->tbo.moving, false);
+   ret = amdgpu_sync_fence(_obj, bo->tbo.moving, false);
if (ret) {
pr_debug("Memory eviction: Sync BO fence failed. Try 
again\n");
goto validate_map_fail;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 9e0c99760367..614919f265b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -799,29 +799,23 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser 
*p)
if (r)
return r;
  
-	r = amdgpu_sync_fence(adev, >job->sync,

- fpriv->prt_va->last_pt_update, false);
+   r = amdgpu_sync_vm_fence(>job->sync, fpriv->prt_va->last_pt_update);
if (r)
return r;
  
  	if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {

-   struct dma_fence *f;
-
bo_va = fpriv->csa_va;
BUG_ON(!bo_va);
r = amdgpu_vm_bo_update(adev, bo_va, false);
if (r)
return r;
  
-		f = bo_va->last_pt_update;

-   r = amdgpu_sync_fence(adev, >job->sync, f, false);
+   r = amdgpu_sync_vm_fence(>job->sync, bo_va->last_pt_update);
if (r)
return r;
}
  
  	amdgpu_bo_list_for_each_entry(e, p->bo_list) {

-   struct dma_fence *f;
-
/* ignore duplicates */
bo = ttm_to_amdgpu_bo(e->tv.bo);
if (!bo)
@@ -835,8 +829,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
if (r)
return r;
  
-		f = bo_va->last_pt_update;

-   r = amdgpu_sync_fence(adev, >job->sync, f, false);
+   r = amdgpu_sync_vm_fence(>job->sync, bo_va->last_pt_update);
if (r)
return r;
}
@@ -849,7 +842,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
if (r)
return r;
  
-	r = amdgpu_sync_fence(adev, >job->sync, vm->last_update, false);

+   r = amdgpu_sync_vm_fence(>job->sync, vm->last_update);
if (r)
return r;
  
@@ -991,7 +984,7 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,

dma_fence_put(old);
}
  
-		r = amdgpu_sync_fence(p->adev, >job->sync, fence, true);

+   r = amdgpu_sync_fence(>job->sync, fence, true);
dma_fence_put(fence);
if (r)
return r;
@@ -1013,7 +1006,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
 

Re: [PATCH 4/5] drm/amdgpu: add VM eviction lock v2

[Felix Kuehling]

On 2019-12-05 8:39 a.m., Christian König wrote:

This allows to invalidate VM entries without taking the reservation lock.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 39 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 +++
  2 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0d700e8154c4..839d6df394fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -656,7 +656,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
  void *param)
  {
struct amdgpu_vm_bo_base *bo_base, *tmp;
-   int r = 0;
+   int r;
  
  	vm->bulk_moveable &= list_empty(>evicted);
  
@@ -665,7 +665,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  
  		r = validate(param, bo);

if (r)
-   break;
+   return r;
  
  		if (bo->tbo.type != ttm_bo_type_kernel) {

amdgpu_vm_bo_moved(bo_base);
@@ -678,7 +678,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
}
}
  
-	return r;

+   mutex_lock(>eviction_lock);
+   vm->evicting = false;
+   mutex_unlock(>eviction_lock);
+
+   return 0;
  }
  
  /**

@@ -1555,15 +1559,25 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
if (!(flags & AMDGPU_PTE_VALID))
owner = AMDGPU_FENCE_OWNER_KFD;
  
+	mutex_lock(>eviction_lock);

+   if (vm->evicting) {
+   r = EINPROGRESS;


Not sure about this error code. As far as I can find, this is normally 
used on non-blocking sockets. I found this explanation: 
https://stackoverflow.com/questions/8277970/what-are-possible-reason-for-socket-error-einprogress-in-solaris


Quote: "so there is another error for non-blocking connect: EINPROGRESS, 
which tells you that the operation is in progress and you should check 
its status later."


This call is neither non-blocking nor is the requested page table update 
in progress when this error is returned. So I'd think a better error to 
return here would be EBUSY.


Other than that, this patch is

Reviewed-by: Felix Kuehling 



+   goto error_unlock;
+   }
+
r = vm->update_funcs->prepare(, owner, exclusive);
if (r)
-   return r;
+   goto error_unlock;
  
  	r = amdgpu_vm_update_ptes(, start, last + 1, addr, flags);

if (r)
-   return r;
+   goto error_unlock;
  
-	return vm->update_funcs->commit(, fence);

+   r = vm->update_funcs->commit(, fence);
+
+error_unlock:
+   mutex_unlock(>eviction_lock);
+   return r;
  }
  
  /**

@@ -2522,11 +2536,19 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
return false;
  
+	/* Try to block ongoing updates */

+   if (!mutex_trylock(_base->vm->eviction_lock))
+   return false;
+
/* Don't evict VM page tables while they are updated */
if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
-   !dma_fence_is_signaled(bo_base->vm->last_delayed))
+   !dma_fence_is_signaled(bo_base->vm->last_delayed)) {
+   mutex_unlock(_base->vm->eviction_lock);
return false;
+   }
  
+	bo_base->vm->evicting = true;

+   mutex_unlock(_base->vm->eviction_lock);
return true;
  }
  
@@ -2773,6 +2795,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,

vm->last_direct = dma_fence_get_stub();
vm->last_delayed = dma_fence_get_stub();
  
+	mutex_init(>eviction_lock);

+   vm->evicting = false;
+
amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, );
if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d93ea9ad879e..d5613d184e99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -242,6 +242,10 @@ struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached   va;
  
+	/* Lock to prevent eviction while we are updating page tables */

+   struct mutexeviction_lock;
+   boolevicting;
+
/* BOs who needs a validation */
struct list_headevicted;
  

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[PATCH v3] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
 
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
 
-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}
 
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 
if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
 
ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

Re: [PATCH v3] drm/scheduler: rework entity creation

[Nirmoy]

Please ignore this one as I forgot to add the Reviewed-by


Regards,

Nirmoy

On 12/5/19 5:01 PM, Nirmoy Das wrote:

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
  drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
  drivers/gpu/drm/lima/lima_sched.c|  5 +-
  drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
  drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
  drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
  include/drm/gpu_scheduler.h  |  8 ++-
  11 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
  
  	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
  
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,

if (!rings[j]->adev)
continue;
  
-			rqs[num_rqs++] = [j]->sched.sched_rq[priority];

+   sched_list[num_rqs++] = [j]->sched;
}
  
  		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)

r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
  
  	if (enable) {

struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
  
  		ring = adev->mman.buffer_funcs_ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
  int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >uvd.inst[0].ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
  int amdgpu_vce_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >vce.ring[0];

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 

Re: [PATCH 1/1] drm/amdkfd: Improve kfd_process lookup in kfd_ioctl

[Philip Yang]

One comment in line.

With it is fixed, this is reviewed by Philip Yang 

Philip

On 2019-12-04 11:13 p.m., Felix Kuehling wrote:

Use filep->private_data to store a pointer to the kfd_process data
structure. Take an extra reference for that, which gets released in
the kfd_release callback. Check that the process calling kfd_ioctl
is the same that opened the file descriptor. Return -EBADF if it's
not, so that this error can be distinguished in user mode.

Signed-off-by: Felix Kuehling 
---
  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 30 
  drivers/gpu/drm/amd/amdkfd/kfd_process.c |  2 ++
  2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 2cb51d1e857c..1aebda4bbbe7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -42,6 +42,7 @@
  
  static long kfd_ioctl(struct file *, unsigned int, unsigned long);

  static int kfd_open(struct inode *, struct file *);
+static int kfd_release(struct inode *, struct file *);
  static int kfd_mmap(struct file *, struct vm_area_struct *);
  
  static const char kfd_dev_name[] = "kfd";

@@ -51,6 +52,7 @@ static const struct file_operations kfd_fops = {
.unlocked_ioctl = kfd_ioctl,
.compat_ioctl = kfd_ioctl,
.open = kfd_open,
+   .release = kfd_release,
.mmap = kfd_mmap,
  };
  
@@ -124,8 +126,13 @@ static int kfd_open(struct inode *inode, struct file *filep)

if (IS_ERR(process))
return PTR_ERR(process);
  
-	if (kfd_is_locked())

+   if (kfd_is_locked()) {
+   kfd_unref_process(process);
return -EAGAIN;
+   }
+
+   /* filep now owns the reference returned by kfd_create_process */
+   filep->private_data = process;
  
  	dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",

process->pasid, process->is_32bit_user_mode);
@@ -133,6 +140,16 @@ static int kfd_open(struct inode *inode, struct file 
*filep)
return 0;
  }
  
+static int kfd_release(struct inode *inode, struct file *filep)

+{
+   struct kfd_process *process = filep->private_data;
+
+   if (process)
+   kfd_unref_process(process);
+
+   return 0;
+}
+
  static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
void *data)
  {
@@ -1840,9 +1857,14 @@ static long kfd_ioctl(struct file *filep, unsigned int 
cmd, unsigned long arg)
  
  	dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
  
-	process = kfd_get_process(current);

-   if (IS_ERR(process)) {
-   dev_dbg(kfd_device, "no process\n");
+   /* Get the process struct from the filep. Only the process
+* that opened /dev/kfd can use the file descriptor. Child
+* processes need to create their own KFD device context.
+*/
+   process = filep->private_data;
+   if (process->lead_thread != current->group_leader) {
+   dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
+   retcode = -EBADF;
goto err_i1;
}
  
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c

index 8276601a122f..bb2f26532feb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -324,6 +324,8 @@ struct kfd_process *kfd_create_process(struct file *filep)
(int)process->lead_thread->pid);
}
  out:
+   if (process)

if (!IS_ERR_OR_NULL(process))


+   kref_get(>ref);
mutex_unlock(_processes_mutex);
  
  	return process;



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Re: [PATCH v2] drm/scheduler: rework entity creation

[Nirmoy]

On 12/5/19 4:43 PM, Christian König wrote:

Am 05.12.19 um 15:48 schrieb Nirmoy Das:


  EXPORT_SYMBOL(drm_sched_entity_set_priority);
@@ -490,18 +474,20 @@ void drm_sched_entity_select_rq(struct 
drm_sched_entity *entity)

  struct dma_fence *fence;
  struct drm_sched_rq *rq;
  -    if (spsc_queue_count(>job_queue) || 
entity->num_rq_list <= 1)
+    if (spsc_queue_count(>job_queue) || 
entity->num_sched_list <= 1)

  return;
    fence = READ_ONCE(entity->last_scheduled);
  if (fence && !dma_fence_is_signaled(fence))
  return;
  +    spin_lock(>rq_lock);
  rq = drm_sched_entity_get_free_sched(entity);
-    if (rq == entity->rq)
+    if (rq == entity->rq) {
+    spin_unlock(>rq_lock);
  return;
+    }


Should we redesign that into:

if (rq != entity->rq) {

-    spin_lock(>rq_lock);
  drm_sched_rq_remove_entity(entity->rq, entity);
  entity->rq = rq;

}

Would probably be easier to understand.


Yes, looks much cleaner with that. Sent a v3 with that change.
Apart from that the patch is Reviewed-by: Christian König 
.


Do you want to work on a follow up patch first or should I push this 
to drm-misc-next?
Please push this to drm-misc-next for now. I am thinking of doing rest 
of cleanup and on-demad entity creation for each HW IP together.


Regards,
Christian.



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[PATCH v2] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 70 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 77 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
 
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
 
-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}
 
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 
if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
 
ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>vce.entity, 

[PATCH] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 70 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 77 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
 
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
 
-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}
 
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 
if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
 
ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>vce.entity, 

[PATCH v3] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
 
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
 
-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}
 
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 
if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
 
ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>vce.entity, 

Re: [GIT PULL] Please pull hmm changes

[Jerome Glisse]

On Tue, Dec 03, 2019 at 02:42:12AM +, Jason Gunthorpe wrote:
> On Sat, Nov 30, 2019 at 10:23:31AM -0800, Linus Torvalds wrote:
> > On Sat, Nov 30, 2019 at 10:03 AM Linus Torvalds
> >  wrote:
> > >
> > > I'll try to figure the code out, but my initial reaction was "yeah,
> > > not in my VM".
> > 
> > Why is it ok to sometimes do
> > 
> > WRITE_ONCE(mni->invalidate_seq, cur_seq);
> > 
> > (to pair with the unlocked READ_ONCE), and sometimes then do
> > 
> > mni->invalidate_seq = mmn_mm->invalidate_seq;
> > 
> > My initial guess was that latter is only done at initialization time,
> > but at least in one case it's done *after* the mni has been added to
> > the mmn_mm (oh, how I despise those names - I can only repeat: WTF?).
> 
> Yes, the only occurrences are in the notifier_insert, under the
> spinlock. The one case where it is out of the natural order was to
> make the manipulation of seq a bit saner, but in all cases since the
> spinlock is held there is no way for another thread to get the pointer
> to the 'mmu_interval_notifier *' to do the unlocked read.
> 
> Regarding the ugly names.. Naming has been really hard here because
> currently everything is a 'mmu notifier' and the natural abberviations
> from there are crummy. Here is the basic summary:
> 
> struct mmu_notifier_mm (ie the mm->mmu_notifier_mm)
>-> mmn_mm
> struct mm_struct 
>-> mm
> struct mmu_notifier (ie the user subscription to the mm_struct)
>-> mn
> struct mmu_interval_notifier (the other kind of user subscription)
>-> mni

What about "interval" the context should already tell people
it is related to mmu notifier and thus a notifier. I would
just remove the notifier suffix, this would match the below
range.

> struct mmu_notifier_range (ie the args to invalidate_range)
>-> range

Yeah range as context should tell you it is related to mmu
notifier.

> 
> I can send a patch to switch mmn_mm to mmu_notifier_mm, which is the
> only pre-existing name for this value. But IIRC, it is a somewhat ugly
> with long line wrapping. 'mni' is a pain, I have to reflect on that.
> (honesly, I dislike mmu_notififer_mm quite a lot too)
> 
> I think it would be overall nicer with better names for the original
> structs. Perhaps:
> 
>  mmn_* - MMU notifier prefix
>  mmn_state <- struct mmu_notifier_mm
>  mmn_subscription (mmn_sub) <- struct mmu_notifier
>  mmn_range_subscription (mmn_range_sub) <- struct mmu_interval_notifier
>  mmn_invalidate_desc <- struct mmu_notifier_range

This looks good.

> 
> At least this is how I describe them in my mind..  This is a lot of
> churn, and spreads through many drivers. This is why I kept the names
> as-is and we ended up with the also quite bad 'mmu_interval_notifier'
> 
> Maybe just switch mmu_notifier_mm for mmn_state and leave the drivers
> alone?
> 
> Anyone on the CC list have advice?

Maybe we can do a semantic patch to do convertion and then Linus
can easily apply the patch by just re-running the coccinelle.

Cheers,
Jérôme

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Re: [PATCH v2] drm/scheduler: rework entity creation

[Christian König]

Am 05.12.19 um 15:48 schrieb Nirmoy Das:

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
  drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
  drivers/gpu/drm/lima/lima_sched.c|  5 +-
  drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
  drivers/gpu/drm/scheduler/sched_entity.c | 70 ++--
  drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
  include/drm/gpu_scheduler.h  |  8 ++-
  11 files changed, 77 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
  
  	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
  
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,

if (!rings[j]->adev)
continue;
  
-			rqs[num_rqs++] = [j]->sched.sched_rq[priority];

+   sched_list[num_rqs++] = [j]->sched;
}
  
  		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)

r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
  
  	if (enable) {

struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
  
  		ring = adev->mman.buffer_funcs_ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
  int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >uvd.inst[0].ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
  int amdgpu_vce_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >vce.ring[0];

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

Re: [RFC 0/7] UVD support for SI in amdgpu

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

You could enable UVD support on amdgpu using the original firmware from radeon, 
but you'd have to adjust the memory map on the GPU for SI to match radeon.  So 
updated firmware is not a requirement per se, it's just needed to keep the 
memory map the same as other GPUs.

Alex


From: amd-gfx  on behalf of Christian 
König 
Sent: Thursday, December 5, 2019 10:19 AM
To: Matthew Taylor ; amd-gfx@lists.freedesktop.org 

Subject: Re: [RFC 0/7] UVD support for SI in amdgpu

Hi Matthew,

Am 05.12.19 um 15:16 schrieb Matthew Taylor:
Hi,

Back in November 2017, Piotr Redlewski, provided some patches for UVD support 
in the SI cards, the thread had the same subject as this message.

The outcome of a conversation between himself and other developers on the list 
was to wait for something in updated firmware.  As this was over 2 years ago, I 
was wondering if the firmware has been updated sufficiently for Piotr's patches 
to be reconsidered or modified to deliver the UVD support for the SI cards?

we discussed that internally quite lengthy and the firmware will probably never 
be released.

To be honest we actually considering dropping SI support completely from amdgpu.

Regards,
Christian.


Thanks for you help

Kind Regards

Matthew Taylor



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Re: [RFC 0/7] UVD support for SI in amdgpu

[Christian König]

Hi Matthew,

Am 05.12.19 um 15:16 schrieb Matthew Taylor:

Hi,

Back in November 2017, Piotr Redlewski, provided some patches for UVD 
support in the SI cards, the thread had the same subject as this message.


The outcome of a conversation between himself and other developers on 
the list was to wait for something in updated firmware.  As this was 
over 2 years ago, I was wondering if the firmware has been updated 
sufficiently for Piotr's patches to be reconsidered or modified to 
deliver the UVD support for the SI cards?


we discussed that internally quite lengthy and the firmware will 
probably never be released.


To be honest we actually considering dropping SI support completely from 
amdgpu.


Regards,
Christian.



Thanks for you help

Kind Regards

Matthew Taylor

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RE: [PATCH] drm: Add FEC registers for LT-tunable repeaters

[Liu, Zhan]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Rodrigo Siqueira
> Sent: 2019/December/05, Thursday 8:59 AM
> To: =dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; amd-
> g...@lists.freedesktop.org
> Cc: Li, Sun peng (Leo) ; Berthe, Abdoulaye
> ; Jani Nikula ;
> Cornij, Nikola ; Manasi Navare
> ; Wentland, Harry
> ; Ville Syrjälä 
> Subject: [PATCH] drm: Add FEC registers for LT-tunable repeaters
> 
> FEC is supported since DP 1.4, and it was expanded for LT-tunable in DP 1.4a.
> This commit adds the address registers for
> FEC_ERROR_COUNT_PHY_REPEATER1 and
> FEC_CAPABILITY_PHY_REPEATER1.
> 
> Cc: Abdoulaye Berthe 
> Cc: Harry Wentland 
> Cc: Leo Li 
> Cc: Jani Nikula 
> Cc: Manasi Navare 
> Cc: Ville Syrjälä 
> Signed-off-by: Abdoulaye Berthe 
> Signed-off-by: Rodrigo Siqueira 

Looks good to me.
Reviewed-by: Zhan Liu 

> ---
>  include/drm/drm_dp_helper.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 51ecb5112ef8..b2057009aabc 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1042,6 +1042,8 @@
>  #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1
> 0xf0039 /* 1.3 */
>  #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1
> 0xf003b /* 1.3 */
>  #define DP_FEC_STATUS_PHY_REPEATER1  0xf0290 /*
> 1.4 */
> +#define DP_FEC_ERROR_COUNT_PHY_REPEATER10xf0291 /*
> 1.4 */
> +#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a
> */
> 
>  /* Repeater modes */
>  #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55/*
> 1.3 */
> --
> 2.24.0
> 
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Re: [PATCH] drm/scheduler: rework entity creation

[Nirmoy]

On 12/5/19 3:42 PM, Nirmoy Das wrote:

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
  drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
  drivers/gpu/drm/lima/lima_sched.c|  5 +-
  drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
  drivers/gpu/drm/scheduler/sched_entity.c | 70 ++--
  drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
  include/drm/gpu_scheduler.h  |  8 ++-
  11 files changed, 77 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
  
  	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
  
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,

if (!rings[j]->adev)
continue;
  
-			rqs[num_rqs++] = [j]->sched.sched_rq[priority];

+   sched_list[num_rqs++] = [j]->sched;
}
  
  		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)

r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
  
  	if (enable) {

struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
  
  		ring = adev->mman.buffer_funcs_ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
  int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >uvd.inst[0].ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
  int amdgpu_vce_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >vce.ring[0];

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

[RFC 0/7] UVD support for SI in amdgpu

[Matthew Taylor]

Hi,

Back in November 2017, Piotr Redlewski, provided some patches for UVD
support in the SI cards, the thread had the same subject as this message.

The outcome of a conversation between himself and other developers on the
list was to wait for something in updated firmware.  As this was over 2
years ago, I was wondering if the firmware has been updated sufficiently
for Piotr's patches to be reconsidered or modified to deliver the UVD
support for the SI cards?

Thanks for you help

Kind Regards

Matthew Taylor
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[PATCH] drm: Add FEC registers for LT-tunable repeaters

[Rodrigo Siqueira]

FEC is supported since DP 1.4, and it was expanded for LT-tunable in DP
1.4a. This commit adds the address registers for
FEC_ERROR_COUNT_PHY_REPEATER1 and FEC_CAPABILITY_PHY_REPEATER1.

Cc: Abdoulaye Berthe 
Cc: Harry Wentland 
Cc: Leo Li 
Cc: Jani Nikula 
Cc: Manasi Navare 
Cc: Ville Syrjälä 
Signed-off-by: Abdoulaye Berthe 
Signed-off-by: Rodrigo Siqueira 
---
 include/drm/drm_dp_helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 51ecb5112ef8..b2057009aabc 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1042,6 +1042,8 @@
 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1  0xf0039 /* 1.3 */
 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1  0xf003b /* 1.3 */
 #define DP_FEC_STATUS_PHY_REPEATER10xf0290 /* 1.4 */
+#define DP_FEC_ERROR_COUNT_PHY_REPEATER10xf0291 /* 1.4 */
+#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
 
 /* Repeater modes */
 #define DP_PHY_REPEATER_MODE_TRANSPARENT   0x55/* 1.3 */
-- 
2.24.0

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Re: [PATCH] drm/amd/display: rename a leftover DCN1_0 kconfig

[Alex Deucher]

On Thu, Dec 5, 2019 at 2:26 AM Xiaojie Yuan  wrote:
>
> Fixes: b86a1aa36a92 ("drm/amd/display: rename DCN1_0 kconfig to DCN")
> Signed-off-by: Xiaojie Yuan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 2645d20e8c4c..573c20d25e58 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -2181,7 +2181,7 @@ static void commit_planes_for_stream(struct dc *dc,
> }
> if (dc->hwss.program_front_end_for_ctx && update_type != 
> UPDATE_TYPE_FAST) {
> dc->hwss.program_front_end_for_ctx(dc, context);
> -#ifdef CONFIG_DRM_AMD_DC_DCN1_0
> +#ifdef CONFIG_DRM_AMD_DC_DCN
> if (dc->debug.validate_dml_output) {
> for (i = 0; i < dc->res_pool->pipe_count; i++) {
> struct pipe_ctx cur_pipe = 
> context->res_ctx.pipe_ctx[i];
> --
> 2.20.1
>
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[RFC PATCH] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  8 +--
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  7 +--
 drivers/gpu/drm/scheduler/sched_entity.c | 65 +---
 drivers/gpu/drm/v3d/v3d_drv.c|  7 +--
 include/drm/gpu_scheduler.h  |  9 ++--
 11 files changed, 69 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..e8f46c13d073 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
 
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
 
-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}
 
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ sched_list, num_rqs,
+ >guilty, priority);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..a960dd7c0711 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,12 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 
if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
 
ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity, ,
+ 1, NULL, DRM_SCHED_PRIORITY_KERNEL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..b803a8882864 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, ,
+ 1, NULL, DRM_SCHED_PRIORITY_NORMAL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..b44f28d44fb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>vce.entity, ,
+ 1, NULL, 

[PATCH 5/5] drm/amdgpu: immedially invalidate PTEs

[Christian König]

When a BO is evicted immedially invalidate the mapped PTEs.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 839d6df394fc..e578113bfd55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2565,6 +2565,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 struct amdgpu_bo *bo, bool evicted)
 {
struct amdgpu_vm_bo_base *bo_base;
+   int r;
 
/* shadow bo doesn't have bo base, its validation needs its parent */
if (bo->parent && bo->parent->shadow == bo)
@@ -2572,8 +2573,22 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 
for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
struct amdgpu_vm *vm = bo_base->vm;
+   struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+
+   if (bo->tbo.type != ttm_bo_type_kernel) {
+   struct amdgpu_bo_va *bo_va;
+
+   bo_va = container_of(bo_base, struct amdgpu_bo_va,
+base);
+   r = amdgpu_vm_bo_update(adev, bo_va,
+   bo->tbo.base.resv != resv);
+   if (!r) {
+   amdgpu_vm_bo_idle(bo_base);
+   continue;
+   }
+   }
 
-   if (evicted && bo->tbo.base.resv == 
vm->root.base.bo->tbo.base.resv) {
+   if (evicted && bo->tbo.base.resv == resv) {
amdgpu_vm_bo_evicted(bo_base);
continue;
}
-- 
2.17.1

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[PATCH 3/5] drm/amdgpu: stop adding VM updates fences to the resv obj

[Christian König]

Don't add the VM update fences to the resv object and remove
the handling to stop implicitely syncing to them.

Ongoing updates prevent page tables from being evicted and we manually
block for all updates to complete before releasing PDs and PTS.

This way we can do updates even without the resv obj locked.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c|  6 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 30 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  4 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 11 +---
 4 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index f1e5fbef54d8..ae8bc766215c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -243,10 +243,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
/* VM updates are only interesting
 * for other VM updates and moves.
 */
-   if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
-   (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
-   ((owner == AMDGPU_FENCE_OWNER_VM) !=
-(fence_owner == AMDGPU_FENCE_OWNER_VM)))
+   if (owner == AMDGPU_FENCE_OWNER_VM &&
+   fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED)
continue;
 
/* Ignore fence from the same owner and explicit one as
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a22bd57129d1..0d700e8154c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -562,8 +562,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 {
entry->priority = 0;
entry->tv.bo = >root.base.bo->tbo;
-   /* One for the VM updates, one for TTM and one for the CS job */
-   entry->tv.num_shared = 3;
+   /* One for TTM and one for the CS job */
+   entry->tv.num_shared = 2;
entry->user_pages = NULL;
list_add(>tv.head, validated);
 }
@@ -2522,6 +2522,11 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
return false;
 
+   /* Don't evict VM page tables while they are updated */
+   if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
+   !dma_fence_is_signaled(bo_base->vm->last_delayed))
+   return false;
+
return true;
 }
 
@@ -2687,8 +2692,16 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, 
uint32_t min_vm_size,
  */
 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
 {
-   return dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
-  true, true, timeout);
+   timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
+   true, true, timeout);
+   if (timeout <= 0)
+   return timeout;
+
+   timeout = dma_fence_wait_timeout(vm->last_direct, true, timeout);
+   if (timeout <= 0)
+   return timeout;
+
+   return dma_fence_wait_timeout(vm->last_delayed, true, timeout);
 }
 
 /**
@@ -2757,6 +2770,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
else
vm->update_funcs = _vm_sdma_funcs;
vm->last_update = NULL;
+   vm->last_direct = dma_fence_get_stub();
+   vm->last_delayed = dma_fence_get_stub();
 
amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, );
if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
@@ -2807,6 +2822,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
vm->root.base.bo = NULL;
 
 error_free_delayed:
+   dma_fence_put(vm->last_direct);
+   dma_fence_put(vm->last_delayed);
drm_sched_entity_destroy(>delayed);
 
 error_free_direct:
@@ -3007,6 +3024,11 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct 
amdgpu_vm *vm)
vm->pasid = 0;
}
 
+   dma_fence_wait(vm->last_direct, false);
+   dma_fence_put(vm->last_direct);
+   dma_fence_wait(vm->last_delayed, false);
+   dma_fence_put(vm->last_delayed);
+
list_for_each_entry_safe(mapping, tmp, >freed, list) {
if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
amdgpu_vm_prt_fini(adev, vm);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index db561765453b..d93ea9ad879e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -269,6 +269,10 @@ struct amdgpu_vm {
struct drm_sched_entity direct;
struct drm_sched_entity delayed;
 
+   /* Last 

[PATCH 2/5] drm/amdgpu: explicitely sync to VM updates v2

[Christian König]

Allows us to reduce the overhead while syncing to fences a bit.

v2: also drop adev parameter from the functions

Signed-off-by: Christian König 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  8 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 19 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c   | 13 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c  | 38 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h  |  8 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c   |  2 +-
 7 files changed, 51 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index b6d1958d514f..d8db5ecdf9c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -358,7 +358,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct 
amdgpu_sync *sync)
if (ret)
return ret;
 
-   return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
+   return amdgpu_sync_fence(sync, vm->last_update, false);
 }
 
 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
@@ -751,7 +751,7 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
 
amdgpu_vm_clear_freed(adev, vm, _va->last_pt_update);
 
-   amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
+   amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
 
return 0;
 }
@@ -770,7 +770,7 @@ static int update_gpuvm_pte(struct amdgpu_device *adev,
return ret;
}
 
-   return amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
+   return amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
 }
 
 static int map_bo_to_gpuvm(struct amdgpu_device *adev,
@@ -2045,7 +2045,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, 
struct dma_fence **ef)
pr_debug("Memory eviction: Validate BOs failed. Try 
again\n");
goto validate_map_fail;
}
-   ret = amdgpu_sync_fence(NULL, _obj, bo->tbo.moving, false);
+   ret = amdgpu_sync_fence(_obj, bo->tbo.moving, false);
if (ret) {
pr_debug("Memory eviction: Sync BO fence failed. Try 
again\n");
goto validate_map_fail;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 9e0c99760367..614919f265b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -799,29 +799,23 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser 
*p)
if (r)
return r;
 
-   r = amdgpu_sync_fence(adev, >job->sync,
- fpriv->prt_va->last_pt_update, false);
+   r = amdgpu_sync_vm_fence(>job->sync, fpriv->prt_va->last_pt_update);
if (r)
return r;
 
if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
-   struct dma_fence *f;
-
bo_va = fpriv->csa_va;
BUG_ON(!bo_va);
r = amdgpu_vm_bo_update(adev, bo_va, false);
if (r)
return r;
 
-   f = bo_va->last_pt_update;
-   r = amdgpu_sync_fence(adev, >job->sync, f, false);
+   r = amdgpu_sync_vm_fence(>job->sync, bo_va->last_pt_update);
if (r)
return r;
}
 
amdgpu_bo_list_for_each_entry(e, p->bo_list) {
-   struct dma_fence *f;
-
/* ignore duplicates */
bo = ttm_to_amdgpu_bo(e->tv.bo);
if (!bo)
@@ -835,8 +829,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
if (r)
return r;
 
-   f = bo_va->last_pt_update;
-   r = amdgpu_sync_fence(adev, >job->sync, f, false);
+   r = amdgpu_sync_vm_fence(>job->sync, bo_va->last_pt_update);
if (r)
return r;
}
@@ -849,7 +842,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
if (r)
return r;
 
-   r = amdgpu_sync_fence(adev, >job->sync, vm->last_update, false);
+   r = amdgpu_sync_vm_fence(>job->sync, vm->last_update);
if (r)
return r;
 
@@ -991,7 +984,7 @@ static int amdgpu_cs_process_fence_dep(struct 
amdgpu_cs_parser *p,
dma_fence_put(old);
}
 
-   r = amdgpu_sync_fence(p->adev, >job->sync, fence, true);
+   r = amdgpu_sync_fence(>job->sync, fence, true);
dma_fence_put(fence);
if (r)
return r;
@@ -1013,7 +1006,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
return r;
}
 
-   r 

[PATCH 1/5] drm/amdgpu: move VM eviction decision into amdgpu_vm.c

[Christian König]

When a page tables needs to be evicted the VM code should
decide if that is possible or not.

Signed-off-by: Christian König 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 22 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  1 +
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..81f6764f1ba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1489,11 +1489,8 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct 
ttm_buffer_object *bo,
struct dma_fence *f;
int i;
 
-   /* Don't evict VM page tables while they are busy, otherwise we can't
-* cleanly handle page faults.
-*/
if (bo->type == ttm_bo_type_kernel &&
-   !dma_resv_test_signaled_rcu(bo->base.resv, true))
+   !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
return false;
 
/* If bo is a KFD BO, check if the bo belongs to the current process.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a94c4faa5af1..a22bd57129d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2503,6 +2503,28 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
kfree(bo_va);
 }
 
+/**
+ * amdgpu_vm_evictable - check if we can evict a VM
+ *
+ * @bo: A page table of the VM.
+ *
+ * Check if it is possible to evict a VM.
+ */
+bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
+{
+   struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
+
+   /* Page tables of a destroyed VM can go away immediately */
+   if (!bo_base || !bo_base->vm)
+   return true;
+
+   /* Don't evict VM page tables while they are busy */
+   if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
+   return false;
+
+   return true;
+}
+
 /**
  * amdgpu_vm_bo_invalidate - mark the bo as invalid
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 76fcf853035c..db561765453b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -381,6 +381,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
bool clear);
+bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 struct amdgpu_bo *bo, bool evicted);
 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
-- 
2.17.1

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[PATCH 4/5] drm/amdgpu: add VM eviction lock v2

[Christian König]

This allows to invalidate VM entries without taking the reservation lock.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 39 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 +++
 2 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0d700e8154c4..839d6df394fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -656,7 +656,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
  void *param)
 {
struct amdgpu_vm_bo_base *bo_base, *tmp;
-   int r = 0;
+   int r;
 
vm->bulk_moveable &= list_empty(>evicted);
 
@@ -665,7 +665,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
 
r = validate(param, bo);
if (r)
-   break;
+   return r;
 
if (bo->tbo.type != ttm_bo_type_kernel) {
amdgpu_vm_bo_moved(bo_base);
@@ -678,7 +678,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
}
}
 
-   return r;
+   mutex_lock(>eviction_lock);
+   vm->evicting = false;
+   mutex_unlock(>eviction_lock);
+
+   return 0;
 }
 
 /**
@@ -1555,15 +1559,25 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
if (!(flags & AMDGPU_PTE_VALID))
owner = AMDGPU_FENCE_OWNER_KFD;
 
+   mutex_lock(>eviction_lock);
+   if (vm->evicting) {
+   r = EINPROGRESS;
+   goto error_unlock;
+   }
+
r = vm->update_funcs->prepare(, owner, exclusive);
if (r)
-   return r;
+   goto error_unlock;
 
r = amdgpu_vm_update_ptes(, start, last + 1, addr, flags);
if (r)
-   return r;
+   goto error_unlock;
 
-   return vm->update_funcs->commit(, fence);
+   r = vm->update_funcs->commit(, fence);
+
+error_unlock:
+   mutex_unlock(>eviction_lock);
+   return r;
 }
 
 /**
@@ -2522,11 +2536,19 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
return false;
 
+   /* Try to block ongoing updates */
+   if (!mutex_trylock(_base->vm->eviction_lock))
+   return false;
+
/* Don't evict VM page tables while they are updated */
if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
-   !dma_fence_is_signaled(bo_base->vm->last_delayed))
+   !dma_fence_is_signaled(bo_base->vm->last_delayed)) {
+   mutex_unlock(_base->vm->eviction_lock);
return false;
+   }
 
+   bo_base->vm->evicting = true;
+   mutex_unlock(_base->vm->eviction_lock);
return true;
 }
 
@@ -2773,6 +2795,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
vm->last_direct = dma_fence_get_stub();
vm->last_delayed = dma_fence_get_stub();
 
+   mutex_init(>eviction_lock);
+   vm->evicting = false;
+
amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, );
if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d93ea9ad879e..d5613d184e99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -242,6 +242,10 @@ struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached   va;
 
+   /* Lock to prevent eviction while we are updating page tables */
+   struct mutexeviction_lock;
+   boolevicting;
+
/* BOs who needs a validation */
struct list_headevicted;
 
-- 
2.17.1

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Re: [RFC PATCH] drm/scheduler: rework entity creation

[Das, Nirmoy]

[AMD Official Use Only - Internal Distribution Only]

Thanks Christian,


I will modify and resend.

Regards,
Nirmoy

From: Koenig, Christian 
Sent: Thursday, December 5, 2019 1:29:49 PM
To: Das, Nirmoy ; Nirmoy Das ; 
Deucher, Alexander ; Ho, Kenny 
Cc: amd-gfx@lists.freedesktop.org ; Das, Nirmoy 

Subject: Re: [RFC PATCH] drm/scheduler: rework entity creation

Am 05.12.19 um 12:04 schrieb Nirmoy:
> Hi Christian,
>
> I am not exactly sure about drm_sched_entity_set_priority() I wonder
> if just changing
>
> entity->priority  to ctx->override_priority should work. With this
> change drm_sched_entity_select_rq()
>
> will chose a rq based on entity->priority which seems to me correct.
> But is this enough to fix the old bug you were
>
> talking about which mess up already scheduled job on priority change?

Yes, that should perfectly do it.

>
> okay I just realized I need a lock to make sure
>
> drm_sched_entity_set_priority() and drm_sched_entity_select_rq()
> shouldn't happen at the same time.

Yeah, you probably need to grab the lock and make sure that you get the
priority to use while holding the lock as well.

Regards,
Christian.

>
>
> Regards,
>
> Nirmoy
>
>
> On 12/5/19 11:52 AM, Nirmoy Das wrote:
>> Entity currently keeps a copy of run_queue list and modify it in
>> drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
>> list. Use drm_gpu_scheduler list instead of drm_sched_rq list
>> in drm_sched_entity struct. In this way we can select a runqueue based
>> on entity/ctx's priority for a  drm scheduler.
>>
>> Signed-off-by: Nirmoy Das 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 +--
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  7 +--
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 +--
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 +--
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
>>   drivers/gpu/drm/etnaviv/etnaviv_drv.c|  8 +--
>>   drivers/gpu/drm/lima/lima_sched.c|  5 +-
>>   drivers/gpu/drm/panfrost/panfrost_job.c  |  7 +--
>>   drivers/gpu/drm/scheduler/sched_entity.c | 65 +---
>>   drivers/gpu/drm/v3d/v3d_drv.c|  7 +--
>>   include/drm/gpu_scheduler.h  |  9 ++--
>>   11 files changed, 69 insertions(+), 74 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> index a0d3d7b756eb..e8f46c13d073 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> @@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device
>> *adev,
>> for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
>>   struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
>> -struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
>> +struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
>>   unsigned num_rings = 0;
>>   unsigned num_rqs = 0;
>>   @@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct
>> amdgpu_device *adev,
>>   if (!rings[j]->adev)
>>   continue;
>>   -rqs[num_rqs++] = [j]->sched.sched_rq[priority];
>> +sched_list[num_rqs++] = [j]->sched;
>>   }
>> for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
>>   r = drm_sched_entity_init(>entities[i][j].entity,
>> -  rqs, num_rqs, >guilty);
>> +  sched_list, num_rqs,
>> +  >guilty, priority);
>>   if (r)
>>   goto error_cleanup_entities;
>>   }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index 19ffe00d9072..a960dd7c0711 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -1957,11 +1957,12 @@ void
>> amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool
>> enable)
>> if (enable) {
>>   struct amdgpu_ring *ring;
>> -struct drm_sched_rq *rq;
>> +struct drm_gpu_scheduler *sched;
>> ring = adev->mman.buffer_funcs_ring;
>> -rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
>> -r = drm_sched_entity_init(>mman.entity, , 1, NULL);
>> +sched = >sched;
>> +r = drm_sched_entity_init(>mman.entity, ,
>> +  1, NULL, DRM_SCHED_PRIORITY_KERNEL);
>>   if (r) {
>>   DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
>> r);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>> index e324bfe6c58f..b803a8882864 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>> @@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
>>   int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
>>   {
>>   struct amdgpu_ring *ring;
>> -struct drm_sched_rq *rq;
>> +

Re: [PATCH 1/4] drm/amd/powerplay: implement interface to retrieve gpu temperature for renoir

[Wang, Kevin(Yang)]

[AMD Official Use Only - Internal Distribution Only]

Series are Reviewed-by: Kevin Wang 

Best Regards,
Kevin

From: amd-gfx  on behalf of Xiaomeng Hou 

Sent: Thursday, December 5, 2019 7:50 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Hou, Xiaomeng (Matthew) 
Subject: [PATCH 1/4] drm/amd/powerplay: implement interface to retrieve gpu 
temperature for renoir

add sensor interface of get gpu temperature for debugfs.

Change-Id: I2499b6652fad6d5d776b6ed4cd5157636583ed39
Signed-off-by: Xiaomeng Hou 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 3788047bd704..3f6f0ebf1fbe 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -429,6 +429,24 @@ static int renoir_get_gpu_power(struct smu_context *smu, 
uint32_t *value)
 return 0;
 }

+static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
+{
+   int ret = 0;
+   SmuMetrics_t metrics;
+
+   if (!value)
+   return -EINVAL;
+
+   ret = renoir_get_metrics_table(smu, );
+   if (ret)
+   return ret;
+
+   *value = (metrics.GfxTemperature / 100) *
+   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+   return 0;
+}
+
 static int renoir_get_current_activity_percent(struct smu_context *smu,
enum amd_pp_sensors sensor,
uint32_t *value)
@@ -787,6 +805,10 @@ static int renoir_read_sensor(struct smu_context *smu,
 ret = renoir_get_gpu_power(smu, (uint32_t *)data);
 *size = 4;
 break;
+   case AMDGPU_PP_SENSOR_GPU_TEMP:
+   ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
+   *size = 4;
+   break;
 default:
 ret = smu_v12_0_read_sensor(smu, sensor, data, size);
 }
--
2.24.0

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Re: [RFC PATCH] drm/scheduler: rework entity creation

[Christian König]

Am 05.12.19 um 12:04 schrieb Nirmoy:

Hi Christian,

I am not exactly sure about drm_sched_entity_set_priority() I wonder 
if just changing


entity->priority  to ctx->override_priority should work. With this 
change drm_sched_entity_select_rq()


will chose a rq based on entity->priority which seems to me correct. 
But is this enough to fix the old bug you were


talking about which mess up already scheduled job on priority change?


Yes, that should perfectly do it.



okay I just realized I need a lock to make sure

drm_sched_entity_set_priority() and drm_sched_entity_select_rq() 
shouldn't happen at the same time.


Yeah, you probably need to grab the lock and make sure that you get the 
priority to use while holding the lock as well.


Regards,
Christian.




Regards,

Nirmoy


On 12/5/19 11:52 AM, Nirmoy Das wrote:

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
  drivers/gpu/drm/etnaviv/etnaviv_drv.c    |  8 +--
  drivers/gpu/drm/lima/lima_sched.c    |  5 +-
  drivers/gpu/drm/panfrost/panfrost_job.c  |  7 +--
  drivers/gpu/drm/scheduler/sched_entity.c | 65 +---
  drivers/gpu/drm/v3d/v3d_drv.c    |  7 +--
  include/drm/gpu_scheduler.h  |  9 ++--
  11 files changed, 69 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

index a0d3d7b756eb..e8f46c13d073 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device 
*adev,

    for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
  struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-    struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+    struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
  unsigned num_rings = 0;
  unsigned num_rqs = 0;
  @@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct 
amdgpu_device *adev,

  if (!rings[j]->adev)
  continue;
  -    rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+    sched_list[num_rqs++] = [j]->sched;
  }
    for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
  r = drm_sched_entity_init(>entities[i][j].entity,
-  rqs, num_rqs, >guilty);
+  sched_list, num_rqs,
+  >guilty, priority);
  if (r)
  goto error_cleanup_entities;
  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index 19ffe00d9072..a960dd7c0711 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,12 @@ void 
amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool 
enable)

    if (enable) {
  struct amdgpu_ring *ring;
-    struct drm_sched_rq *rq;
+    struct drm_gpu_scheduler *sched;
    ring = adev->mman.buffer_funcs_ring;
-    rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-    r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+    sched = >sched;
+    r = drm_sched_entity_init(>mman.entity, ,
+  1, NULL, DRM_SCHED_PRIORITY_KERNEL);
  if (r) {
  DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
    r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

index e324bfe6c58f..b803a8882864 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
  int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
  {
  struct amdgpu_ring *ring;
-    struct drm_sched_rq *rq;
+    struct drm_gpu_scheduler *sched;
  int r;
    ring = >uvd.inst[0].ring;
-    rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-    r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+    sched = >sched;
+    r = drm_sched_entity_init(>uvd.entity, ,
+  1, NULL, DRM_SCHED_PRIORITY_NORMAL);
  if (r) {
  DRM_ERROR("Failed setting up UVD kernel entity.\n");
  return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

index 46b590af2fd2..b44f28d44fb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ 

Re: [RFC PATCH] drm/scheduler: rework entity creation

[Christian König]

Am 05.12.19 um 11:52 schrieb Nirmoy Das:

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.


Looks good to me in general only a few nit picks below.



Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
  drivers/gpu/drm/etnaviv/etnaviv_drv.c|  8 +--
  drivers/gpu/drm/lima/lima_sched.c|  5 +-
  drivers/gpu/drm/panfrost/panfrost_job.c  |  7 +--
  drivers/gpu/drm/scheduler/sched_entity.c | 65 +---
  drivers/gpu/drm/v3d/v3d_drv.c|  7 +--
  include/drm/gpu_scheduler.h  |  9 ++--
  11 files changed, 69 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..e8f46c13d073 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
  
  	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
  
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,

if (!rings[j]->adev)
continue;
  
-			rqs[num_rqs++] = [j]->sched.sched_rq[priority];

+   sched_list[num_rqs++] = [j]->sched;
}
  
  		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)

r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ sched_list, num_rqs,
+ >guilty, priority);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..a960dd7c0711 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,12 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
  
  	if (enable) {

struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
  
  		ring = adev->mman.buffer_funcs_ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity, ,
+ 1, NULL, DRM_SCHED_PRIORITY_KERNEL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..b803a8882864 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
  int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >uvd.inst[0].ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, ,
+ 1, NULL, DRM_SCHED_PRIORITY_NORMAL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..b44f28d44fb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
  int amdgpu_vce_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >vce.ring[0];

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

[PATCH 4/4] drm/amd/powerplay: correct the value retrieved through GPU_LOAD sensor interface

[Xiaomeng Hou]

the unit of variable AverageGfxActivity defined in smu12 metrics
struct is centi, so the retrieved value should be divided by 100 before
return.

Change-Id: Ia7873597977cb5479b015d632ab24a7aa20a1cfb
Signed-off-by: Xiaomeng Hou 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 1e6b79cff23c..8fe8fefcbbbf 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -509,7 +509,7 @@ static int renoir_get_current_activity_percent(struct 
smu_context *smu,
 
switch (sensor) {
case AMDGPU_PP_SENSOR_GPU_LOAD:
-   *value = metrics.AverageGfxActivity;
+   *value = metrics.AverageGfxActivity / 100;
break;
default:
pr_err("Invalid sensor for retrieving clock activity\n");
-- 
2.24.0

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[PATCH 3/4] drm/amd/powerplay: implement the get_enabled_mask callback for smu12

[Xiaomeng Hou]

implement sensor interface of feature mask for debugfs.

Change-Id: Ia085aab4c82b978e1e8c8ddc3ca6278b9dec8005
Signed-off-by: Xiaomeng Hou 
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  3 ++
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c|  1 +
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 29 +++
 3 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 8b4069c8e668..1e58eefea77b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -76,6 +76,9 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu);
 
 int smu_v12_0_populate_smc_tables(struct smu_context *smu);
 
+int smu_v12_0_get_enabled_mask(struct smu_context *smu,
+ uint32_t *feature_mask, uint32_t num);
+
 int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
  enum smu_clk_type clk_id,
  uint32_t *value);
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 1c26d7798146..1e6b79cff23c 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -899,6 +899,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.init_smc_tables = smu_v12_0_init_smc_tables,
.fini_smc_tables = smu_v12_0_fini_smc_tables,
.populate_smc_tables = smu_v12_0_populate_smc_tables,
+   .get_enabled_mask = smu_v12_0_get_enabled_mask,
.get_current_clk_freq = smu_v12_0_get_current_clk_freq,
.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
.mode2_reset = smu_v12_0_mode2_reset,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 9022e60ac9dc..f6993c470fd2 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -354,6 +354,35 @@ int smu_v12_0_populate_smc_tables(struct smu_context *smu)
return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, 
smu_table->clocks_table, false);
 }
 
+int smu_v12_0_get_enabled_mask(struct smu_context *smu,
+ uint32_t *feature_mask, uint32_t num)
+{
+   uint32_t feature_mask_high = 0, feature_mask_low = 0;
+   int ret = 0;
+
+   if (!feature_mask || num < 2)
+   return -EINVAL;
+
+   ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
+   if (ret)
+   return ret;
+   ret = smu_read_smc_arg(smu, _mask_high);
+   if (ret)
+   return ret;
+
+   ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
+   if (ret)
+   return ret;
+   ret = smu_read_smc_arg(smu, _mask_low);
+   if (ret)
+   return ret;
+
+   feature_mask[0] = feature_mask_low;
+   feature_mask[1] = feature_mask_high;
+
+   return ret;
+}
+
 int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
  enum smu_clk_type clk_id,
  uint32_t *value)
-- 
2.24.0

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[PATCH 2/4] drm/amd/powerplay: implement interface to retrieve clock freq for renoir

[Xiaomeng Hou]

implement smu12 get_clk_freq interface to get clock frequency like
MCLK/SCLK.

Change-Id: I2481d649811c15cd2d8e2741242b2928a32413fc
Signed-off-by: Xiaomeng Hou 
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  4 ++
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 49 +++
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 20 
 3 files changed, 73 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 44c65dd8850d..8b4069c8e668 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -76,6 +76,10 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu);
 
 int smu_v12_0_populate_smc_tables(struct smu_context *smu);
 
+int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
+ enum smu_clk_type clk_id,
+ uint32_t *value);
+
 int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type 
clk_type,
 uint32_t *min, uint32_t *max);
 
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 3f6f0ebf1fbe..1c26d7798146 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -31,6 +31,9 @@
 #include "renoir_ppt.h"
 
 
+#define CLK_MAP(clk, index) \
+   [SMU_##clk] = {1, (index)}
+
 #define MSG_MAP(msg, index) \
[SMU_MSG_##msg] = {1, (index)}
 
@@ -104,6 +107,14 @@ static struct smu_12_0_cmn2aisc_mapping 
renoir_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(SetHardMinFclkByFreq,   PPSMC_MSG_SetHardMinFclkByFreq),
 };
 
+static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = {
+   CLK_MAP(GFXCLK, CLOCK_GFXCLK),
+   CLK_MAP(SCLK,   CLOCK_GFXCLK),
+   CLK_MAP(SOCCLK, CLOCK_SOCCLK),
+   CLK_MAP(UCLK, CLOCK_UMCCLK),
+   CLK_MAP(MCLK, CLOCK_UMCCLK),
+};
+
 static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
TAB_MAP_VALID(WATERMARKS),
TAB_MAP_INVALID(CUSTOM_DPM),
@@ -125,6 +136,21 @@ static int renoir_get_smu_msg_index(struct smu_context 
*smc, uint32_t index)
return mapping.map_to;
 }
 
+static int renoir_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+{
+   struct smu_12_0_cmn2aisc_mapping mapping;
+
+   if (index >= SMU_CLK_COUNT)
+   return -EINVAL;
+
+   mapping = renoir_clk_map[index];
+   if (!(mapping.valid_mapping)) {
+   return -EINVAL;
+   }
+
+   return mapping.map_to;
+}
+
 static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
 {
struct smu_12_0_cmn2aisc_mapping mapping;
@@ -352,6 +378,26 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context 
*smu, bool enable)
return ret;
 }
 
+static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
+  enum smu_clk_type clk_type,
+  uint32_t *value)
+{
+   int ret = 0, clk_id = 0;
+   SmuMetrics_t metrics;
+
+   ret = renoir_get_metrics_table(smu, );
+   if (ret)
+   return ret;
+
+   clk_id = smu_clk_get_index(smu, clk_type);
+   if (clk_id < 0)
+   return clk_id;
+
+   *value = metrics.ClockFrequency[clk_id];
+
+   return ret;
+}
+
 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
 {
int ret = 0, i = 0;
@@ -819,6 +865,7 @@ static int renoir_read_sensor(struct smu_context *smu,
 
 static const struct pptable_funcs renoir_ppt_funcs = {
.get_smu_msg_index = renoir_get_smu_msg_index,
+   .get_smu_clk_index = renoir_get_smu_clk_index,
.get_smu_table_index = renoir_get_smu_table_index,
.tables_init = renoir_tables_init,
.set_power_state = NULL,
@@ -827,6 +874,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.get_current_power_state = renoir_get_current_power_state,
.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
+   .get_current_clk_freq_by_table = renoir_get_current_clk_freq_by_table,
.force_dpm_limit_value = renoir_force_dpm_limit_value,
.unforce_dpm_levels = renoir_unforce_dpm_levels,
.get_workload_type = renoir_get_workload_type,
@@ -851,6 +899,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.init_smc_tables = smu_v12_0_init_smc_tables,
.fini_smc_tables = smu_v12_0_fini_smc_tables,
.populate_smc_tables = smu_v12_0_populate_smc_tables,
+   .get_current_clk_freq = smu_v12_0_get_current_clk_freq,
.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
.mode2_reset = smu_v12_0_mode2_reset,
.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
diff --git 

[PATCH 1/4] drm/amd/powerplay: implement interface to retrieve gpu temperature for renoir

[Xiaomeng Hou]

add sensor interface of get gpu temperature for debugfs.

Change-Id: I2499b6652fad6d5d776b6ed4cd5157636583ed39
Signed-off-by: Xiaomeng Hou 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 3788047bd704..3f6f0ebf1fbe 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -429,6 +429,24 @@ static int renoir_get_gpu_power(struct smu_context *smu, 
uint32_t *value)
return 0;
 }
 
+static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
+{
+   int ret = 0;
+   SmuMetrics_t metrics;
+
+   if (!value)
+   return -EINVAL;
+
+   ret = renoir_get_metrics_table(smu, );
+   if (ret)
+   return ret;
+
+   *value = (metrics.GfxTemperature / 100) *
+   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+   return 0;
+}
+
 static int renoir_get_current_activity_percent(struct smu_context *smu,
   enum amd_pp_sensors sensor,
   uint32_t *value)
@@ -787,6 +805,10 @@ static int renoir_read_sensor(struct smu_context *smu,
ret = renoir_get_gpu_power(smu, (uint32_t *)data);
*size = 4;
break;
+   case AMDGPU_PP_SENSOR_GPU_TEMP:
+   ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
+   *size = 4;
+   break;
default:
ret = smu_v12_0_read_sensor(smu, sensor, data, size);
}
-- 
2.24.0

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Re: [RFC PATCH] drm/scheduler: rework entity creation

[Nirmoy]

Hi Christian,

I am not exactly sure about drm_sched_entity_set_priority() I wonder if 
just changing


entity->priority  to ctx->override_priority should work. With this 
change drm_sched_entity_select_rq()


will chose a rq based on entity->priority which seems to me correct. But 
is this enough to fix the old bug you were


talking about which mess up already scheduled job on priority change?


okay I just realized I need a lock to make sure

drm_sched_entity_set_priority() and drm_sched_entity_select_rq() 
shouldn't happen at the same time.



Regards,

Nirmoy


On 12/5/19 11:52 AM, Nirmoy Das wrote:

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
  drivers/gpu/drm/etnaviv/etnaviv_drv.c|  8 +--
  drivers/gpu/drm/lima/lima_sched.c|  5 +-
  drivers/gpu/drm/panfrost/panfrost_job.c  |  7 +--
  drivers/gpu/drm/scheduler/sched_entity.c | 65 +---
  drivers/gpu/drm/v3d/v3d_drv.c|  7 +--
  include/drm/gpu_scheduler.h  |  9 ++--
  11 files changed, 69 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..e8f46c13d073 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
  
  	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
  
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,

if (!rings[j]->adev)
continue;
  
-			rqs[num_rqs++] = [j]->sched.sched_rq[priority];

+   sched_list[num_rqs++] = [j]->sched;
}
  
  		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)

r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ sched_list, num_rqs,
+ >guilty, priority);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..a960dd7c0711 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,12 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
  
  	if (enable) {

struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
  
  		ring = adev->mman.buffer_funcs_ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity, ,
+ 1, NULL, DRM_SCHED_PRIORITY_KERNEL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..b803a8882864 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
  int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
  {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
  
  	ring = >uvd.inst[0].ring;

-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, ,
+ 1, NULL, DRM_SCHED_PRIORITY_NORMAL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..b44f28d44fb4 100644
--- 

Re: reserving VRAM for page tables

[Christian König]

Sorry, just forgot to add the mailing list.

Am 05.12.19 um 11:49 schrieb Christian König:

Hi guys,

I've seen some patches flying by to change how much VRAM is reserved 
for page tables in the KFD.


Would it make sense to fully move that into amdgpu_vram_mgr.c?

Regards,
Christian.


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[PATCH v2] drm/dp_mst: Remove VCPI while disabling topology mgr

[Wayne Lin]

[Why]

This patch is trying to address the issue observed when hotplug DP
daisy chain monitors.

e.g.
src-mstb-mstb-sst -> src (unplug) mstb-mstb-sst -> src-mstb-mstb-sst
(plug in again)

Once unplug a DP MST capable device, driver will call
drm_dp_mst_topology_mgr_set_mst() to disable MST. In this function,
it cleans data of topology manager while disabling mst_state. However,
it doesn't clean up the proposed_vcpis of topology manager.
If proposed_vcpi is not reset, once plug in MST daisy chain monitors
later, code will fail at checking port validation while trying to
allocate payloads.

When MST capable device is plugged in again and try to allocate
payloads by calling drm_dp_update_payload_part1(), this
function will iterate over all proposed virtual channels to see if
any proposed VCPI's num_slots is greater than 0. If any proposed
VCPI's num_slots is greater than 0 and the port which the
specific virtual channel directed to is not in the topology, code then
fails at the port validation. Since there are stale VCPI allocations
from the previous topology enablement in proposed_vcpi[], code will fail
at port validation and reurn EINVAL.

[How]

Clean up the data of stale proposed_vcpi[] and reset mgr->proposed_vcpis
to NULL while disabling mst in drm_dp_mst_topology_mgr_set_mst().

Changes since v1:
*Add on more details in commit message to describe the issue which the 
patch is trying to fix

Signed-off-by: Wayne Lin 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index ae5809a1f19a..bf4f745a4edb 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3386,6 +3386,7 @@ static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8  
dp_link_count)
 int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool 
mst_state)
 {
int ret = 0;
+   int i = 0;
struct drm_dp_mst_branch *mstb = NULL;
 
mutex_lock(>lock);
@@ -3446,10 +3447,21 @@ int drm_dp_mst_topology_mgr_set_mst(struct 
drm_dp_mst_topology_mgr *mgr, bool ms
/* this can fail if the device is gone */
drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
ret = 0;
+   mutex_lock(>payload_lock);
memset(mgr->payloads, 0, mgr->max_payloads * sizeof(struct 
drm_dp_payload));
mgr->payload_mask = 0;
set_bit(0, >payload_mask);
+   for (i = 0; i < mgr->max_payloads; i++) {
+   struct drm_dp_vcpi *vcpi = mgr->proposed_vcpis[i];
+
+   if (vcpi) {
+   vcpi->vcpi = 0;
+   vcpi->num_slots = 0;
+   }
+   mgr->proposed_vcpis[i] = NULL;
+   }
mgr->vcpi_mask = 0;
+   mutex_unlock(>payload_lock);
}
 
 out_unlock:
-- 
2.17.1

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Re: Deadlock on PTEs update for HMM

[Christian König]

Hi guys,

I was wondering why the heck Felix wants to add another lock for over an 
hour before I realized that I accidentally forget to send out patch #4 
and #5.


And yes what you describe is exactly what my patch #4 is doing and patch 
#5 is then a prove of concept to use the new interface for evictions of 
shared BOs.


Regards,
Christian.

Am 05.12.19 um 02:27 schrieb Felix Kuehling:

[adding the mailing list back]

Christian sent a 3-patch series that I just reviewed and commented on. 
That removes the need to lock the page directory reservation for 
updating page tables. That solves a part of the problem, but not all 
of it.


We still need to implement that driver lock for HMM, and add a 
vm_resident flag in the vm structure that could be checked in the new 
amdgpu_vm_evictable function Christian added. That function still runs 
in atomic context (under the ttm_bo_glob.lru_lock spinlock). So we 
can't lock a mutex there. But we can use trylock and return "not 
evictable" if we fail to take the mutex.


If we take the mutex successfully, we can update the vm_resident flag 
to false and allow the eviction.


The rest should work just the way I proposed earlier.

Regards,
  Felix

On 2019-12-04 8:01 p.m., Sierra Guiza, Alejandro (Alex) wrote:

[AMD Official Use Only - Internal Distribution Only]

Hi Christian,
I wonder if you had have time to check on this implementation?
Please let me know if there's something that I could help you with

Regards,
Alex

-Original Message-
From: Christian König 
Sent: Friday, November 29, 2019 1:41 AM
To: Kuehling, Felix ; Koenig, Christian 
; Sierra Guiza, Alejandro (Alex) 


Cc: amd-gfx@lists.freedesktop.org
Subject: Re: Deadlock on PTEs update for HMM

[CAUTION: External Email]

Hi Felix,

yes that is exactly my thinking as well. Problem is that getting this 
to work was much harder than I thought.


We can't use a mutex cause TTM is calling the eviction callback in 
atomic context. A spinlock doesn't looked like a good idea either 
because we potentially need to wait for the hardware with a fixed IB 
pool.


Because of this I've started to rewrite the TTM handling to not call 
the driver in an atomic context any more, but that took me way longer 
than expected as well.


I'm currently experimenting with using a trylock driver mutex, that 
at least that should work for now until we got something better.


Regards,
Christian.

Am 28.11.19 um 21:30 schrieb Felix Kuehling:

Hi Christian,

I'm thinking about this problem, trying to come up with a solution.
The fundamental problem is that we need low-overhead access to the
page table in the MMU notifier, without much memory management or
locking.

There is one "driver lock" that we're supposed to take in the MMU
notifier as well as when we update page tables that is prescribed by
the HMM documentation (Documentation/vm/hmm.rst). I don't currently
see such a lock in amdgpu. We'll probably need to add that anyway,
with all the usual precautions about lock dependencies around MMU
notifiers. Then we could use that lock to protect page table residency
state, in addition to the reservation of the top-level page directory.

We don't want to block eviction of page tables unconditionally, so the
MMU notifier must be able to deal with the situation that page tables
are not resident at the moment. But the lock can delay page tables
from being evicted while an MMU notifier is in progress and protect us
from race conditions between MMU notifiers invalidating PTEs, and page
tables getting evicted.

amdgpu_vm_bo_invalidate could detect when a page table is being
evicted, and update a new "vm_resident" flag inside the amdgpu_vm
while holding the "HMM driver lock". If an MMU notifier is in
progress, trying to take the "HMM driver lock" will delay the eviction
long enough for any pending PTE invalidation to complete.

In the case that page tables are not resident (vm_resident flag is
false), it means the GPU is currently not accessing any memory in that
amdgpu_vm address space. So we don't need to invalidate the PTEs right
away. I think we could implement a deferred invalidation mechanism for
this case, that delays the invalidation until the next time the page
tables are made resident. amdgpu_amdkfd_gpuvm_restore_process_bos
would replay any deferred PTE invalidations after validating the page
tables but before restarting the user mode queues for the process. If
graphics ever implements page-fault-based memory management, you'd
need to do something similar in amdgpu_cs.

Once all that is in place, we should be able to update PTEs in MMU
notifiers without reserving the page tables.

If we use SDMA for updating page tables, we may need a pre-allocated
IB for use in MMU notifiers. And there is problably other details to
be worked out about exactly how we implement the PTE invalidation in
MMU notifiers and reflecting that in the state of the amdgpu_vm and
amdgpu_bo_va_mapping.

Does this idea sound reasonable to you? Can you think