[PATCH 2/2] drm/amdgpu: add invalidate semaphore limit for SRIOV in gmc10

[Changfeng.Zhu]

From: changzhu 

It may fail to load guest driver in round 2 when using invalidate
semaphore for SRIOV. So it needs to avoid using invalidate semaphore
for SRIOV.

Change-Id: I2719671cf86a1755b05c5f2ac7420a901abbe916
Signed-off-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 29 +++---
 1 file changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 381bb709f021..5c5ced29fde2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -218,6 +218,21 @@ static uint32_t gmc_v10_0_get_invalidate_req(unsigned int 
vmid,
return req;
 }
 
+/**
+ * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
+ *
+ * @adev: amdgpu_device pointer
+ * @vmhub: vmhub type
+ *
+ */
+static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
+  uint32_t vmhub)
+{
+   return ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)));
+}
+
 /*
  * GART
  * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -228,6 +243,7 @@ static uint32_t gmc_v10_0_get_invalidate_req(unsigned int 
vmid,
 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
   unsigned int vmhub, uint32_t flush_type)
 {
+   bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
struct amdgpu_vmhub *hub = >vmhub[vmhub];
u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type);
/* Use register 17 for GART */
@@ -243,8 +259,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if (use_semaphore) {
for (i = 0; i < adev->usec_timeout; i++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -277,8 +292,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
}
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1)
+   if (use_semaphore)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -369,6 +383,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 unsigned vmid, uint64_t pd_addr)
 {
+   bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, 
ring->funcs->vmhub);
struct amdgpu_vmhub *hub = >adev->vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
unsigned eng = ring->vm_inv_eng;
@@ -381,8 +396,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if (use_semaphore)
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -398,8 +412,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if (use_semaphore)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
-- 
2.17.1

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[PATCH 1/2] drm/amdgpu: add invalidate semaphore limit for SRIOV and picasso in gmc9

[Changfeng.Zhu]

From: changzhu 

It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.

Change-Id: I806f8e99ec97be84e6aed0f5c499a53b1931b490
Signed-off-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 44 +++
 1 file changed, 24 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 601667246a1c..efa55e9676be 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -412,6 +412,24 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int 
vmid,
return req;
 }
 
+/**
+ * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
+ *
+ * @adev: amdgpu_device pointer
+ * @vmhub: vmhub type
+ *
+ */
+static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
+  uint32_t vmhub)
+{
+   return ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)));
+}
+
 /*
  * GART
  * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -431,6 +449,7 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int 
vmid,
 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type)
 {
+   bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
const unsigned eng = 17;
u32 j, tmp;
struct amdgpu_vmhub *hub;
@@ -464,11 +483,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8))) {
+   if (use_semaphore) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -498,11 +513,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
}
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (use_semaphore)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -520,6 +531,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
 {
+   bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, 
ring->funcs->vmhub);
struct amdgpu_device *adev = ring->adev;
struct amdgpu_vmhub *hub = >vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
@@ -533,11 +545,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (use_semaphore)
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -553,11 +561,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (use_semaphore)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
-- 
2.17.1

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[PATCH v3] drm/amd/display: Fix AppleDongle can't be detected

[Louis Li]

[Why]
External monitor cannot be displayed consistently, if connecting
via this Apple dongle (A1621, USB Type-C to HDMI).
Experiments prove that the dongle needs 200ms at least to be ready
for communication, after it drives HPDsignal high, and DPCD cannot
be read correctly during the period, even reading it repeatedly.
In such a case, driver does not perform link training bcz of no DPCD.

[How]
When driver is run to the modified point, EDID is read correctly
and dpcd_sink_count of link is not zero. Therefore, link training
should be successfully performed. Which implies parameters should
be updated, e.g. lane count, link rate, etc. Checking parameters,
if values of those parameters are zero, link training is not
performed. So, do link-training to have detection completed.

With this patch applied, the problem cannot be reproduced.
Testing other dongles, results are PASS.
Patch(v3) is verified PASS by both AMD internal lab and customer.


Signed-off-by: Louis Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 7372dedd2f48..6188edc92d0f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -725,7 +725,9 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
 
if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
sink_caps.transaction_type == 
DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
-   reason != DETECT_REASON_HPDRX) {
+   link->verified_link_cap.lane_count == 0 &&
+   link->verified_link_cap.link_rate == 0 &&
+   link->verified_link_cap.link_spread == 0) {
/*
 * TODO debug why Dell 2413 doesn't like
 *  two link trainings
-- 
2.21.0

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RE: [PATCH] drm/amdgpu/gfx10: update gfx golden settings for navi12

[Xu, Feifei]

Reviewed-by: Feifei Xu 

-Original Message-
From: Tianci Yin  
Sent: Wednesday, December 11, 2019 2:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ; 
Yuan, Xiaojie ; Long, Gang ; Li, 
Pauline ; Yin, Tianci (Rico) 
Subject: [PATCH] drm/amdgpu/gfx10: update gfx golden settings for navi12

From: "Tianci.Yin" 

add registers: mmSPI_CONFIG_CNTL
update registers: mmDB_DEBUG4 and mmUTCL1_CTRL

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index db9b8bfb1c3c..557ebf317b5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -185,7 +185,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x, 0x2000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x, 0x0420),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0200),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0480),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0490),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x, 
0x003f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0x, 
0x03860204),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0, 
0x0500), @@ -205,12 +205,13 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0820, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
+0x00070104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0080)
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x00c0)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
--
2.17.1

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[PATCH] drm/amdgpu/gfx10: update gfx golden settings for navi12

[Tianci Yin]

From: "Tianci.Yin" 

add registers: mmSPI_CONFIG_CNTL
update registers: mmDB_DEBUG4 and mmUTCL1_CTRL

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index db9b8bfb1c3c..557ebf317b5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -185,7 +185,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x, 0x2000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x, 0x0420),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0200),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0480),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0490),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x, 
0x003f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0x, 
0x03860204),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0, 
0x0500),
@@ -205,12 +205,13 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0820, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0080)
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x00c0)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
-- 
2.17.1

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RE: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Quan, Evan]

Acked-by: Evan Quan 

> -Original Message-
> From: amd-gfx  On Behalf Of Yintian
> Tao
> Sent: Wednesday, December 11, 2019 10:51 AM
> To: Deucher, Alexander ; Feng, Kenneth
> 
> Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
> Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
> 
> Originally, due to the restriction from PSP and SMU, VF has to send message to
> hypervisor driver to handle powerplay change which is complicated and
> redundant. Currently, SMU and PSP can support VF to directly handle
> powerplay change by itself. Therefore, the old code about the handshake
> between VF and PF to handle powerplay will be removed and VF will use new
> the registers below to handshake with SMU.
> mmMP1_SMN_C2PMSG_101: register to handle SMU message
> mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
> mmMP1_SMN_C2PMSG_103: register to handle SMU response
> 
> v2: remove module parameter pp_one_vf
> v3: fix the parens
> v4: forbid vf to change smu feature
> v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
> v6: change skip condition at vega10_copy_table_to_smc
> 
> Signed-off-by: Yintian Tao 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
>  drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
>  .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
>  .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
>  .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
>  .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
>  .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
>  17 files changed, 352 insertions(+), 300 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7324a5fc5ccb..47b4f359f07c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct
> amdgpu_device *adev)
>   }
>   }
> 
> + if (amdgpu_sriov_vf(adev))
> + amdgpu_virt_init_data_exchange(adev);
> +
>   r = amdgpu_ib_pool_init(adev);
>   if (r) {
>   dev_err(adev->dev, "IB initialization failed (%d).\n", r); @@ -
> 1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
> *adev)
>   amdgpu_amdkfd_device_init(adev);
> 
>  init_failed:
> - if (amdgpu_sriov_vf(adev)) {
> - if (!r)
> - amdgpu_virt_init_data_exchange(adev);
> + if (amdgpu_sriov_vf(adev))
>   amdgpu_virt_release_full_gpu(adev, true);
> - }
> 
>   return r;
>  }
> @@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>   mutex_init(>virt.vf_errors.lock);
>   hash_init(adev->mn_hash);
>   mutex_init(>lock_reset);
> - mutex_init(>virt.dpm_mutex);
>   mutex_init(>psp.mutex);
> 
>   r = amdgpu_device_check_arguments(adev);
> @@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> 
>   amdgpu_fbdev_init(adev);
> 
> - if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
> - amdgpu_pm_virt_sysfs_init(adev);
> -
>   r = amdgpu_pm_sysfs_init(adev);
>   if (r) {
>   adev->pm_sysfs_en = false;
> @@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device
> *adev)
>   iounmap(adev->rmmio);
>   adev->rmmio = NULL;
>   amdgpu_device_doorbell_fini(adev);
> - if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
> - amdgpu_pm_virt_sysfs_fini(adev);
> 
>   amdgpu_debugfs_regs_cleanup(adev);
>   device_remove_file(adev->dev, _attr_pcie_replay_count); @@ -
> 3673,6 +3667,7 @@ static int amdgpu_device_reset_sriov(struct
> amdgpu_device *adev,
>   if (r)
>   goto error;
> 
> + amdgpu_virt_init_data_exchange(adev);
>   /* we need recover gart prior to run SMC/CP/SDMA resume */
>   amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
> 
> @@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct
> amdgpu_device *adev,
>   amdgpu_amdkfd_post_reset(adev);
> 
>  error:
> - amdgpu_virt_init_data_exchange(adev);
>   amdgpu_virt_release_full_gpu(adev, true);
>   if (!r && adev->virt.gim_feature &
> AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
>   amdgpu_inc_vram_lost(adev);
> diff --git 

RE: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

I assume the smu firmware has been changed accordingly.
Reviewed-by: Kenneth Feng 


-Original Message-
From: Yintian Tao  
Sent: Wednesday, December 11, 2019 10:51 AM
To: Deucher, Alexander ; Feng, Kenneth 

Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

Originally, due to the restriction from PSP and SMU, VF has to send message to 
hypervisor driver to handle powerplay change which is complicated and 
redundant. Currently, SMU and PSP can support VF to directly handle powerplay 
change by itself. Therefore, the old code about the handshake between VF and PF 
to handle powerplay will be removed and VF will use new the registers below to 
handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
v6: change skip condition at vega10_copy_table_to_smc

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
 .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 17 files changed, 352 insertions(+), 300 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r); @@ 
-1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count); @@ -3673,6 
+3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 

Recall: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Feng, Kenneth]

Feng, Kenneth would like to recall the message, "[PATCH] drm/amd/powerplay: 
enable pp one vf mode for vega10".
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RE: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]



-Original Message-
From: Yintian Tao  
Sent: Wednesday, December 11, 2019 10:51 AM
To: Deucher, Alexander ; Feng, Kenneth 

Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

Originally, due to the restriction from PSP and SMU, VF has to send message to 
hypervisor driver to handle powerplay change which is complicated and 
redundant. Currently, SMU and PSP can support VF to directly handle powerplay 
change by itself. Therefore, the old code about the handshake between VF and PF 
to handle powerplay will be removed and VF will use new the registers below to 
handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
v6: change skip condition at vega10_copy_table_to_smc

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
 .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 17 files changed, 352 insertions(+), 300 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r); @@ 
-1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count); @@ -3673,6 
+3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- 

Re: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

[Yin, Tianci (Rico)]

[AMD Official Use Only - Internal Distribution Only]

Thanks Feifei!

From: Xu, Feifei 
Sent: Wednesday, December 11, 2019 11:29
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org 

Cc: Zhang, Hawking ; Yuan, Xiaojie 
; Long, Gang ; Li, Pauline 
; Yin, Tianci (Rico) 
Subject: RE: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings



Series is Reviewed-by: Feifei Xu 

-Original Message-
From: Tianci Yin 
Sent: Wednesday, December 11, 2019 11:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ; 
Yuan, Xiaojie ; Long, Gang ; Li, 
Pauline ; Yin, Tianci (Rico) 
Subject: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

From: "Tianci.Yin" 

add registers: mmSPI_CONFIG_CNTL

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ed630d37c32c..f3324fa4e194 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -114,6 +114,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1[] =
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 
0x0444),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070104),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0100, 0x0130),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
--
2.17.1

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RE: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

[Xu, Feifei]

Series is Reviewed-by: Feifei Xu 

-Original Message-
From: Tianci Yin  
Sent: Wednesday, December 11, 2019 11:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ; 
Yuan, Xiaojie ; Long, Gang ; Li, 
Pauline ; Yin, Tianci (Rico) 
Subject: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

From: "Tianci.Yin" 

add registers: mmSPI_CONFIG_CNTL

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ed630d37c32c..f3324fa4e194 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -114,6 +114,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 
0x0444),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0100, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
-- 
2.17.1

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[PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

[Tianci Yin]

From: "Tianci.Yin" 

add registers: mmSPI_CONFIG_CNTL

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ed630d37c32c..f3324fa4e194 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -114,6 +114,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 
0x0444),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0100, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
-- 
2.17.1

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[PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14

[Tianci Yin]

From: "Tianci.Yin" 

add registers: mmSPI_CONFIG_CNTL

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f3324fa4e194..db9b8bfb1c3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -160,6 +160,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 
0x0444),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070105),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
-- 
2.17.1

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[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Yintian Tao]

Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
v6: change skip condition at vega10_copy_table_to_smc

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
 .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 17 files changed, 352 insertions(+), 300 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3673,6 +3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, 
false) * 10;

Re: [PATCH] drm/amdgpu: wait for all rings to drain before runtime suspending

[zhoucm1]

On 2019/12/11 上午6:08, Alex Deucher wrote:

Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend.  Doesn't fix any known issue.

We already do this via the fence driver suspend function, but we
just force completion rather than bailing.  This bails on runtime
suspend so we can try again later once the fences are signaled to
avoid missing any outstanding work.


The idea sounds OK to me, but if you want to drain the rings, you should 
make sure no more submission, right?


So you should park all schedulers before waiting for all outstanding 
fences completed.


-David



Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 2f367146c72c..81322b0a8acf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1214,13 +1214,23 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
struct pci_dev *pdev = to_pci_dev(dev);
struct drm_device *drm_dev = pci_get_drvdata(pdev);
struct amdgpu_device *adev = drm_dev->dev_private;
-   int ret;
+   int ret, i;
  
  	if (!adev->runpm) {

pm_runtime_forbid(dev);
return -EBUSY;
}
  
+	/* wait for all rings to drain before suspending */

+   for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+   struct amdgpu_ring *ring = adev->rings[i];
+   if (ring && ring->sched.ready) {
+   ret = amdgpu_fence_wait_empty(ring);
+   if (ret)
+   return -EBUSY;
+   }
+   }
+
if (amdgpu_device_supports_boco(drm_dev))
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
drm_kms_helper_poll_disable(drm_dev);

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RE: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Quan, Evan]

> + /* under pp_one_vf mode, vbios or hypervisor driver
> +  * has already copy table to smc so here only skip it
> +  */
> + if (!hwmgr->not_vf && !hwmgr->pp_one_vf)
> + return 0;
This code seems inconsistent with the comment. Maybe using "if 
(hwmgr->pp_one_vf)" is enough.

Other than this, the patch seem fine with me. With above addressed, the patch 
is acked-by: Evan Quan 

> -Original Message-
> From: amd-gfx  On Behalf Of Yintian
> Tao
> Sent: Wednesday, December 11, 2019 2:50 AM
> To: Deucher, Alexander ; Feng, Kenneth
> 
> Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
> Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
> 
> Originally, due to the restriction from PSP and SMU, VF has
> to send message to hypervisor driver to handle powerplay
> change which is complicated and redundant. Currently, SMU
> and PSP can support VF to directly handle powerplay
> change by itself. Therefore, the old code about the handshake
> between VF and PF to handle powerplay will be removed and VF
> will use new the registers below to handshake with SMU.
> mmMP1_SMN_C2PMSG_101: register to handle SMU message
> mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
> mmMP1_SMN_C2PMSG_103: register to handle SMU response
> 
> v2: remove module parameter pp_one_vf
> v3: fix the parens
> v4: forbid vf to change smu feature
> v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
> 
> Signed-off-by: Yintian Tao 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
>  drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
>  .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
>  .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
>  .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
>  .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
>  .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
>  17 files changed, 352 insertions(+), 300 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7324a5fc5ccb..47b4f359f07c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct
> amdgpu_device *adev)
>   }
>   }
> 
> + if (amdgpu_sriov_vf(adev))
> + amdgpu_virt_init_data_exchange(adev);
> +
>   r = amdgpu_ib_pool_init(adev);
>   if (r) {
>   dev_err(adev->dev, "IB initialization failed (%d).\n", r);
> @@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct
> amdgpu_device *adev)
>   amdgpu_amdkfd_device_init(adev);
> 
>  init_failed:
> - if (amdgpu_sriov_vf(adev)) {
> - if (!r)
> - amdgpu_virt_init_data_exchange(adev);
> + if (amdgpu_sriov_vf(adev))
>   amdgpu_virt_release_full_gpu(adev, true);
> - }
> 
>   return r;
>  }
> @@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>   mutex_init(>virt.vf_errors.lock);
>   hash_init(adev->mn_hash);
>   mutex_init(>lock_reset);
> - mutex_init(>virt.dpm_mutex);
>   mutex_init(>psp.mutex);
> 
>   r = amdgpu_device_check_arguments(adev);
> @@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> 
>   amdgpu_fbdev_init(adev);
> 
> - if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
> - amdgpu_pm_virt_sysfs_init(adev);
> -
>   r = amdgpu_pm_sysfs_init(adev);
>   if (r) {
>   adev->pm_sysfs_en = false;
> @@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device
> *adev)
>   iounmap(adev->rmmio);
>   adev->rmmio = NULL;
>   amdgpu_device_doorbell_fini(adev);
> - if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
> - amdgpu_pm_virt_sysfs_fini(adev);
> 
>   amdgpu_debugfs_regs_cleanup(adev);
>   device_remove_file(adev->dev, _attr_pcie_replay_count);
> @@ -3673,6 +3667,7 @@ static int amdgpu_device_reset_sriov(struct
> amdgpu_device *adev,
>   if (r)
>   goto error;
> 
> + amdgpu_virt_init_data_exchange(adev);
>   /* we need recover gart prior to run SMC/CP/SDMA resume */
>   amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
> 
> @@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct
> amdgpu_device 

Re: [PATCH] drm/amd/display: include linux/slab.h where needed

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Dec 10, 2019 at 2:59 PM Arnd Bergmann  wrote:
>
> Calling kzalloc() and related functions requires the
> linux/slab.h header to be included:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 
> 'dcn21_ipp_create':
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error: 
> implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? 
> [-Werror=implicit-function-declaration]
>kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
>
> A lot of other headers also miss a direct include in this file,
> but this is the only one that causes a problem for now.
>
> Signed-off-by: Arnd Bergmann 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index 906c84e6b49b..af57885bbff2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -23,6 +23,8 @@
>   *
>   */
>
> +#include 
> +
>  #include "dm_services.h"
>  #include "dc.h"
>
> --
> 2.20.0
>
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[PATCH] drm/amdgpu: wait for all rings to drain before runtime suspending

[Alex Deucher]

Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend.  Doesn't fix any known issue.

We already do this via the fence driver suspend function, but we
just force completion rather than bailing.  This bails on runtime
suspend so we can try again later once the fences are signaled to
avoid missing any outstanding work.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 2f367146c72c..81322b0a8acf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1214,13 +1214,23 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
struct pci_dev *pdev = to_pci_dev(dev);
struct drm_device *drm_dev = pci_get_drvdata(pdev);
struct amdgpu_device *adev = drm_dev->dev_private;
-   int ret;
+   int ret, i;
 
if (!adev->runpm) {
pm_runtime_forbid(dev);
return -EBUSY;
}
 
+   /* wait for all rings to drain before suspending */
+   for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+   struct amdgpu_ring *ring = adev->rings[i];
+   if (ring && ring->sched.ready) {
+   ret = amdgpu_fence_wait_empty(ring);
+   if (ret)
+   return -EBUSY;
+   }
+   }
+
if (amdgpu_device_supports_boco(drm_dev))
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
drm_kms_helper_poll_disable(drm_dev);
-- 
2.23.0

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[PATCH AUTOSEL 4.14 090/130] drm/amdgpu: fix potential double drop fence reference

[Sasha Levin]

From: Pan Bian 

[ Upstream commit 946ab8db6953535a3a88c957db8328beacdfed9d ]

The object fence is not set to NULL after its reference is dropped. As a
result, its reference may be dropped again if error occurs after that,
which may lead to a use after free bug. To avoid the issue, fence is
explicitly set to NULL after dropping its reference.

Acked-by: Christian König 
Signed-off-by: Pan Bian 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
index ed8c3739015be..b35b0741fd97e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
@@ -125,6 +125,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
}
 
dma_fence_put(fence);
+   fence = NULL;
 
r = amdgpu_bo_kmap(vram_obj, _map);
if (r) {
@@ -170,6 +171,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
}
 
dma_fence_put(fence);
+   fence = NULL;
 
r = amdgpu_bo_kmap(gtt_obj[i], _map);
if (r) {
-- 
2.20.1

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Re: [PATCH] drm/amd/display: fix undefined struct member reference

[Arnd Bergmann]

On Tue, Dec 10, 2019 at 9:56 PM Kazlauskas, Nicholas
 wrote:
> On 2019-12-10 3:54 p.m., Liu, Zhan wrote:

> >>
> >> Fixes: c3d03c5a196f ("drm/amd/display: Include num_vmid and num_dsc
> >> within NV14's resource caps")
> >> Signed-off-by: Arnd Bergmann 
> >
> > Thank you for catching that On my side I kept that flag enabled all the 
> > time, so I didn't realize there was a warning hidden here.
> >
> > Reviewed-by: Zhan Liu 
>
> What tree is this reported on?

This is plain linux-5.5-rc1.

> We dropped this flag whenever building DCN. Sounds like we're missing a
> patch if you're getting this.
>
> So this is a NAK from me for going into amd-staging-drm-next at least.

Fair enough, please revert c3d03c5a196f ("drm/amd/display: Include
num_vmid and num_dsc within NV14's resource caps") for 5.5-rc2 then.

  Arnd
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RE: [PATCH] drm/amd/display: fix undefined struct member reference

[Deucher, Alexander]

> -Original Message-
> From: Kazlauskas, Nicholas 
> Sent: Tuesday, December 10, 2019 3:56 PM
> To: Liu, Zhan ; Arnd Bergmann ;
> Wentland, Harry ; Li, Sun peng (Leo)
> ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; David Airlie ; Daniel Vetter
> 
> Cc: Liu, Charlene ; Yang, Eric
> ; linux-ker...@vger.kernel.org; amd-
> g...@lists.freedesktop.org; Cornij, Nikola ;
> Laktyushkin, Dmytro ; dri-
> de...@lists.freedesktop.org; Lei, Jun ; Lakha,
> Bhawanpreet 
> Subject: Re: [PATCH] drm/amd/display: fix undefined struct member
> reference
> 
> On 2019-12-10 3:54 p.m., Liu, Zhan wrote:
> >
> >
> >> -Original Message-
> >> From: Arnd Bergmann 
> >> Sent: 2019/December/10, Tuesday 3:31 PM
> >> To: Wentland, Harry ; Li, Sun peng (Leo)
> >> ; Deucher, Alexander
> ;
> >> Koenig, Christian ; Zhou, David(ChunMing)
> >> ; David Airlie ; Daniel Vetter
> >> ; Liu, Zhan 
> >> Cc: Arnd Bergmann ; Laktyushkin, Dmytro
> >> ; Lakha, Bhawanpreet
> >> ; Lei, Jun ; Liu,
> >> Charlene ; Yang, Eric ;
> >> Cornij, Nikola ;
> >> amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> >> linux-ker...@vger.kernel.org
> >> Subject: [PATCH] drm/amd/display: fix undefined struct member
> >> reference
> >>
> >> An initialization was added for two optional struct members.  One of
> >> these is always present in the dcn20_resource file, but the other one
> >> depends on CONFIG_DRM_AMD_DC_DSC_SUPPORT and causes a build
> failure
> >> if that is
> >> missing:
> >>
> >>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:926:1
> >> 4: error: excess elements in struct initializer [-Werror]
> >> .num_dsc = 5,
> >>
> >> Add another #ifdef around the assignment.
> >>
> >> Fixes: c3d03c5a196f ("drm/amd/display: Include num_vmid and num_dsc
> >> within NV14's resource caps")
> >> Signed-off-by: Arnd Bergmann 
> >
> > Thank you for catching that  On my side I kept that flag enabled all the
> time, so I didn't realize there was a warning hidden here.
> >
> > Reviewed-by: Zhan Liu 
> 
> What tree is this reported on?
> 
> We dropped this flag whenever building DCN. Sounds like we're missing a
> patch if you're getting this.
> 
> So this is a NAK from me for going into amd-staging-drm-next at least.
> 

Those patches are not upstream yet.  They are queued for 5.6.  So we need this 
patch for 5.5.  I'll apply it.

Alex

> Nicholas Kazlauskas
> 
> >
> >> ---
> >>   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> >> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> >> index faab89d1e694..fdf93e6edf43 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> >> @@ -923,7 +923,9 @@ static const struct resource_caps res_cap_nv14 = {
> >>.num_dwb = 1,
> >>.num_ddc = 5,
> >>.num_vmid = 16,
> >> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> >>.num_dsc = 5,
> >> +#endif
> >>   };
> >>
> >>   static const struct dc_debug_options debug_defaults_drv = {
> >> --
> >> 2.20.0
> >
> > ___
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> >

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[PATCH] drm/amd/display: fix undefined struct member reference

[Arnd Bergmann]

An initialization was added for two optional struct members.  One of
these is always present in the dcn20_resource file, but the other one
depends on CONFIG_DRM_AMD_DC_DSC_SUPPORT and causes a build failure if
that is missing:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:926:14: error: 
excess elements in struct initializer [-Werror]
   .num_dsc = 5,

Add another #ifdef around the assignment.

Fixes: c3d03c5a196f ("drm/amd/display: Include num_vmid and num_dsc within 
NV14's resource caps")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index faab89d1e694..fdf93e6edf43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -923,7 +923,9 @@ static const struct resource_caps res_cap_nv14 = {
.num_dwb = 1,
.num_ddc = 5,
.num_vmid = 16,
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
.num_dsc = 5,
+#endif
 };
 
 static const struct dc_debug_options debug_defaults_drv = {
-- 
2.20.0

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[PATCH] drm/amd/display: include linux/slab.h where needed

[Arnd Bergmann]

Calling kzalloc() and related functions requires the
linux/slab.h header to be included:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 
'dcn21_ipp_create':
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error: 
implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? 
[-Werror=implicit-function-declaration]
   kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);

A lot of other headers also miss a direct include in this file,
but this is the only one that causes a problem for now.

Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 906c84e6b49b..af57885bbff2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -23,6 +23,8 @@
  *
  */
 
+#include 
+
 #include "dm_services.h"
 #include "dc.h"
 
-- 
2.20.0

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Re: [PATCH] drm/amd/display: include linux/slab.h where needed

[Arnd Bergmann]

On Tue, Dec 10, 2019 at 9:30 PM Kazlauskas, Nicholas
 wrote:
>
> On 2019-12-10 2:59 p.m., Arnd Bergmann wrote:
> > Calling kzalloc() and related functions requires the
> > linux/slab.h header to be included:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In 
> > function 'dcn21_ipp_create':
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: 
> > error: implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? 
> > [-Werror=implicit-function-declaration]
> > kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
> >
> > A lot of other headers also miss a direct include in this file,
> > but this is the only one that causes a problem for now.
> >
> > Signed-off-by: Arnd Bergmann 
>
> What version of the kernel are you building?

This is v5.5-rc1, plus some local patches.

> We have:
>
> #include 
>
> in os_types.h which gets included as part of this file:
>
> #include  -> #include  -> #include 

I don't see linux/slab.h in os_types.h. I now see that commit
4fc4dca8320e ("drm/amd: drop use of drmp.h in os_types.h")
was merged into linux-5.3, which may have caused this.

I also don't see anything in os_types.h that needs linux/slab.h.

Arnd
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[PATCH AUTOSEL 4.19 175/177] drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2

[Sasha Levin]

From: Sam Bobroff 

[ Upstream commit 3d0e3ce52ce3eb4b9de3caf9c38dbb5a4d3e13c3 ]

The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address.  This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8 guest).

Instead, use the DMA address of the dummy page because it will always
be safe.

Fixes: 27ae10641e9c ("drm/amdgpu: add interupt handler implementation for si 
v3")
Signed-off-by: Sam Bobroff 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c 
b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 60dad63098a2a..e40a3fbc3e760 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -62,7 +62,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
u64 wptr_off;
 
si_ih_disable_interrupts(adev);
-   WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
+   /* set dummy read address to dummy page address */
+   WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
interrupt_cntl = RREG32(INTERRUPT_CNTL);
interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
-- 
2.20.1

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[PATCH AUTOSEL 4.19 119/177] drm/amdgpu: fix potential double drop fence reference

[Sasha Levin]

From: Pan Bian 

[ Upstream commit 946ab8db6953535a3a88c957db8328beacdfed9d ]

The object fence is not set to NULL after its reference is dropped. As a
result, its reference may be dropped again if error occurs after that,
which may lead to a use after free bug. To avoid the issue, fence is
explicitly set to NULL after dropping its reference.

Acked-by: Christian König 
Signed-off-by: Pan Bian 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
index 8904e62dca7ae..41d3142ef3cf0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
@@ -138,6 +138,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
}
 
dma_fence_put(fence);
+   fence = NULL;
 
r = amdgpu_bo_kmap(vram_obj, _map);
if (r) {
@@ -183,6 +184,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
}
 
dma_fence_put(fence);
+   fence = NULL;
 
r = amdgpu_bo_kmap(gtt_obj[i], _map);
if (r) {
-- 
2.20.1

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[PATCH AUTOSEL 4.19 118/177] drm/amdgpu: disallow direct upload save restore list from gfx driver

[Sasha Levin]

From: Hawking Zhang 

[ Upstream commit 58f46d4b65021083ef4b4d49c6e2c58e5783f626 ]

Direct uploading save/restore list via mmio register writes breaks the security
policy. Instead, the driver should pass s list to psp.

For all the ASICs that use rlc v2_1 headers, the driver actually upload s list
twice, in non-psp ucode front door loading phase and gfx pg initialization 
phase.
The latter is not allowed.

VG12 is the only exception where the driver still keeps legacy approach for S
list uploading. In theory, this can be elimnated if we have valid srcntl ucode
for VG12.

Signed-off-by: Hawking Zhang 
Reviewed-by: Candice Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7824116498169..28794b1b15c10 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2187,7 +2187,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 * And it's needed by gfxoff feature.
 */
if (adev->gfx.rlc.is_rlc_v2_1) {
-   gfx_v9_1_init_rlc_save_restore_list(adev);
+   if (adev->asic_type == CHIP_VEGA12)
+   gfx_v9_1_init_rlc_save_restore_list(adev);
gfx_v9_0_enable_save_restore_machine(adev);
}
 
-- 
2.20.1

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[PATCH AUTOSEL 4.19 049/177] drm/amd/display: Fix dongle_caps containing stale information.

[Sasha Levin]

From: David Galiffi 

[ Upstream commit dd998291dbe92106d8c4a7581c409b356928d711 ]

[WHY]

During detection:
function: get_active_converter_info populates link->dpcd_caps.dongle_caps
only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is
DOWN_STREAM_DETAILED_HDMI or DOWN_STREAM_DETAILED_DP_PLUS_PLUS.
Otherwise, it is not cleared, and stale information remains.

During mode validation:
function: dp_active_dongle_validate_timing reads
link->dpcd_caps.dongle_caps->dongle_type to determine the maximum
pixel clock to support. This information is now stale and no longer
valid.

[HOW]
dp_active_dongle_validate_timing should be using
link->dpcd_caps->dongle_type instead.

Signed-off-by: David Galiffi 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c| 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 23a7ef97afdd2..c6f7c1344a9b8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1950,7 +1950,7 @@ static bool dp_active_dongle_validate_timing(
break;
}
 
-   if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
+   if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
dongle_caps->extendedCapValid == false)
return true;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 05840f5bddd59..122249da03ab7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2172,6 +2172,7 @@ static void get_active_converter_info(
uint8_t data, struct dc_link *link)
 {
union dp_downstream_port_present ds_port = { .byte = data };
+   memset(>dpcd_caps.dongle_caps, 0, 
sizeof(link->dpcd_caps.dongle_caps));
 
/* decode converter info*/
if (!ds_port.fields.PORT_PRESENT) {
-- 
2.20.1

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[PATCH AUTOSEL 4.19 025/177] drm/amdkfd: fix a potential NULL pointer dereference (v2)

[Sasha Levin]

From: Allen Pais 

[ Upstream commit 81de29d842ccb776c0f77aa3e2b11b07fff0c0e2 ]

alloc_workqueue is not checked for errors and as a result,
a potential NULL dereference could occur.

v2 (Felix Kuehling):
* Fix compile error (kfifo_free instead of fifo_free)
* Return proper error code

Signed-off-by: Allen Pais 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index c56ac47cd3189..bc47f6a444564 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -62,6 +62,11 @@ int kfd_interrupt_init(struct kfd_dev *kfd)
}
 
kfd->ih_wq = alloc_workqueue("KFD IH", WQ_HIGHPRI, 1);
+   if (unlikely(!kfd->ih_wq)) {
+   kfifo_free(>ih_fifo);
+   dev_err(kfd_chardev(), "Failed to allocate KFD IH workqueue\n");
+   return -ENOMEM;
+   }
spin_lock_init(>interrupt_lock);
 
INIT_WORK(>interrupt_work, interrupt_wq);
-- 
2.20.1

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[PATCH AUTOSEL 4.19 005/177] drm/amdgpu: grab the id mgr lock while accessing passid_mapping

[Sasha Levin]

From: Christian König 

[ Upstream commit 6817bf283b2b851095825ec7f0e9f10398e09125 ]

Need to make sure that we actually dropping the right fence.
Could be done with RCU as well, but to complicated for a fix.

Signed-off-by: Christian König 
Reviewed-by: Chunming Zhou 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 49fe5084c53dd..69fb90d9c4855 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -700,10 +700,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job, bool need_
id->oa_base != job->oa_base ||
id->oa_size != job->oa_size);
bool vm_flush_needed = job->vm_needs_flush;
-   bool pasid_mapping_needed = id->pasid != job->pasid ||
-   !id->pasid_mapping ||
-   !dma_fence_is_signaled(id->pasid_mapping);
struct dma_fence *fence = NULL;
+   bool pasid_mapping_needed;
unsigned patch_offset = 0;
int r;
 
@@ -713,6 +711,12 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job, bool need_
pasid_mapping_needed = true;
}
 
+   mutex_lock(_mgr->lock);
+   if (id->pasid != job->pasid || !id->pasid_mapping ||
+   !dma_fence_is_signaled(id->pasid_mapping))
+   pasid_mapping_needed = true;
+   mutex_unlock(_mgr->lock);
+
gds_switch_needed &= !!ring->funcs->emit_gds_switch;
vm_flush_needed &= !!ring->funcs->emit_vm_flush  &&
job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
@@ -752,9 +756,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job, bool need_
}
 
if (pasid_mapping_needed) {
+   mutex_lock(_mgr->lock);
id->pasid = job->pasid;
dma_fence_put(id->pasid_mapping);
id->pasid_mapping = dma_fence_get(fence);
+   mutex_unlock(_mgr->lock);
}
dma_fence_put(fence);
 
-- 
2.20.1

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[PATCH AUTOSEL 5.3 010/292] drm/amdgpu/sriov: add ring_stop before ring_create in psp v11 code

[Sasha Levin]

From: Jack Zhang 

[ Upstream commit 51c0f58e9f6af3a387d14608033e6796a7ad90ee ]

psp  v11 code missed ring stop in ring create function(VMR)
while psp v3.1 code had the code. This will cause VM destroy1
fail and psp ring create fail.

For SIOV-VF, ring_stop should not be deleted in ring_create
function.

Signed-off-by: Jack Zhang 
Reviewed-by: Feifei Xu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 61 ++
 1 file changed, 34 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 41b72588adcf5..68774524e58bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -373,6 +373,34 @@ static bool psp_v11_0_support_vmr_ring(struct psp_context 
*psp)
return false;
 }
 
+static int psp_v11_0_ring_stop(struct psp_context *psp,
+ enum psp_ring_type ring_type)
+{
+   int ret = 0;
+   struct amdgpu_device *adev = psp->adev;
+
+   /* Write the ring destroy command*/
+   if (psp_v11_0_support_vmr_ring(psp))
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
+GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
+   else
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
+GFX_CTRL_CMD_ID_DESTROY_RINGS);
+
+   /* there might be handshake issue with hardware which needs delay */
+   mdelay(20);
+
+   /* Wait for response flag (bit 31) */
+   if (psp_v11_0_support_vmr_ring(psp))
+   ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_101),
+  0x8000, 0x8000, false);
+   else
+   ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_64),
+  0x8000, 0x8000, false);
+
+   return ret;
+}
+
 static int psp_v11_0_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type)
 {
@@ -382,6 +410,12 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
struct amdgpu_device *adev = psp->adev;
 
if (psp_v11_0_support_vmr_ring(psp)) {
+   ret = psp_v11_0_ring_stop(psp, ring_type);
+   if (ret) {
+   DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
+   return ret;
+   }
+
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
@@ -426,33 +460,6 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
return ret;
 }
 
-static int psp_v11_0_ring_stop(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
-   int ret = 0;
-   struct amdgpu_device *adev = psp->adev;
-
-   /* Write the ring destroy command*/
-   if (psp_v11_0_support_vmr_ring(psp))
-   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
-GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
-   else
-   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
-GFX_CTRL_CMD_ID_DESTROY_RINGS);
-
-   /* there might be handshake issue with hardware which needs delay */
-   mdelay(20);
-
-   /* Wait for response flag (bit 31) */
-   if (psp_v11_0_support_vmr_ring(psp))
-   ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_101),
-  0x8000, 0x8000, false);
-   else
-   ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_64),
-  0x8000, 0x8000, false);
-
-   return ret;
-}
 
 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 enum psp_ring_type ring_type)
-- 
2.20.1

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[PATCH AUTOSEL 5.3 011/292] drm/amdgpu: grab the id mgr lock while accessing passid_mapping

[Sasha Levin]

From: Christian König 

[ Upstream commit 6817bf283b2b851095825ec7f0e9f10398e09125 ]

Need to make sure that we actually dropping the right fence.
Could be done with RCU as well, but to complicated for a fix.

Signed-off-by: Christian König 
Reviewed-by: Chunming Zhou 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 24c3c05e2fb7d..4a7b2ffd3bfe3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1036,10 +1036,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job, bool need_
id->oa_base != job->oa_base ||
id->oa_size != job->oa_size);
bool vm_flush_needed = job->vm_needs_flush;
-   bool pasid_mapping_needed = id->pasid != job->pasid ||
-   !id->pasid_mapping ||
-   !dma_fence_is_signaled(id->pasid_mapping);
struct dma_fence *fence = NULL;
+   bool pasid_mapping_needed;
unsigned patch_offset = 0;
int r;
 
@@ -1049,6 +1047,12 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job, bool need_
pasid_mapping_needed = true;
}
 
+   mutex_lock(_mgr->lock);
+   if (id->pasid != job->pasid || !id->pasid_mapping ||
+   !dma_fence_is_signaled(id->pasid_mapping))
+   pasid_mapping_needed = true;
+   mutex_unlock(_mgr->lock);
+
gds_switch_needed &= !!ring->funcs->emit_gds_switch;
vm_flush_needed &= !!ring->funcs->emit_vm_flush  &&
job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
@@ -1088,9 +1092,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job, bool need_
}
 
if (pasid_mapping_needed) {
+   mutex_lock(_mgr->lock);
id->pasid = job->pasid;
dma_fence_put(id->pasid_mapping);
id->pasid_mapping = dma_fence_get(fence);
+   mutex_unlock(_mgr->lock);
}
dma_fence_put(fence);
 
-- 
2.20.1

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[PATCH AUTOSEL 5.3 013/292] drm/amd/display: Handle virtual signal type in disable_link()

[Sasha Levin]

From: Martin Tsai 

[ Upstream commit 616f5b65f1c02d3d6ae370644670d14c57de2fd8 ]

[Why]
The new implementation changed the behavior to allow process setMode
to DAL when DAL returns empty mode query for unplugged display.
This will trigger additional disable_link().
When unplug HDMI from MST dock, driver will update stream->signal to
"Virtual". disable_link() will call disable_output() if the signal type
is not DP and induce other displays on MST dock show black screen.

[How]
Don't need to process disable_output() if the signal type is virtual.

Signed-off-by: Martin Tsai 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 355b4ba127966..90217cf83ce17 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2157,8 +2157,10 @@ static void disable_link(struct dc_link *link, enum 
signal_type signal)
dp_set_fec_ready(link, false);
}
 #endif
-   } else
-   link->link_enc->funcs->disable_output(link->link_enc, signal);
+   } else {
+   if (signal != SIGNAL_TYPE_VIRTUAL)
+   link->link_enc->funcs->disable_output(link->link_enc, 
signal);
+   }
 
if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
/* MST disable link only when no stream use the link */
-- 
2.20.1

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[PATCH AUTOSEL 5.3 006/292] drm/amd/display: verify stream link before link test

[Sasha Levin]

From: Jing Zhou 

[ Upstream commit b131932215c993ea5adf8192d1de2e8d6b23048d ]

[Why]
DP1.2 LL CTS test failure.

[How]
The failure is caused by not verify stream link is equal
to link, only check stream and link is not null.

Signed-off-by: Jing Zhou 
Reviewed-by: Wenjing Liu 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index a9135764e5806..767de9d6b07a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -312,7 +312,8 @@ void dp_retrain_link_dp_test(struct dc_link *link,
if (pipes[i].stream != NULL &&
!pipes[i].top_pipe &&
pipes[i].stream->link != NULL &&
-   pipes[i].stream_res.stream_enc != NULL) {
+   pipes[i].stream_res.stream_enc != NULL &&
+   pipes[i].stream->link == link) {
udelay(100);
 
pipes[i].stream_res.stream_enc->funcs->dp_blank(
-- 
2.20.1

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[PATCH AUTOSEL 5.4 162/350] drm/amd/display: correctly populate dpp refclk in fpga

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 952f6c4b5d72d40f93f3deb61239290b357d434e ]

[Why]
In diags environment we are not programming the DPP DTO
correctly.

[How]
Populate the dpp refclk in dccg so it can be used to correctly
program DPP DTO.

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 3e8ac303bd526..23ec283eb07b6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -320,6 +320,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
struct dc_state *context,
bool safe_to_lower)
 {
+   struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
+
struct dc_clocks *new_clocks = >bw_ctx.bw.dcn.clk;
/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off 
of it */
int fclk_adj = new_clocks->fclk_khz > 120 ? new_clocks->fclk_khz : 
120;
@@ -357,14 +359,18 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
}
 
-   /* Both fclk and dppclk ref are run on the same scemi clock so we
-* need to keep the same value for both
+   /* Both fclk and ref_dppclk run on the same scemi clock.
+* So take the higher value since the DPP DTO is typically programmed
+* such that max dppclk is 1:1 with ref_dppclk.
 */
if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
 
+   // Both fclk and ref_dppclk run on the same scemi clock.
+   clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
+
dm_set_dcn_clocks(clk_mgr->ctx, _mgr->clks);
 }
 
-- 
2.20.1

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[PATCH AUTOSEL 5.4 053/350] drm/amdkfd: fix a potential NULL pointer dereference (v2)

[Sasha Levin]

From: Allen Pais 

[ Upstream commit 81de29d842ccb776c0f77aa3e2b11b07fff0c0e2 ]

alloc_workqueue is not checked for errors and as a result,
a potential NULL dereference could occur.

v2 (Felix Kuehling):
* Fix compile error (kfifo_free instead of fifo_free)
* Return proper error code

Signed-off-by: Allen Pais 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index c56ac47cd3189..bc47f6a444564 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -62,6 +62,11 @@ int kfd_interrupt_init(struct kfd_dev *kfd)
}
 
kfd->ih_wq = alloc_workqueue("KFD IH", WQ_HIGHPRI, 1);
+   if (unlikely(!kfd->ih_wq)) {
+   kfifo_free(>ih_fifo);
+   dev_err(kfd_chardev(), "Failed to allocate KFD IH workqueue\n");
+   return -ENOMEM;
+   }
spin_lock_init(>interrupt_lock);
 
INIT_WORK(>interrupt_work, interrupt_wq);
-- 
2.20.1

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[PATCH AUTOSEL 5.4 055/350] drm/amd/powerplay: A workaround to GPU RESET on APU

[Sasha Levin]

From: chen gong 

[ Upstream commit 068ad870bbd8f4f2c5b2fd4977a4f3330c9988f4 ]

Changes to function "smu_suspend" in amdgpu_smu.c is a workaround.

We should get real information about if baco is enabled or not, while we
always consider APU SMU feature as enabled in current code.

I know APU do not support baco mode for GPU reset, so I use
"adev->flags" to skip function "smu_feature_is_enabled".

Signed-off-by: chen gong 
Reviewed-by: Aaron Liu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4acf139ea0140..58c091ab67b26 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1344,7 +1344,10 @@ static int smu_suspend(void *handle)
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = >smu;
-   bool baco_feature_is_enabled = smu_feature_is_enabled(smu, 
SMU_FEATURE_BACO_BIT);
+   bool baco_feature_is_enabled = false;
+
+   if(!(adev->flags & AMD_IS_APU))
+   baco_feature_is_enabled = smu_feature_is_enabled(smu, 
SMU_FEATURE_BACO_BIT);
 
ret = smu_system_features_control(smu, false);
if (ret)
-- 
2.20.1

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[PATCH AUTOSEL 5.4 096/350] drm/amd/display: wait for set pipe mcp command completion

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 15caeabc5787c15babad7ee444afe9c26df1c8b3 ]

[Why]
When the driver sends a pipe set command to the DMCU FW, it does not wait
for the command to complete. This can lead to unpredictable behavior if,
for example, the driver were to request a pipe disable to the FW via MCP,
then power down some hardware before the firmware has completed processing
the command.

[How]
Wait for the DMCU FW to finish processing set pipe commands

Signed-off-by: Josip Pavic 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index 58bd131d5b484..7700a855d77ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -77,6 +77,9 @@ static bool dce_abm_set_pipe(struct abm *abm, uint32_t 
controller_id)
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 
+   REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+   1, 8);
+
return true;
 }
 
-- 
2.20.1

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[PATCH AUTOSEL 5.4 098/350] drm/amd/display: add new active dongle to existent w/a

[Sasha Levin]

From: Vitaly Prosyak 

[ Upstream commit 566b4252fe9da9582dde008c5e9c3eb7c136e348 ]

[Why & How]
Dongle 0x00E04C power down all internal circuits including
AUX communication preventing reading DPCD table.
Encoder will skip DP RX power down on disable output
to keep receiver powered all the time.

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
Acked-by: Vitaly Prosyak 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 1 +
 drivers/gpu/drm/amd/display/include/ddc_service_types.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index f5742719b5d9b..9e261dbf2e493 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2691,6 +2691,7 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, 
uint8_t *dpcd_data,
 * keep receiver powered all the time.*/
case DP_BRANCH_DEVICE_ID_0010FA:
case DP_BRANCH_DEVICE_ID_0080E1:
+   case DP_BRANCH_DEVICE_ID_00E04C:
link->wa_flags.dp_keep_receiver_powered = true;
break;
 
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h 
b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 18961707db237..9ad49da50a17d 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -31,6 +31,8 @@
 #define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
 #define DP_BRANCH_DEVICE_ID_1A 0x1A
 #define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
+#define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
+#define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C
 
 enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
-- 
2.20.1

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[PATCH AUTOSEL 5.4 060/350] drm/amd/display: fix struct init in update_bounding_box

[Sasha Levin]

From: Raul E Rangel 

[ Upstream commit 960b6f4f2d2e96d5f7ffe2854e0040b46cafbd36 ]

dcn20_resource.c:2636:9: error: missing braces around initializer 
[-Werror=missing-braces]
  struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] 
= {0};
 ^

Fixes: 7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource")

Signed-off-by: Raul E Rangel 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index ebe67c34dabf6..78b2cc2e122fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3041,7 +3041,7 @@ static void cap_soc_clocks(
 static void update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table *max_clocks, unsigned int 
*uclk_states, unsigned int num_states)
 {
-   struct _vcs_dpi_voltage_scaling_st 
calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
+   struct _vcs_dpi_voltage_scaling_st 
calculated_states[MAX_CLOCK_LIMIT_STATES];
int i;
int num_calculated_states = 0;
int min_dcfclk = 0;
@@ -3049,6 +3049,8 @@ static void update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_
if (num_states == 0)
return;
 
+   memset(calculated_states, 0, sizeof(calculated_states));
+
if (dc->bb_overrides.min_dcfclk_mhz > 0)
min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
else
-- 
2.20.1

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[PATCH AUTOSEL 5.4 230/350] drm/amdgpu: disallow direct upload save restore list from gfx driver

[Sasha Levin]

From: Hawking Zhang 

[ Upstream commit 58f46d4b65021083ef4b4d49c6e2c58e5783f626 ]

Direct uploading save/restore list via mmio register writes breaks the security
policy. Instead, the driver should pass s list to psp.

For all the ASICs that use rlc v2_1 headers, the driver actually upload s list
twice, in non-psp ucode front door loading phase and gfx pg initialization 
phase.
The latter is not allowed.

VG12 is the only exception where the driver still keeps legacy approach for S
list uploading. In theory, this can be elimnated if we have valid srcntl ucode
for VG12.

Signed-off-by: Hawking Zhang 
Reviewed-by: Candice Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 97cf0b5368737..c9ba2ec6d0382 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2930,7 +2930,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 * And it's needed by gfxoff feature.
 */
if (adev->gfx.rlc.is_rlc_v2_1) {
-   gfx_v9_1_init_rlc_save_restore_list(adev);
+   if (adev->asic_type == CHIP_VEGA12)
+   gfx_v9_1_init_rlc_save_restore_list(adev);
gfx_v9_0_enable_save_restore_machine(adev);
}
 
-- 
2.20.1

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[PATCH AUTOSEL 5.4 073/350] drm/amdkfd: Fix MQD size calculation

[Sasha Levin]

From: Oak Zeng 

[ Upstream commit 40a9592a26608e16f7545a068ea4165e1869f629 ]

On device initialization, a chunk of GTT memory is pre-allocated for
HIQ and all SDMA queues mqd. The size of this allocation was wrong.
The correct sdma engine number should be PCIe-optimized SDMA engine
number plus xgmi SDMA engine number.

Reported-by: Jonathan Kim 
Signed-off-by: Jonathan Kim 
Signed-off-by: Oak Zeng 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index d985e31fcc1eb..f335f73919d15 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1676,7 +1676,8 @@ static int allocate_hiq_sdma_mqd(struct 
device_queue_manager *dqm)
struct kfd_dev *dev = dqm->dev;
struct kfd_mem_obj *mem_obj = >hiq_sdma_mqd;
uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
-   dev->device_info->num_sdma_engines *
+   (dev->device_info->num_sdma_engines +
+   dev->device_info->num_xgmi_sdma_engines) *
dev->device_info->num_sdma_queues_per_engine +
dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
 
-- 
2.20.1

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[PATCH AUTOSEL 5.4 246/350] drm/amdgpu: Avoid accidental thread reactivation.

[Sasha Levin]

From: Andrey Grodzovsky 

[ Upstream commit a28fda312a9fabdf0e5f5652449d6197c9fb0a90 ]

Problem:
During GPU reset we call the GPU scheduler to suspend it's
thread, those two functions in amdgpu also suspend and resume
the sceduler for their needs but this can collide with GPU
reset in progress and accidently restart a suspended thread
before time.

Fix:
Serialize with GPU reset.

Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 5652cc72ed3a9..81842ba8cd757 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -859,6 +859,9 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void 
*data)
struct amdgpu_device *adev = dev->dev_private;
int r = 0, i;
 
+   /* Avoid accidently unparking the sched thread during GPU reset */
+   mutex_lock(>lock_reset);
+
/* hold on the scheduler */
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
struct amdgpu_ring *ring = adev->rings[i];
@@ -884,6 +887,8 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void 
*data)
kthread_unpark(ring->sched.thread);
}
 
+   mutex_unlock(>lock_reset);
+
return 0;
 }
 
@@ -1036,6 +1041,9 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
if (!fences)
return -ENOMEM;
 
+   /* Avoid accidently unparking the sched thread during GPU reset */
+   mutex_lock(>lock_reset);
+
/* stop the scheduler */
kthread_park(ring->sched.thread);
 
@@ -1075,6 +1083,8 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
/* restart the scheduler */
kthread_unpark(ring->sched.thread);
 
+   mutex_unlock(>lock_reset);
+
ttm_bo_unlock_delayed_workqueue(>mman.bdev, resched);
 
if (fences)
-- 
2.20.1

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[PATCH AUTOSEL 5.4 115/350] drm/amd/powerplay: avoid disabling ECC if RAS is enabled for VEGA20

[Sasha Levin]

From: Le Ma 

[ Upstream commit df9331e561dab0a451cbd6a679ee88a95f306fd6 ]

Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
for ECC supported SKU.

Signed-off-by: Le Ma 
Reviewed-by: Alex Deucher 
Reviewed-by: Hawking Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
index df6ff92524011..b068d1c7b44d2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
@@ -29,7 +29,7 @@
 #include "vega20_baco.h"
 #include "vega20_smumgr.h"
 
-
+#include "amdgpu_ras.h"
 
 static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
 {
@@ -74,6 +74,7 @@ int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum 
BACO_STATE *state)
 int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
enum BACO_STATE cur_state;
uint32_t data;
 
@@ -84,10 +85,11 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum 
BACO_STATE state)
return 0;
 
if (state == BACO_STATE_IN) {
-   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
-   data |= 0x8000;
-   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
-
+   if (!ras || !ras->supported) {
+   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+   data |= 0x8000;
+   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+   }
 
if(smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_EnterBaco, 0))
return -EINVAL;
-- 
2.20.1

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[PATCH AUTOSEL 5.4 100/350] drm/amd/display: Fix dongle_caps containing stale information.

[Sasha Levin]

From: David Galiffi 

[ Upstream commit dd998291dbe92106d8c4a7581c409b356928d711 ]

[WHY]

During detection:
function: get_active_converter_info populates link->dpcd_caps.dongle_caps
only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is
DOWN_STREAM_DETAILED_HDMI or DOWN_STREAM_DETAILED_DP_PLUS_PLUS.
Otherwise, it is not cleared, and stale information remains.

During mode validation:
function: dp_active_dongle_validate_timing reads
link->dpcd_caps.dongle_caps->dongle_type to determine the maximum
pixel clock to support. This information is now stale and no longer
valid.

[HOW]
dp_active_dongle_validate_timing should be using
link->dpcd_caps->dongle_type instead.

Signed-off-by: David Galiffi 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c| 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index de1b61595ffbf..efc1d30544bb6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2219,7 +2219,7 @@ static bool dp_active_dongle_validate_timing(
break;
}
 
-   if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
+   if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
dongle_caps->extendedCapValid == false)
return true;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9e261dbf2e493..5a583707d198a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2545,6 +2545,7 @@ static void get_active_converter_info(
uint8_t data, struct dc_link *link)
 {
union dp_downstream_port_present ds_port = { .byte = data };
+   memset(>dpcd_caps.dongle_caps, 0, 
sizeof(link->dpcd_caps.dongle_caps));
 
/* decode converter info*/
if (!ds_port.fields.PORT_PRESENT) {
-- 
2.20.1

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[PATCH AUTOSEL 5.4 125/350] drm/amd/display: enable hostvm based on roimmu active for dcn2.1

[Sasha Levin]

From: Dmytro Laktyushkin 

[ Upstream commit 48d92e8eda3d9b61978377e7539bfc5958e850cf ]

Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.

Signed-off-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 40 ---
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index d1266741763b9..f5f6b4a0f0aa4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -22,6 +22,7 @@
  * Authors: AMD
  *
  */
+#include 
 #include "dm_services.h"
 #include "dcn20/dcn20_hubbub.h"
 #include "dcn21_hubbub.h"
@@ -71,30 +72,39 @@ static uint32_t convert_and_clamp(
 void dcn21_dchvm_init(struct hubbub *hubbub)
 {
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+   uint32_t riommu_active;
+   int i;
 
//Init DCHVM block
REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
 
//Poll until RIOMMU_ACTIVE = 1
-   //TODO: Figure out interval us and retry count
-   REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);
+   for (i = 0; i < 100; i++) {
+   REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, _active);
 
-   //Reflect the power status of DCHUBBUB
-   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
+   if (riommu_active)
+   break;
+   else
+   udelay(5);
+   }
+
+   if (riommu_active) {
+   //Reflect the power status of DCHUBBUB
+   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
 
-   //Start rIOMMU prefetching
-   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
+   //Start rIOMMU prefetching
+   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
 
-   // Enable dynamic clock gating
-   REG_UPDATE_4(DCHVM_CLK_CTRL,
-   HVM_DISPCLK_R_GATE_DIS, 0,
-   HVM_DISPCLK_G_GATE_DIS, 0,
-   HVM_DCFCLK_R_GATE_DIS, 0,
-   HVM_DCFCLK_G_GATE_DIS, 0);
+   // Enable dynamic clock gating
+   REG_UPDATE_4(DCHVM_CLK_CTRL,
+   HVM_DISPCLK_R_GATE_DIS, 0,
+   HVM_DISPCLK_G_GATE_DIS, 0,
+   HVM_DCFCLK_R_GATE_DIS, 0,
+   HVM_DCFCLK_G_GATE_DIS, 0);
 
-   //Poll until HOSTVM_PREFETCH_DONE = 1
-   //TODO: Figure out interval us and retry count
-   REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+   //Poll until HOSTVM_PREFETCH_DONE = 1
+   REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+   }
 }
 
 static int hubbub21_init_dchub(struct hubbub *hubbub,
-- 
2.20.1

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[PATCH AUTOSEL 5.4 102/350] drm/amd/display: Program DWB watermarks from correct state

[Sasha Levin]

From: Julian Parkin 

[ Upstream commit edb922b022c0c94805c4ffad202b3edff83d76f0 ]

[Why]
When diags adds a DWB via a stream update, we calculate MMHUBBUB
paramaters, but dc->current_state has not yet been updated
when the DWB programming happens. This leads to overflow on
high bandwidth tests since the incorrect MMHUBBUB arbitration
parameters are programmed.

[How]
Pass the updated context down to the (enable|update)_writeback functions
so that they can use the correct watermarks when programming MMHUBBUB.

Signed-off-by: Julian Parkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c| 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 +++--
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  | 6 --
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index bf1d7bb90e0f9..bb09243758fe3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -423,10 +423,10 @@ bool dc_stream_add_writeback(struct dc *dc,
 
if (dwb->funcs->is_enabled(dwb)) {
/* writeback pipe already enabled, only need to update 
*/
-   dc->hwss.update_writeback(dc, stream_status, wb_info);
+   dc->hwss.update_writeback(dc, stream_status, wb_info, 
dc->current_state);
} else {
/* Enable writeback pipe from scratch*/
-   dc->hwss.enable_writeback(dc, stream_status, wb_info);
+   dc->hwss.enable_writeback(dc, stream_status, wb_info, 
dc->current_state);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 1212da12c4144..9108240d3c1b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1337,7 +1337,8 @@ bool dcn20_update_bandwidth(
 static void dcn20_enable_writeback(
struct dc *dc,
const struct dc_stream_status *stream_status,
-   struct dc_writeback_info *wb_info)
+   struct dc_writeback_info *wb_info,
+   struct dc_state *context)
 {
struct dwbc *dwb;
struct mcif_wb *mcif_wb;
@@ -1354,7 +1355,7 @@ static void dcn20_enable_writeback(
optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
/* set MCIF_WB buffer and arbitration configuration */
mcif_wb->funcs->config_mcif_buf(mcif_wb, _info->mcif_buf_params, 
wb_info->dwb_params.dest_height);
-   mcif_wb->funcs->config_mcif_arb(mcif_wb, 
>current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
+   mcif_wb->funcs->config_mcif_arb(mcif_wb, 
>bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
/* Enable MCIF_WB */
mcif_wb->funcs->enable_mcif(mcif_wb);
/* Enable DWB */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 3a938cd414ea4..f6cc2d6f576d2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -321,10 +321,12 @@ struct hw_sequencer_funcs {
struct dc_state *context);
void (*update_writeback)(struct dc *dc,
const struct dc_stream_status *stream_status,
-   struct dc_writeback_info *wb_info);
+   struct dc_writeback_info *wb_info,
+   struct dc_state *context);
void (*enable_writeback)(struct dc *dc,
const struct dc_stream_status *stream_status,
-   struct dc_writeback_info *wb_info);
+   struct dc_writeback_info *wb_info,
+   struct dc_state *context);
void (*disable_writeback)(struct dc *dc,
unsigned int dwb_pipe_inst);
 #endif
-- 
2.20.1

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[PATCH AUTOSEL 5.4 232/350] drm/amdgpu: fix potential double drop fence reference

[Sasha Levin]

From: Pan Bian 

[ Upstream commit 946ab8db6953535a3a88c957db8328beacdfed9d ]

The object fence is not set to NULL after its reference is dropped. As a
result, its reference may be dropped again if error occurs after that,
which may lead to a use after free bug. To avoid the issue, fence is
explicitly set to NULL after dropping its reference.

Acked-by: Christian König 
Signed-off-by: Pan Bian 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
index b66d29d5ffa2c..b158230af8db7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
@@ -138,6 +138,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
}
 
dma_fence_put(fence);
+   fence = NULL;
 
r = amdgpu_bo_kmap(vram_obj, _map);
if (r) {
@@ -183,6 +184,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
}
 
dma_fence_put(fence);
+   fence = NULL;
 
r = amdgpu_bo_kmap(gtt_obj[i], _map);
if (r) {
-- 
2.20.1

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[PATCH AUTOSEL 5.4 095/350] drm/amd/display: Properly round nominal frequency for SPD

[Sasha Levin]

From: Aric Cyr 

[ Upstream commit c59802313e84bede954235b3a5dd0dd5325f49c5 ]

[Why]
Some displays rely on the SPD verticle frequency maximum value.
Must round the calculated refresh rate to the nearest integer.

[How]
Round the nominal calculated refresh rate to the nearest whole
integer.

Signed-off-by: Aric Cyr 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/modules/freesync/freesync.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index ec70c9b12e1aa..0978c698f0f85 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -743,6 +743,10 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
nominal_field_rate_in_uhz =
mod_freesync_calc_nominal_field_rate(stream);
 
+   /* Rounded to the nearest Hz */
+   nominal_field_rate_in_uhz = 100ULL *
+   div_u64(nominal_field_rate_in_uhz + 50, 100);
+
min_refresh_in_uhz = in_config->min_refresh_in_uhz;
max_refresh_in_uhz = in_config->max_refresh_in_uhz;
 
@@ -996,14 +1000,13 @@ unsigned long long mod_freesync_calc_nominal_field_rate(
const struct dc_stream_state *stream)
 {
unsigned long long nominal_field_rate_in_uhz = 0;
+   unsigned int total = stream->timing.h_total * stream->timing.v_total;
 
-   /* Calculate nominal field rate for stream */
+   /* Calculate nominal field rate for stream, rounded up to nearest 
integer */
nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz / 10;
nominal_field_rate_in_uhz *= 1000ULL * 1000ULL * 1000ULL;
-   nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
-   stream->timing.h_total);
-   nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
-   stream->timing.v_total);
+
+   nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, 
total);
 
return nominal_field_rate_in_uhz;
 }
-- 
2.20.1

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[PATCH AUTOSEL 5.4 050/350] drm/amd/display: Set number of pipes to 1 if the second pipe was disabled

[Sasha Levin]

From: Nikola Cornij 

[ Upstream commit 2fef0faa1cdc5d41ce3ef83f7b8f7e7ecb02d700 ]

[why]
Some ODM-related register settings are inconsistently updated by VBIOS, causing
the state in DC to be invalid, which would then end up crashing in certain
use-cases (such as disable/enable device).

[how]
Check the enabled status of the second pipe when determining the number of
OPTC sources. If the second pipe is disabled, set the number of sources to 1
regardless of other settings (that may not be updated correctly).

Signed-off-by: Nikola Cornij 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 2137e2be21404..dda90995ba933 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -287,6 +287,10 @@ void optc2_get_optc_source(struct timing_generator *optc,
*num_of_src_opp = 2;
else
*num_of_src_opp = 1;
+
+   /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
+   if (*src_opp_id_1 == 0xf)
+   *num_of_src_opp = 1;
 }
 
 void optc2_set_dwb_source(struct timing_generator *optc,
-- 
2.20.1

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[PATCH AUTOSEL 5.4 126/350] drm/amd/display: fix header for RN clk mgr

[Sasha Levin]

From: joseph gravenor 

[ Upstream commit cd83fa1ea9b9431cf1d57ac4179a11bc4393a5b6 ]

[why]
Should always MP0_BASE for any register definition from MP per-IP header files.
I belive the reason the linux version of MP1_BASE works is The 0th element of 
the 0th table
of that is identical to the corrisponding value of MP0_BASE in the renoir 
offset header file.
The reason we should only use MP0_BASE is There is only one set of per-IP 
headers MP
that includes all register definitions related to SMU IP block. This IP 
includes MP0, MP1, MP2
and  an ecryption engine that can be used only by MP0. As a result all register 
definitions from
MP file should be based only on MP0_BASE data.

[How]
Change MP1_BASE to MP0_BASE

Signed-off-by: joseph gravenor 
Acked-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 50984c1811bb2..468c6bb0e3119 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -33,7 +33,7 @@
 #include "mp/mp_12_0_0_sh_mask.h"
 
 #define REG(reg_name) \
-   (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## 
reg_name)
+   (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## 
reg_name)
 
 #define FN(reg_name, field) \
FD(reg_name##__##field)
-- 
2.20.1

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[PATCH AUTOSEL 5.4 231/350] drm/amd/powerplay: fix struct init in renoir_print_clk_levels

[Sasha Levin]

From: Raul E Rangel 

[ Upstream commit d942070575910fdb687b9c8fd5467704b2f77c24 ]

drivers/gpu/drm/amd/powerplay/renoir_ppt.c:186:2: error: missing braces
around initializer [-Werror=missing-braces]
  SmuMetrics_t metrics = {0};
^

Fixes: 8b8031703bd7 ("drm/amd/powerplay: implement sysfs for getting dpm clock")

Signed-off-by: Raul E Rangel 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index e62bfba51562d..e5283dafc4148 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -183,11 +183,13 @@ static int renoir_print_clk_levels(struct smu_context 
*smu,
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
-   SmuMetrics_t metrics = {0};
+   SmuMetrics_t metrics;
 
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
 
+   memset(, 0, sizeof(metrics));
+
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
   (void *), false);
if (ret)
-- 
2.20.1

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[PATCH AUTOSEL 5.4 127/350] drm/amdgpu: fix amdgpu trace event print string format error

[Sasha Levin]

From: Kevin Wang 

[ Upstream commit 2c2fdb8bca290c439e383cfb6857b0c65e528964 ]

the trace event print string format error.
(use integer type to handle string)

before:
amdgpu_test_kev-1556  [002]   138.508781: amdgpu_cs_ioctl:
sched_job=8, timeline=gfx_0.0.0, context=177, seqno=1,
ring_name=94d01c207bf0, num_ibs=2

after:
amdgpu_test_kev-1506  [004]   370.703783: amdgpu_cs_ioctl:
sched_job=12, timeline=gfx_0.0.0, context=234, seqno=2,
ring_name=gfx_0.0.0, num_ibs=1

change trace event list:
1.amdgpu_cs_ioctl
2.amdgpu_sched_run_job
3.amdgpu_ib_pipe_sync

Signed-off-by: Kevin Wang 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 77674a7b96163..91899d28fa722 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -170,7 +170,7 @@ TRACE_EVENT(amdgpu_cs_ioctl,
 __field(unsigned int, context)
 __field(unsigned int, seqno)
 __field(struct dma_fence *, fence)
-__field(char *, ring_name)
+__string(ring, 
to_amdgpu_ring(job->base.sched)->name)
 __field(u32, num_ibs)
 ),
 
@@ -179,12 +179,12 @@ TRACE_EVENT(amdgpu_cs_ioctl,
   __assign_str(timeline, 
AMDGPU_JOB_GET_TIMELINE_NAME(job))
   __entry->context = 
job->base.s_fence->finished.context;
   __entry->seqno = job->base.s_fence->finished.seqno;
-  __entry->ring_name = 
to_amdgpu_ring(job->base.sched)->name;
+  __assign_str(ring, 
to_amdgpu_ring(job->base.sched)->name)
   __entry->num_ibs = job->num_ibs;
   ),
TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, 
ring_name=%s, num_ibs=%u",
  __entry->sched_job_id, __get_str(timeline), 
__entry->context,
- __entry->seqno, __entry->ring_name, __entry->num_ibs)
+ __entry->seqno, __get_str(ring), __entry->num_ibs)
 );
 
 TRACE_EVENT(amdgpu_sched_run_job,
@@ -195,7 +195,7 @@ TRACE_EVENT(amdgpu_sched_run_job,
 __string(timeline, 
AMDGPU_JOB_GET_TIMELINE_NAME(job))
 __field(unsigned int, context)
 __field(unsigned int, seqno)
-__field(char *, ring_name)
+__string(ring, 
to_amdgpu_ring(job->base.sched)->name)
 __field(u32, num_ibs)
 ),
 
@@ -204,12 +204,12 @@ TRACE_EVENT(amdgpu_sched_run_job,
   __assign_str(timeline, 
AMDGPU_JOB_GET_TIMELINE_NAME(job))
   __entry->context = 
job->base.s_fence->finished.context;
   __entry->seqno = job->base.s_fence->finished.seqno;
-  __entry->ring_name = 
to_amdgpu_ring(job->base.sched)->name;
+  __assign_str(ring, 
to_amdgpu_ring(job->base.sched)->name)
   __entry->num_ibs = job->num_ibs;
   ),
TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, 
ring_name=%s, num_ibs=%u",
  __entry->sched_job_id, __get_str(timeline), 
__entry->context,
- __entry->seqno, __entry->ring_name, __entry->num_ibs)
+ __entry->seqno, __get_str(ring), __entry->num_ibs)
 );
 
 
@@ -468,7 +468,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
TP_PROTO(struct amdgpu_job *sched_job, struct dma_fence *fence),
TP_ARGS(sched_job, fence),
TP_STRUCT__entry(
-__field(const char *,name)
+__string(ring, sched_job->base.sched->name);
 __field(uint64_t, id)
 __field(struct dma_fence *, fence)
 __field(uint64_t, ctx)
@@ -476,14 +476,14 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
 ),
 
TP_fast_assign(
-  __entry->name = sched_job->base.sched->name;
+  __assign_str(ring, sched_job->base.sched->name)
   __entry->id = sched_job->base.id;
   __entry->fence = fence;
   __entry->ctx = fence->context;
   __entry->seqno = fence->seqno;
   ),
TP_printk("job ring=%s, id=%llu, need pipe sync to fence=%p, 
context=%llu, seq=%u",
- __entry->name, __entry->id,
+

[PATCH AUTOSEL 5.4 160/350] drm/amd/display: setting the DIG_MODE to the correct value.

[Sasha Levin]

From: Zhan liu 

[ Upstream commit 967a3b85bac91c55eff740e61bf270c2732f48b2 ]

[Why]
This patch is for fixing Navi14 HDMI display pink screen issue.

[How]
Call stream->link->link_enc->funcs->setup twice. This is setting
the DIG_MODE to the correct value after having been overridden by
the call to transmitter control.

Signed-off-by: Zhan Liu 
Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index efc1d30544bb6..067f5579f4523 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2769,6 +2769,15 @@ void core_link_enable_stream(
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);
 
+   /* This second call is needed to reconfigure the DIG
+* as a workaround for the incorrect value being applied
+* from transmitter control.
+*/
+   if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+   stream->link->link_enc->funcs->setup(
+   stream->link->link_enc,
+   pipe_ctx->stream->signal);
+
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
-- 
2.20.1

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[PATCH AUTOSEL 5.4 057/350] drm/amd/display: set minimum abm backlight level

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 2ad0cdf9e2e9e079af34af681863fa638f2ee212 ]

[Why]
A lot of the time, the backlight characteristic curve maps min backlight
to a non-zero value.
But there are cases where we want the curve to intersect at 0.
In this scenario even if OS never asks to set 0% backlight, the ABM
reduction can result in backlight being lowered close to 0.
This particularly can cause problems in some LED drivers, and in
general just looks like backlight is completely off.

[How]
Add default cap to disallow backlight from dropping below 1%
even after ABM reduction is applied.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  5 ++
 .../amd/display/modules/power/power_helpers.c | 77 +++
 .../amd/display/modules/power/power_helpers.h |  1 +
 3 files changed, 49 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4139f129eafb4..4e9c15c409bac 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -940,6 +940,11 @@ static int dm_late_init(void *handle)
params.backlight_lut_array_size = 16;
params.backlight_lut_array = linear_lut;
 
+   /* Min backlight level after ABM reduction,  Don't allow below 1%
+* 0x x 0.01 = 0x28F
+*/
+   params.min_abm_backlight = 0x28F;
+
/* todo will enable for navi10 */
if (adev->asic_type <= CHIP_RAVEN) {
ret = dmcu_load_iram(dmcu, params);
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 05e2be856037e..ba1aafe40512e 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -115,7 +115,7 @@ static const struct abm_parameters * const abm_settings[] = 
{
 /* NOTE: iRAM is 256B in size */
 struct iram_table_v_2 {
/* flags  */
-   uint16_t flags; /* 0x00 
U16  */
+   uint16_t min_abm_backlight; /* 0x00 
U16  */
 
/* parameters for ABM2.0 algorithm */
uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x02 
U0.8 */
@@ -140,10 +140,10 @@ struct iram_table_v_2 {
 
/* For reading PSR State directly from IRAM */
uint8_t psr_state;  /* 0xf0 
  */
-   uint8_t dmcu_mcp_interface_version; 
/* 0xf1   */
-   uint8_t dmcu_abm_feature_version;   
/* 0xf2   */
-   uint8_t dmcu_psr_feature_version;   
/* 0xf3   */
-   uint16_t dmcu_version;  
/* 0xf4   */
+   uint8_t dmcu_mcp_interface_version; /* 0xf1 
  */
+   uint8_t dmcu_abm_feature_version;   /* 0xf2 
  */
+   uint8_t dmcu_psr_feature_version;   /* 0xf3 
  */
+   uint16_t dmcu_version;  /* 0xf4 
  */
uint8_t dmcu_state; /* 0xf6 
  */
 
uint16_t blRampReduction;   /* 0xf7 
  */
@@ -164,42 +164,43 @@ struct iram_table_v_2_2 {
uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x16 
U0.8 */
uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];/* 0x2a 
U2.6 */
uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x3e 
U2.6 */
-   uint8_t hybrid_factor[NUM_AGGR_LEVEL];  
/* 0x52 U0.8 */
-   uint8_t contrast_factor[NUM_AGGR_LEVEL];
/* 0x56 U0.8 */
-   uint8_t deviation_gain[NUM_AGGR_LEVEL]; 
/* 0x5a U0.8 */
-   uint8_t iir_curve[NUM_AMBI_LEVEL];  
/* 0x5e U0.8 */
-   uint8_t min_knee[NUM_AGGR_LEVEL];   
/* 0x63 U0.8 */
-   uint8_t max_knee[NUM_AGGR_LEVEL];   
/* 0x67 U0.8 */
-   uint8_t pad[21];
/* 0x6b U0.8 */
+   uint8_t hybrid_factor[NUM_AGGR_LEVEL];  /* 0x52 
U0.8 */
+   uint8_t contrast_factor[NUM_AGGR_LEVEL];/* 0x56 
U0.8 */
+   uint8_t 

[PATCH AUTOSEL 5.4 337/350] drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2

[Sasha Levin]

From: Sam Bobroff 

[ Upstream commit 3d0e3ce52ce3eb4b9de3caf9c38dbb5a4d3e13c3 ]

The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address.  This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8 guest).

Instead, use the DMA address of the dummy page because it will always
be safe.

Fixes: 27ae10641e9c ("drm/amdgpu: add interupt handler implementation for si 
v3")
Signed-off-by: Sam Bobroff 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c 
b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 57bb5f9e08b2d..88ae27a5a03db 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -64,7 +64,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
 
si_ih_disable_interrupts(adev);
-   WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
+   /* set dummy read address to dummy page address */
+   WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
interrupt_cntl = RREG32(INTERRUPT_CNTL);
interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
-- 
2.20.1

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Re: [PATCH] drm/amd/display: fix undefined struct member reference

[Kazlauskas, Nicholas]

On 2019-12-10 3:54 p.m., Liu, Zhan wrote:




-Original Message-
From: Arnd Bergmann 
Sent: 2019/December/10, Tuesday 3:31 PM
To: Wentland, Harry ; Li, Sun peng (Leo)
; Deucher, Alexander
; Koenig, Christian
; Zhou, David(ChunMing)
; David Airlie ; Daniel Vetter
; Liu, Zhan 
Cc: Arnd Bergmann ; Laktyushkin, Dmytro
; Lakha, Bhawanpreet
; Lei, Jun ; Liu,
Charlene ; Yang, Eric ;
Cornij, Nikola ; amd-gfx@lists.freedesktop.org;
dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org
Subject: [PATCH] drm/amd/display: fix undefined struct member reference

An initialization was added for two optional struct members.  One of these is
always present in the dcn20_resource file, but the other one depends on
CONFIG_DRM_AMD_DC_DSC_SUPPORT and causes a build failure if that is
missing:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:926:1
4: error: excess elements in struct initializer [-Werror]
.num_dsc = 5,

Add another #ifdef around the assignment.

Fixes: c3d03c5a196f ("drm/amd/display: Include num_vmid and num_dsc
within NV14's resource caps")
Signed-off-by: Arnd Bergmann 


Thank you for catching that  On my side I kept that flag enabled all the time, 
so I didn't realize there was a warning hidden here.

Reviewed-by: Zhan Liu 


What tree is this reported on?

We dropped this flag whenever building DCN. Sounds like we're missing a 
patch if you're getting this.


So this is a NAK from me for going into amd-staging-drm-next at least.

Nicholas Kazlauskas




---
  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index faab89d1e694..fdf93e6edf43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -923,7 +923,9 @@ static const struct resource_caps res_cap_nv14 = {
.num_dwb = 1,
.num_ddc = 5,
.num_vmid = 16,
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
.num_dsc = 5,
+#endif
  };

  static const struct dc_debug_options debug_defaults_drv = {
--
2.20.0


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RE: [PATCH] drm/amd/display: fix undefined struct member reference

[Liu, Zhan]

> -Original Message-
> From: Arnd Bergmann 
> Sent: 2019/December/10, Tuesday 3:31 PM
> To: Wentland, Harry ; Li, Sun peng (Leo)
> ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; David Airlie ; Daniel Vetter
> ; Liu, Zhan 
> Cc: Arnd Bergmann ; Laktyushkin, Dmytro
> ; Lakha, Bhawanpreet
> ; Lei, Jun ; Liu,
> Charlene ; Yang, Eric ;
> Cornij, Nikola ; amd-gfx@lists.freedesktop.org;
> dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: [PATCH] drm/amd/display: fix undefined struct member reference
> 
> An initialization was added for two optional struct members.  One of these is
> always present in the dcn20_resource file, but the other one depends on
> CONFIG_DRM_AMD_DC_DSC_SUPPORT and causes a build failure if that is
> missing:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:926:1
> 4: error: excess elements in struct initializer [-Werror]
>.num_dsc = 5,
> 
> Add another #ifdef around the assignment.
> 
> Fixes: c3d03c5a196f ("drm/amd/display: Include num_vmid and num_dsc
> within NV14's resource caps")
> Signed-off-by: Arnd Bergmann 

Thank you for catching that  On my side I kept that flag enabled all the time, 
so I didn't realize there was a warning hidden here. 

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index faab89d1e694..fdf93e6edf43 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -923,7 +923,9 @@ static const struct resource_caps res_cap_nv14 = {
>   .num_dwb = 1,
>   .num_ddc = 5,
>   .num_vmid = 16,
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>   .num_dsc = 5,
> +#endif
>  };
> 
>  static const struct dc_debug_options debug_defaults_drv = {
> --
> 2.20.0

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Re: [PATCH] drm/amd/display: include linux/slab.h where needed

[Kazlauskas, Nicholas]

On 2019-12-10 2:59 p.m., Arnd Bergmann wrote:

Calling kzalloc() and related functions requires the
linux/slab.h header to be included:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 
'dcn21_ipp_create':
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error: 
implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? 
[-Werror=implicit-function-declaration]
kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);

A lot of other headers also miss a direct include in this file,
but this is the only one that causes a problem for now.

Signed-off-by: Arnd Bergmann 


What version of the kernel are you building?

We have:

#include 

in os_types.h which gets included as part of this file:

#include  -> #include  -> #include 

Nicholas Kazlauskas


---
  drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 906c84e6b49b..af57885bbff2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -23,6 +23,8 @@
   *
   */
  
+#include 

+
  #include "dm_services.h"
  #include "dc.h"
  



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Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI

[Andrey Grodzovsky]

I switched the workqueue we were using for xgmi_reset_work from 
system_highpri_wq to system_unbound_wq - the difference is that workers 
servicing the queue in system_unbound_wq are not bounded to specific CPU 
and so the reset jobs for each XGMI node are getting scheduled to 
different CPU while system_highpri_wq is a bounded work queue. I traced 
it as bellow for 10 consecutive times and didn't see errors any more. 
Also the time diff between BACO entries or exits was never more then 
around 2 uS.


Please give this updated patchset a try

   kworker/u16:2-57    [004] ...1   243.276312: trace_code: func: 
vega20_baco_set_state, line 91 <- - Before BEACO enter
   <...>-60    [007] ...1   243.276312: trace_code: func: 
vega20_baco_set_state, line 91 <- - Before BEACO enter
   kworker/u16:2-57    [004] ...1   243.276384: trace_code: func: 
vega20_baco_set_state, line 105 <- - After BEACO enter done
   <...>-60    [007] ...1   243.276392: trace_code: func: 
vega20_baco_set_state, line 105 <- - After BEACO enter done
   kworker/u16:3-60    [007] ...1   243.276397: trace_code: func: 
vega20_baco_set_state, line 108 <- - Before BEACO exit
   kworker/u16:2-57    [004] ...1   243.276399: trace_code: func: 
vega20_baco_set_state, line 108 <- - Before BEACO exit
   kworker/u16:3-60    [007] ...1   243.288067: trace_code: func: 
vega20_baco_set_state, line 114 <- - After BEACO exit done
   kworker/u16:2-57    [004] ...1   243.295624: trace_code: func: 
vega20_baco_set_state, line 114 <- - After BEACO exit done


Andrey

On 12/9/19 9:45 PM, Ma, Le wrote:


[AMD Official Use Only - Internal Distribution Only]


I’m fine with your solution if synchronization time interval satisfies 
BACO requirements and loop test can pass on XGMI system.


Regards,

Ma Le

*From:*Grodzovsky, Andrey 
*Sent:* Monday, December 9, 2019 11:52 PM
*To:* Ma, Le ; amd-gfx@lists.freedesktop.org; Zhou1, 
Tao ; Deucher, Alexander 
; Li, Dennis ; Zhang, 
Hawking 

*Cc:* Chen, Guchun 
*Subject:* Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset 
support for XGMI


Thanks a lot Ma for trying - I think I have to have my own system to 
debug this so I will keep trying enabling XGMI - i still think the is 
the right and the generic solution for multiple nodes reset 
synchronization and in fact the barrier should also be used for 
synchronizing PSP mode 1 XGMI reset too.


Andrey

On 12/9/19 6:34 AM, Ma, Le wrote:

[AMD Official Use Only - Internal Distribution Only]

Hi Andrey,

I tried your patches on my 2P XGMI platform. The baco can work at
most time, and randomly got following error:

[ 1701.542298] amdgpu: [powerplay] Failed to send message 0x25,
response 0x0

This error usually means some sync issue exist for xgmi baco case.
Feel free to debug your patches on my XGMI platform.

Regards,

Ma Le

*From:*Grodzovsky, Andrey 

*Sent:* Saturday, December 7, 2019 5:51 AM
*To:* Ma, Le  ;
amd-gfx@lists.freedesktop.org
; Zhou1, Tao
 ; Deucher, Alexander
 ;
Li, Dennis  ; Zhang,
Hawking  
*Cc:* Chen, Guchun  
*Subject:* Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset
support for XGMI

Hey Ma, attached a solution - it's just compiled as I still can't
make my XGMI setup work (with bridge connected only one device is
visible to the system while the other is not). Please try it on
your system if you have a chance.

Andrey

On 12/4/19 10:14 PM, Ma, Le wrote:

AFAIK it's enough for even single one node in the hive to to
fail the enter the BACO state on time to fail the entire hive
reset procedure, no ?

[Le]: Yeah, agree that. I’ve been thinking that make all nodes
entering baco simultaneously can reduce the possibility of
node failure to enter/exit BACO risk. For example, in an XGMI
hive with 8 nodes, the total time interval of 8 nodes
enter/exit BACO on 8 CPUs is less than the interval that 8
nodes enter BACO serially and exit BACO serially depending on
one CPU with yield capability. This interval is usually strict
for BACO feature itself. Anyway, we need more looping test
later on any method we will choose.

Any way - I see our discussion blocks your entire patch set -
I think you can go ahead and commit yours way (I think you got
an RB from Hawking) and I will look then and see if I can
implement my method and if it works will just revert your patch.

[Le]: OK, fine.

Andrey

>From 8fcefad4194358ad55aba815cab437459f4bb0e4 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky 
Date: Fri, 6 Dec 2019 13:19:15 -0500

[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Yintian Tao]

Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
 .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 17 files changed, 352 insertions(+), 300 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3673,6 +3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, 
false) * 10;
dev_info.max_memory_clock = 

Re: [PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Nirmoy]

On 12/10/19 6:32 PM, Christian König wrote:


Maybe make this "num_sched_list > 1 ? sched_list : NULL" to avoid 
accidentally dereferencing a stale pointer to the stack.

Do you mean "num_sched_list >= 1 ? sched_list : NULL"


No, the entity->sched_list field should be NULL when num_sched_list==1.

When num_sched_list==1 the entity->sched_list shouldn't be used and we 
can use a dummy list on the stack as parameter. But we should set the 
pointer to NULL in this case just to make sure that nobody is 
dereferencing it.

Okay I understand now.





  -    if(!entity->sched_list)
-    return -ENOMEM;
    init_completion(>entity_idle);
-
-    for (i = 0; i < num_sched_list; i++)
-    entity->sched_list[i] = sched_list[i];
-
  if (num_sched_list)


That check can actually be dropped as well. We return -EINVAL when 
the num_sched_list is zero.


This  one took me some time to understand. So we don't really return 
-EINVAL if num_sched_list == 0


if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
    return -EINVAL;

This is coming from below patch. Are we suppose to tolerate IPs with 
uninitialized sched so that ctx creation dosn't return error ?


Yes, exactly. That's intentionally this way.

GPU reset sometimes resulted in schedulers being disabled because we 
couldn't re-init them. In this case we had entities with an empty 
scheduler list.


That can't happen any more after you make the scheduler arrays 
constant, but I would stick with that behavior.


So I will keep the check.



Regards,
Christian.



Regards,

Nirmoy

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[PATCH 1/4] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
 
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
 
-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}
 
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 81f6764f1ba6..2ff63d0414c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1954,11 +1954,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 
if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
 
ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d587ffe2af8e..a92f3b18e657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

[PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Nirmoy Das]

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c
index f9b6ce29c58f..2e3a058fc239 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -56,8 +56,6 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
  unsigned int num_sched_list,
  atomic_t *guilty)
 {
-   int i;
-
if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
return -EINVAL;
 
@@ -67,22 +65,14 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
entity->guilty = guilty;
entity->num_sched_list = num_sched_list;
entity->priority = priority;
-   entity->sched_list =  kcalloc(num_sched_list,
- sizeof(struct drm_gpu_scheduler *), 
GFP_KERNEL);
+   entity->sched_list = num_sched_list > 1 ? sched_list : NULL;
+   entity->last_scheduled = NULL;
 
-   if(!entity->sched_list)
-   return -ENOMEM;
+   if(num_sched_list)
+   entity->rq = _list[0]->sched_rq[entity->priority];
 
init_completion(>entity_idle);
 
-   for (i = 0; i < num_sched_list; i++)
-   entity->sched_list[i] = sched_list[i];
-
-   if (num_sched_list)
-   entity->rq = >sched_list[0]->sched_rq[entity->priority];
-
-   entity->last_scheduled = NULL;
-
spin_lock_init(>rq_lock);
spsc_queue_init(>job_queue);
 
@@ -312,7 +302,6 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
 
dma_fence_put(entity->last_scheduled);
entity->last_scheduled = NULL;
-   kfree(entity->sched_list);
 }
 EXPORT_SYMBOL(drm_sched_entity_fini);
 
-- 
2.24.0

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[PATCH 2/4] drm/amdgpu: replace vm_pte's run-queue list with drm gpu scheds list

[Nirmoy Das]

drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 ++--
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  5 ++---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/si_dma.c|  8 +++-
 9 files changed, 24 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..a7904d1e71f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2785,7 +2785,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->mman.buffer_funcs = NULL;
adev->mman.buffer_funcs_ring = NULL;
adev->vm_manager.vm_pte_funcs = NULL;
-   adev->vm_manager.vm_pte_num_rqs = 0;
+   adev->vm_manager.vm_pte_num_scheds = 0;
adev->gmc.gmc_funcs = NULL;
adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1c65b5bffa6b..b999b67ff57a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2744,7 +2744,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 {
struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
int r, i;
 
vm->va = RB_ROOT_CACHED;
@@ -2758,19 +2757,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
spin_lock_init(>invalidated_lock);
INIT_LIST_HEAD(>freed);
 
-   for (i = 0; i < adev->vm_manager.vm_pte_num_rqs; i++)
-   sched_list[i] = adev->vm_manager.vm_pte_rqs[i]->sched;
 
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(>direct, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
return r;
 
r = drm_sched_entity_init(>delayed, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
goto error_free_direct;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d5613d184e99..100547f094ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -330,8 +330,8 @@ struct amdgpu_vm_manager {
u64 vram_base_offset;
/* vm pte handling */
const struct amdgpu_vm_pte_funcs*vm_pte_funcs;
-   struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
-   unsignedvm_pte_num_rqs;
+   struct drm_gpu_scheduler
*vm_pte_scheds[AMDGPU_MAX_RINGS];
+   unsignedvm_pte_num_scheds;
struct amdgpu_ring  *page_fault;
 
/* partial resident texture handling */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 82cdb8f57bfd..1f22a8d0f7f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1373,16 +1373,14 @@ static const struct amdgpu_vm_pte_funcs 
cik_sdma_vm_pte_funcs = {
 
 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
-   struct drm_gpu_scheduler *sched;
unsigned i;
 
adev->vm_manager.vm_pte_funcs = _sdma_vm_pte_funcs;
for (i = 0; i < adev->sdma.num_instances; i++) {
-   sched = >sdma.instance[i].ring.sched;
-   adev->vm_manager.vm_pte_rqs[i] =
-   >sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+   adev->vm_manager.vm_pte_scheds[i] =
+   >sdma.instance[i].ring.sched;
}
-   adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+   adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
 }
 
 const struct 

[PATCH 3/4 v2] amd/amdgpu: add sched array to IPs with multiple run-queues

[Nirmoy Das]

This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h|   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   9 +-
 7 files changed, 89 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1d6850af9908..165d1a397266 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
   struct amdgpu_ctx *ctx)
 {
unsigned num_entities = amdgpu_ctx_total_num_entities();
-   unsigned i, j, k;
+   unsigned i, j;
int r;

if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;

for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-   struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-   unsigned num_rings = 0;
-   unsigned num_rqs = 0;
+   struct drm_gpu_scheduler **scheds;
+   struct drm_gpu_scheduler *sched;
+   unsigned num_scheds = 0;

switch (i) {
case AMDGPU_HW_IP_GFX:
-   rings[0] = >gfx.gfx_ring[0];
-   num_rings = 1;
+   scheds = adev->gfx.gfx_sched;
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
-   for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-   rings[j] = >gfx.compute_ring[j];
-   num_rings = adev->gfx.num_compute_rings;
+   scheds = adev->gfx.compute_sched;
+   num_scheds = adev->gfx.num_compute_sched;
break;
case AMDGPU_HW_IP_DMA:
-   for (j = 0; j < adev->sdma.num_instances; ++j)
-   rings[j] = >sdma.instance[j].ring;
-   num_rings = adev->sdma.num_instances;
+   scheds = adev->sdma.sdma_sched;
+   num_scheds = adev->sdma.num_sdma_sched;
break;
case AMDGPU_HW_IP_UVD:
-   rings[0] = >uvd.inst[0].ring;
-   num_rings = 1;
+   sched = >uvd.inst[0].ring.sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCE:
-   rings[0] = >vce.ring[0];
-   num_rings = 1;
+   sched = >vce.ring[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
-   rings[0] = >uvd.inst[0].ring_enc[0];
-   num_rings = 1;
+   sched = >uvd.inst[0].ring_enc[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCN_DEC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   rings[num_rings++] = 
>vcn.inst[j].ring_dec;
-   }
+   scheds = adev->vcn.vcn_dec_sched;
+   num_scheds =  adev->vcn.num_vcn_dec_sched;
break;
case AMDGPU_HW_IP_VCN_ENC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-   rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];
-   }
+   scheds = adev->vcn.vcn_enc_sched;
+   num_scheds =  adev->vcn.num_vcn_enc_sched;
break;
case AMDGPU_HW_IP_VCN_JPEG:
-   for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-  

Re: [PATCH 1/2] drm/amdgpu: modify invalidate semaphore limit in gmc9

[Christian König]

Am 10.12.19 um 17:20 schrieb Changfeng.Zhu:

From: changzhu 

It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.

Change-Id: I806f8e99ec97be84e6aed0f5c499a53b1931b490
Signed-off-by: changzhu 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 47 +++
  1 file changed, 27 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 601667246a1c..552fd7f3fec4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -412,6 +412,27 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int 
vmid,
return req;
  }
  
+/**

+ * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
+ *
+ * @adev: amdgpu_device pointer
+ * @vmhub: vmhub type
+ *
+ */
+static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
+  uint32_t vmhub)
+{
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
+   return true;
+   else
+   return false;


Probably better to not use an if here but instead just return the value. 
E.g. something like this:


return (vmhub == AMD. || ) &&
    


+}
+
  /*
   * GART
   * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -434,6 +455,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
const unsigned eng = 17;
u32 j, tmp;
struct amdgpu_vmhub *hub;
+   bool value = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);


Please use a more meaningful name for the variable, something like 
use_semaphore.


And move that to the beginning of the declaration.

Christian.

  
  	BUG_ON(vmhub >= adev->num_vmhubs);
  
@@ -464,11 +486,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8))) {
+   if (value) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -498,11 +516,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
}
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (value)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -524,6 +538,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
struct amdgpu_vmhub *hub = >vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
unsigned eng = ring->vm_inv_eng;
+   bool value = gmc_v9_0_use_invalidate_semaphore(ring->adev, 
ring->funcs->vmhub);
  
  	/*

 * It may lose gpuvm invalidate acknowldege state across power-gating
@@ -533,11 +548,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (value)
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -553,11 +564,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (value)
/*
 * add semaphore release after invalidation,
  

Re: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Alex Deucher]

() On Tue, Dec 10, 2019 at 4:36 AM Yintian Tao  wrote:
>
> Originally, due to the restriction from PSP and SMU, VF has
> to send message to hypervisor driver to handle powerplay
> change which is complicated and redundant. Currently, SMU
> and PSP can support VF to directly handle powerplay
> change by itself. Therefore, the old code about the handshake
> between VF and PF to handle powerplay will be removed and VF
> will use new the registers below to handshake with SMU.
> mmMP1_SMN_C2PMSG_101: register to handle SMU message
> mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
> mmMP1_SMN_C2PMSG_103: register to handle SMU response
>
> v2: remove module parameter pp_one_vf
> v3: fix the parens
> v4: forbid vf to change smu feature
>
> Signed-off-by: Yintian Tao 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 235 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 --
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
>  drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
>  .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
>  .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 162 
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
>  .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 -
>  .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
>  16 files changed, 406 insertions(+), 302 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index b9ca7e728d3e..465156a12d88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
> *adev)
> }
> }
>
> +   if (amdgpu_sriov_vf(adev))
> +   amdgpu_virt_init_data_exchange(adev);
> +
> r = amdgpu_ib_pool_init(adev);
> if (r) {
> dev_err(adev->dev, "IB initialization failed (%d).\n", r);
> @@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
> *adev)
> amdgpu_amdkfd_device_init(adev);
>
>  init_failed:
> -   if (amdgpu_sriov_vf(adev)) {
> -   if (!r)
> -   amdgpu_virt_init_data_exchange(adev);
> +   if (amdgpu_sriov_vf(adev))
> amdgpu_virt_release_full_gpu(adev, true);
> -   }
>
> return r;
>  }
> @@ -2819,7 +2819,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> mutex_init(>virt.vf_errors.lock);
> hash_init(adev->mn_hash);
> mutex_init(>lock_reset);
> -   mutex_init(>virt.dpm_mutex);
> mutex_init(>psp.mutex);
>
> r = amdgpu_device_check_arguments(adev);
> @@ -3040,9 +3039,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>
> amdgpu_fbdev_init(adev);
>
> -   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
> -   amdgpu_pm_virt_sysfs_init(adev);
> -
> r = amdgpu_pm_sysfs_init(adev);
> if (r) {
> adev->pm_sysfs_en = false;
> @@ -3187,8 +3183,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
> iounmap(adev->rmmio);
> adev->rmmio = NULL;
> amdgpu_device_doorbell_fini(adev);
> -   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
> -   amdgpu_pm_virt_sysfs_fini(adev);
>
> amdgpu_debugfs_regs_cleanup(adev);
> device_remove_file(adev->dev, _attr_pcie_replay_count);
> @@ -3669,6 +3663,7 @@ static int amdgpu_device_reset_sriov(struct 
> amdgpu_device *adev,
> if (r)
> goto error;
>
> +   amdgpu_virt_init_data_exchange(adev);
> /* we need recover gart prior to run SMC/CP/SDMA resume */
> amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
>
> @@ -3686,7 +3681,6 @@ static int amdgpu_device_reset_sriov(struct 
> amdgpu_device *adev,
> amdgpu_amdkfd_post_reset(adev);
>
>  error:
> -   amdgpu_virt_init_data_exchange(adev);
> amdgpu_virt_release_full_gpu(adev, true);
> if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
> amdgpu_inc_vram_lost(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 5ec1415d1755..3a0ea9096498 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, 
> void *data, struct drm_file
> if (adev->pm.dpm_enabled) {
> 

Re: [PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Christian König]

Am 10.12.19 um 16:08 schrieb Nirmoy:
I think amdgpu_ctx_init() should check for num_scheds and not call 
drm_sched_entity_init()


if its zero.


Ah, that's where that came from. No that is intentionally this way, but 
see below.




On 12/10/19 3:47 PM, Nirmoy wrote:


On 12/10/19 2:00 PM, Christian König wrote:

Am 10.12.19 um 13:53 schrieb Nirmoy Das:

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
  1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c

index f9b6ce29c58f..a5f729f421f8 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -67,17 +67,10 @@ int drm_sched_entity_init(struct 
drm_sched_entity *entity,

  entity->guilty = guilty;
  entity->num_sched_list = num_sched_list;
  entity->priority = priority;
-    entity->sched_list =  kcalloc(num_sched_list,
-  sizeof(struct drm_gpu_scheduler *), 
GFP_KERNEL);

+    entity->sched_list =  sched_list;


Maybe make this "num_sched_list > 1 ? sched_list : NULL" to avoid 
accidentally dereferencing a stale pointer to the stack.

Do you mean "num_sched_list >= 1 ? sched_list : NULL"


No, the entity->sched_list field should be NULL when num_sched_list==1.

When num_sched_list==1 the entity->sched_list shouldn't be used and we 
can use a dummy list on the stack as parameter. But we should set the 
pointer to NULL in this case just to make sure that nobody is 
dereferencing it.





  -    if(!entity->sched_list)
-    return -ENOMEM;
    init_completion(>entity_idle);
-
-    for (i = 0; i < num_sched_list; i++)
-    entity->sched_list[i] = sched_list[i];
-
  if (num_sched_list)


That check can actually be dropped as well. We return -EINVAL when 
the num_sched_list is zero.


This  one took me some time to understand. So we don't really return 
-EINVAL if num_sched_list == 0


if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
    return -EINVAL;

This is coming from below patch. Are we suppose to tolerate IPs with 
uninitialized sched so that ctx creation dosn't return error ?


Yes, exactly. That's intentionally this way.

GPU reset sometimes resulted in schedulers being disabled because we 
couldn't re-init them. In this case we had entities with an empty 
scheduler list.


That can't happen any more after you make the scheduler arrays constant, 
but I would stick with that behavior.


Regards,
Christian.



commit 1decbf6bb0b4dc56c9da6c5e57b994ebfc2be3aa
Author: Bas Nieuwenhuizen 
Date:   Wed Jan 30 02:53:19 2019 +0100

    drm/sched: Fix entities with 0 rqs.

    Some blocks in amdgpu can have 0 rqs.

    Job creation already fails with -ENOENT when entity->rq is NULL,
    so jobs cannot be pushed. Without a rq there is no scheduler to
    pop jobs, and rq selection already does the right thing with a
    list of length 0.

    So the operations we need to fix are:
  - Creation, do not set rq to rq_list[0] if the list can have 
length 0.

  - Do not flush any jobs when there is no rq.
  - On entity destruction handle the rq = NULL case.
  - on set_priority, do not try to change the rq if it is NULL.



Regards,
Christian.

  entity->rq = 
>sched_list[0]->sched_rq[entity->priority];
  @@ -312,7 +305,6 @@ void drm_sched_entity_fini(struct 
drm_sched_entity *entity)

    dma_fence_put(entity->last_scheduled);
  entity->last_scheduled = NULL;
-    kfree(entity->sched_list);
  }
  EXPORT_SYMBOL(drm_sched_entity_fini);




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RE: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Tao, Yintian]

Ping...

-Original Message-
From: Yintian Tao  
Sent: 2019年12月10日 17:36
To: Deucher, Alexander ; Feng, Kenneth 

Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 235 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 --
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 162 
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 -
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 16 files changed, 406 insertions(+), 302 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9ca7e728d3e..465156a12d88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2819,7 +2819,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3040,9 +3039,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3187,8 +3183,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3669,6 +3663,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3686,7 +3681,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = 

Re: [PATCH 2/2] drm/amdgpu: modify invalidate semaphore limit in gmc10

[Alex Deucher]

On Tue, Dec 10, 2019 at 11:22 AM Changfeng.Zhu  wrote:
>
> From: changzhu 
>
> It may fail to load guest driver in round 2 when using invalidate
> semaphore for SRIOV. So it needs to avoid using invalidate semaphore
> for SRIOV.
>
> Change-Id: I2719671cf86a1755b05c5f2ac7420a901abbe916
> Signed-off-by: changzhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 32 +++---
>  1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 381bb709f021..fd6e3b3b8084 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -218,6 +218,24 @@ static uint32_t gmc_v10_0_get_invalidate_req(unsigned 
> int vmid,
> return req;
>  }
>
> +/**
> + * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
> + *
> + * @adev: amdgpu_device pointer
> + * @vmhub: vmhub type
> + *
> + */
> +static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> +  uint32_t vmhub)
> +{
> +   if ((vmhub == AMDGPU_MMHUB_0 ||
> +vmhub == AMDGPU_MMHUB_1) &&
> +   (!amdgpu_sriov_vf(adev)))
> +   return true;
> +   else
> +   return false;
> +}
> +
>  /*
>   * GART
>   * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -233,6 +251,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
> *adev, uint32_t vmid,
> /* Use register 17 for GART */
> const unsigned eng = 17;
> unsigned int i;
> +   bool value = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);

Call this use_semaphore or something like that rather than value.
Same comment to the instances below as well.  With that fixed,
Reviewed-by: Alex Deucher 

>
> spin_lock(>gmc.invalidate_lock);
> /*
> @@ -243,8 +262,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
> *adev, uint32_t vmid,
>  */
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if (vmhub == AMDGPU_MMHUB_0 ||
> -   vmhub == AMDGPU_MMHUB_1) {
> +   if (value) {
> for (i = 0; i < adev->usec_timeout; i++) {
> /* a read return value of 1 means semaphore acuqire */
> tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
> @@ -277,8 +295,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
> *adev, uint32_t vmid,
> }
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if (vmhub == AMDGPU_MMHUB_0 ||
> -   vmhub == AMDGPU_MMHUB_1)
> +   if (value)
> /*
>  * add semaphore release after invalidation,
>  * write with 0 means semaphore release
> @@ -372,6 +389,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
> amdgpu_ring *ring,
> struct amdgpu_vmhub *hub = >adev->vmhub[ring->funcs->vmhub];
> uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
> unsigned eng = ring->vm_inv_eng;
> +   bool value = gmc_v10_0_use_invalidate_semaphore(ring->adev, 
> ring->funcs->vmhub);
>
> /*
>  * It may lose gpuvm invalidate acknowldege state across power-gating
> @@ -381,8 +399,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
> amdgpu_ring *ring,
>  */
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> -   ring->funcs->vmhub == AMDGPU_MMHUB_1)
> +   if (value)
> /* a read return value of 1 means semaphore acuqire */
> amdgpu_ring_emit_reg_wait(ring,
>   hub->vm_inv_eng0_sem + eng, 0x1, 
> 0x1);
> @@ -398,8 +415,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
> amdgpu_ring *ring,
> req, 1 << vmid);
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> -   ring->funcs->vmhub == AMDGPU_MMHUB_1)
> +   if (value)
> /*
>  * add semaphore release after invalidation,
>  * write with 0 means semaphore release
> --
> 2.17.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/2] drm/amdgpu: modify invalidate semaphore limit in gmc9

[Alex Deucher]

On Tue, Dec 10, 2019 at 11:21 AM Changfeng.Zhu  wrote:
>
> From: changzhu 
>
> It may fail to load guest driver in round 2 or cause Xstart problem
> when using invalidate semaphore for SRIOV or picasso. So it needs avoid
> using invalidate semaphore for SRIOV and picasso.
>
> Change-Id: I806f8e99ec97be84e6aed0f5c499a53b1931b490
> Signed-off-by: changzhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 47 +++
>  1 file changed, 27 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 601667246a1c..552fd7f3fec4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -412,6 +412,27 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int 
> vmid,
> return req;
>  }
>
> +/**
> + * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
> + *
> + * @adev: amdgpu_device pointer
> + * @vmhub: vmhub type
> + *
> + */
> +static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> +  uint32_t vmhub)
> +{
> +   if ((vmhub == AMDGPU_MMHUB_0 ||
> +vmhub == AMDGPU_MMHUB_1) &&
> +   (!amdgpu_sriov_vf(adev)) &&
> +   (!(adev->asic_type == CHIP_RAVEN &&
> +  adev->rev_id < 0x8 &&
> +  adev->pdev->device == 0x15d8)))
> +   return true;
> +   else
> +   return false;
> +}
> +
>  /*
>   * GART
>   * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -434,6 +455,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
> *adev, uint32_t vmid,
> const unsigned eng = 17;
> u32 j, tmp;
> struct amdgpu_vmhub *hub;
> +   bool value = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);

Call this use_semaphore or something like that rather than value.
Same comment to the instances below as well.  With that fixed,
Reviewed-by: Alex Deucher 

>
> BUG_ON(vmhub >= adev->num_vmhubs);
>
> @@ -464,11 +486,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
> *adev, uint32_t vmid,
>  */
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if ((vmhub == AMDGPU_MMHUB_0 ||
> -vmhub == AMDGPU_MMHUB_1) &&
> -   (!(adev->asic_type == CHIP_RAVEN &&
> -  adev->rev_id < 0x8 &&
> -  adev->pdev->device == 0x15d8))) {
> +   if (value) {
> for (j = 0; j < adev->usec_timeout; j++) {
> /* a read return value of 1 means semaphore acuqire */
> tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
> @@ -498,11 +516,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
> *adev, uint32_t vmid,
> }
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if ((vmhub == AMDGPU_MMHUB_0 ||
> -vmhub == AMDGPU_MMHUB_1) &&
> -   (!(adev->asic_type == CHIP_RAVEN &&
> -  adev->rev_id < 0x8 &&
> -  adev->pdev->device == 0x15d8)))
> +   if (value)
> /*
>  * add semaphore release after invalidation,
>  * write with 0 means semaphore release
> @@ -524,6 +538,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
> amdgpu_ring *ring,
> struct amdgpu_vmhub *hub = >vmhub[ring->funcs->vmhub];
> uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
> unsigned eng = ring->vm_inv_eng;
> +   bool value = gmc_v9_0_use_invalidate_semaphore(ring->adev, 
> ring->funcs->vmhub);
>
> /*
>  * It may lose gpuvm invalidate acknowldege state across power-gating
> @@ -533,11 +548,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
> amdgpu_ring *ring,
>  */
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> -ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> -   (!(adev->asic_type == CHIP_RAVEN &&
> -  adev->rev_id < 0x8 &&
> -  adev->pdev->device == 0x15d8)))
> +   if (value)
> /* a read return value of 1 means semaphore acuqire */
> amdgpu_ring_emit_reg_wait(ring,
>   hub->vm_inv_eng0_sem + eng, 0x1, 
> 0x1);
> @@ -553,11 +564,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
> amdgpu_ring *ring,
> req, 1 << vmid);
>
> /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> -   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> -ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> -   (!(adev->asic_type == CHIP_RAVEN &&
> -  adev->rev_id < 0x8 &&
> -  adev->pdev->device == 0x15d8)))

[PATCH 2/2] drm/amdgpu: modify invalidate semaphore limit in gmc10

[Changfeng.Zhu]

From: changzhu 

It may fail to load guest driver in round 2 when using invalidate
semaphore for SRIOV. So it needs to avoid using invalidate semaphore
for SRIOV.

Change-Id: I2719671cf86a1755b05c5f2ac7420a901abbe916
Signed-off-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 32 +++---
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 381bb709f021..fd6e3b3b8084 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -218,6 +218,24 @@ static uint32_t gmc_v10_0_get_invalidate_req(unsigned int 
vmid,
return req;
 }
 
+/**
+ * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
+ *
+ * @adev: amdgpu_device pointer
+ * @vmhub: vmhub type
+ *
+ */
+static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
+  uint32_t vmhub)
+{
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
+   return true;
+   else
+   return false;
+}
+
 /*
  * GART
  * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -233,6 +251,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
/* Use register 17 for GART */
const unsigned eng = 17;
unsigned int i;
+   bool value = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
 
spin_lock(>gmc.invalidate_lock);
/*
@@ -243,8 +262,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if (value) {
for (i = 0; i < adev->usec_timeout; i++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -277,8 +295,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
}
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1)
+   if (value)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -372,6 +389,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
struct amdgpu_vmhub *hub = >adev->vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
unsigned eng = ring->vm_inv_eng;
+   bool value = gmc_v10_0_use_invalidate_semaphore(ring->adev, 
ring->funcs->vmhub);
 
/*
 * It may lose gpuvm invalidate acknowldege state across power-gating
@@ -381,8 +399,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if (value)
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -398,8 +415,7 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if (value)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
-- 
2.17.1

___
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[PATCH 1/2] drm/amdgpu: modify invalidate semaphore limit in gmc9

[Changfeng.Zhu]

From: changzhu 

It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.

Change-Id: I806f8e99ec97be84e6aed0f5c499a53b1931b490
Signed-off-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 47 +++
 1 file changed, 27 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 601667246a1c..552fd7f3fec4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -412,6 +412,27 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int 
vmid,
return req;
 }
 
+/**
+ * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
+ *
+ * @adev: amdgpu_device pointer
+ * @vmhub: vmhub type
+ *
+ */
+static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
+  uint32_t vmhub)
+{
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
+   return true;
+   else
+   return false;
+}
+
 /*
  * GART
  * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -434,6 +455,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
const unsigned eng = 17;
u32 j, tmp;
struct amdgpu_vmhub *hub;
+   bool value = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 
BUG_ON(vmhub >= adev->num_vmhubs);
 
@@ -464,11 +486,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8))) {
+   if (value) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -498,11 +516,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
}
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (value)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -524,6 +538,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
struct amdgpu_vmhub *hub = >vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
unsigned eng = ring->vm_inv_eng;
+   bool value = gmc_v9_0_use_invalidate_semaphore(ring->adev, 
ring->funcs->vmhub);
 
/*
 * It may lose gpuvm invalidate acknowldege state across power-gating
@@ -533,11 +548,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (value)
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -553,11 +564,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (value)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
-- 
2.17.1

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[PATCH 1/4] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
 
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
 
-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}
 
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 19ffe00d9072..2b6e35893918 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1957,11 +1957,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)
 
if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
 
ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e324bfe6c58f..a1a110f5513d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;
 
ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

[PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Nirmoy Das]

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c
index f9b6ce29c58f..a5f729f421f8 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -67,17 +67,10 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
entity->guilty = guilty;
entity->num_sched_list = num_sched_list;
entity->priority = priority;
-   entity->sched_list =  kcalloc(num_sched_list,
- sizeof(struct drm_gpu_scheduler *), 
GFP_KERNEL);
+   entity->sched_list =  sched_list;
 
-   if(!entity->sched_list)
-   return -ENOMEM;
 
init_completion(>entity_idle);
-
-   for (i = 0; i < num_sched_list; i++)
-   entity->sched_list[i] = sched_list[i];
-
if (num_sched_list)
entity->rq = >sched_list[0]->sched_rq[entity->priority];
 
@@ -312,7 +305,6 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
 
dma_fence_put(entity->last_scheduled);
entity->last_scheduled = NULL;
-   kfree(entity->sched_list);
 }
 EXPORT_SYMBOL(drm_sched_entity_fini);
 
-- 
2.24.0

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[PATCH 2/4] drm/amdgpu: replace vm_pte's run-queue list with drm gpu scheds list

[Nirmoy Das]

drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 ++--
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  5 ++---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/si_dma.c|  8 +++-
 9 files changed, 24 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f85007382093..cf4953c4e2cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2779,7 +2779,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->mman.buffer_funcs = NULL;
adev->mman.buffer_funcs_ring = NULL;
adev->vm_manager.vm_pte_funcs = NULL;
-   adev->vm_manager.vm_pte_num_rqs = 0;
+   adev->vm_manager.vm_pte_num_scheds = 0;
adev->gmc.gmc_funcs = NULL;
adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5e78db30c722..0e1ed8ef2ce7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2687,7 +2687,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 {
struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
int r, i;
 
vm->va = RB_ROOT_CACHED;
@@ -2701,19 +2700,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
spin_lock_init(>invalidated_lock);
INIT_LIST_HEAD(>freed);
 
-   for (i = 0; i < adev->vm_manager.vm_pte_num_rqs; i++)
-   sched_list[i] = adev->vm_manager.vm_pte_rqs[i]->sched;
 
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(>direct, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
return r;
 
r = drm_sched_entity_init(>delayed, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
goto error_free_direct;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 76fcf853035c..5eaba8645a43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -322,8 +322,8 @@ struct amdgpu_vm_manager {
u64 vram_base_offset;
/* vm pte handling */
const struct amdgpu_vm_pte_funcs*vm_pte_funcs;
-   struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
-   unsignedvm_pte_num_rqs;
+   struct drm_gpu_scheduler
*vm_pte_scheds[AMDGPU_MAX_RINGS];
+   unsignedvm_pte_num_scheds;
struct amdgpu_ring  *page_fault;
 
/* partial resident texture handling */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 82cdb8f57bfd..1f22a8d0f7f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1373,16 +1373,14 @@ static const struct amdgpu_vm_pte_funcs 
cik_sdma_vm_pte_funcs = {
 
 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
-   struct drm_gpu_scheduler *sched;
unsigned i;
 
adev->vm_manager.vm_pte_funcs = _sdma_vm_pte_funcs;
for (i = 0; i < adev->sdma.num_instances; i++) {
-   sched = >sdma.instance[i].ring.sched;
-   adev->vm_manager.vm_pte_rqs[i] =
-   >sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+   adev->vm_manager.vm_pte_scheds[i] =
+   >sdma.instance[i].ring.sched;
}
-   adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+   adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
 }
 
 const struct 

[PATCH 3/4 v2] amd/amdgpu: add sched array to IPs with multiple run-queues

[Nirmoy Das]

This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h|   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   9 +-
 7 files changed, 89 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1d6850af9908..165d1a397266 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
   struct amdgpu_ctx *ctx)
 {
unsigned num_entities = amdgpu_ctx_total_num_entities();
-   unsigned i, j, k;
+   unsigned i, j;
int r;

if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;

for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-   struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-   unsigned num_rings = 0;
-   unsigned num_rqs = 0;
+   struct drm_gpu_scheduler **scheds;
+   struct drm_gpu_scheduler *sched;
+   unsigned num_scheds = 0;

switch (i) {
case AMDGPU_HW_IP_GFX:
-   rings[0] = >gfx.gfx_ring[0];
-   num_rings = 1;
+   scheds = adev->gfx.gfx_sched;
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
-   for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-   rings[j] = >gfx.compute_ring[j];
-   num_rings = adev->gfx.num_compute_rings;
+   scheds = adev->gfx.compute_sched;
+   num_scheds = adev->gfx.num_compute_sched;
break;
case AMDGPU_HW_IP_DMA:
-   for (j = 0; j < adev->sdma.num_instances; ++j)
-   rings[j] = >sdma.instance[j].ring;
-   num_rings = adev->sdma.num_instances;
+   scheds = adev->sdma.sdma_sched;
+   num_scheds = adev->sdma.num_sdma_sched;
break;
case AMDGPU_HW_IP_UVD:
-   rings[0] = >uvd.inst[0].ring;
-   num_rings = 1;
+   sched = >uvd.inst[0].ring.sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCE:
-   rings[0] = >vce.ring[0];
-   num_rings = 1;
+   sched = >vce.ring[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
-   rings[0] = >uvd.inst[0].ring_enc[0];
-   num_rings = 1;
+   sched = >uvd.inst[0].ring_enc[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCN_DEC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   rings[num_rings++] = 
>vcn.inst[j].ring_dec;
-   }
+   scheds = adev->vcn.vcn_dec_sched;
+   num_scheds =  adev->vcn.num_vcn_dec_sched;
break;
case AMDGPU_HW_IP_VCN_ENC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-   rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];
-   }
+   scheds = adev->vcn.vcn_enc_sched;
+   num_scheds =  adev->vcn.num_vcn_enc_sched;
break;
case AMDGPU_HW_IP_VCN_JPEG:
-   for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-  

Re: [PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Nirmoy]

I think amdgpu_ctx_init() should check for num_scheds and not call 
drm_sched_entity_init()


if its zero.

On 12/10/19 3:47 PM, Nirmoy wrote:


On 12/10/19 2:00 PM, Christian König wrote:

Am 10.12.19 um 13:53 schrieb Nirmoy Das:

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
  1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c

index f9b6ce29c58f..a5f729f421f8 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -67,17 +67,10 @@ int drm_sched_entity_init(struct 
drm_sched_entity *entity,

  entity->guilty = guilty;
  entity->num_sched_list = num_sched_list;
  entity->priority = priority;
-    entity->sched_list =  kcalloc(num_sched_list,
-  sizeof(struct drm_gpu_scheduler *), GFP_KERNEL);
+    entity->sched_list =  sched_list;


Maybe make this "num_sched_list > 1 ? sched_list : NULL" to avoid 
accidentally dereferencing a stale pointer to the stack.

Do you mean "num_sched_list >= 1 ? sched_list : NULL"



  -    if(!entity->sched_list)
-    return -ENOMEM;
    init_completion(>entity_idle);
-
-    for (i = 0; i < num_sched_list; i++)
-    entity->sched_list[i] = sched_list[i];
-
  if (num_sched_list)


That check can actually be dropped as well. We return -EINVAL when 
the num_sched_list is zero.


This  one took me some time to understand. So we don't really return 
-EINVAL if num_sched_list == 0


if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
    return -EINVAL;

This is coming from below patch. Are we suppose to tolerate IPs with 
uninitialized sched so that ctx creation dosn't return error ?


commit 1decbf6bb0b4dc56c9da6c5e57b994ebfc2be3aa
Author: Bas Nieuwenhuizen 
Date:   Wed Jan 30 02:53:19 2019 +0100

    drm/sched: Fix entities with 0 rqs.

    Some blocks in amdgpu can have 0 rqs.

    Job creation already fails with -ENOENT when entity->rq is NULL,
    so jobs cannot be pushed. Without a rq there is no scheduler to
    pop jobs, and rq selection already does the right thing with a
    list of length 0.

    So the operations we need to fix are:
  - Creation, do not set rq to rq_list[0] if the list can have 
length 0.

  - Do not flush any jobs when there is no rq.
  - On entity destruction handle the rq = NULL case.
  - on set_priority, do not try to change the rq if it is NULL.



Regards,
Christian.

  entity->rq = 
>sched_list[0]->sched_rq[entity->priority];
  @@ -312,7 +305,6 @@ void drm_sched_entity_fini(struct 
drm_sched_entity *entity)

    dma_fence_put(entity->last_scheduled);
  entity->last_scheduled = NULL;
-    kfree(entity->sched_list);
  }
  EXPORT_SYMBOL(drm_sched_entity_fini);



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Re: [PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Nirmoy]

On 12/10/19 2:00 PM, Christian König wrote:

Am 10.12.19 um 13:53 schrieb Nirmoy Das:

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
  1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c

index f9b6ce29c58f..a5f729f421f8 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -67,17 +67,10 @@ int drm_sched_entity_init(struct drm_sched_entity 
*entity,

  entity->guilty = guilty;
  entity->num_sched_list = num_sched_list;
  entity->priority = priority;
-    entity->sched_list =  kcalloc(num_sched_list,
-  sizeof(struct drm_gpu_scheduler *), GFP_KERNEL);
+    entity->sched_list =  sched_list;


Maybe make this "num_sched_list > 1 ? sched_list : NULL" to avoid 
accidentally dereferencing a stale pointer to the stack.

Do you mean "num_sched_list >= 1 ? sched_list : NULL"



  -    if(!entity->sched_list)
-    return -ENOMEM;
    init_completion(>entity_idle);
-
-    for (i = 0; i < num_sched_list; i++)
-    entity->sched_list[i] = sched_list[i];
-
  if (num_sched_list)


That check can actually be dropped as well. We return -EINVAL when the 
num_sched_list is zero.


This  one took me some time to understand. So we don't really return 
-EINVAL if num_sched_list == 0


if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
    return -EINVAL;

This is coming from below patch. Are we suppose to tolerate IPs with 
uninitialized sched so that ctx creation dosn't return error ?


commit 1decbf6bb0b4dc56c9da6c5e57b994ebfc2be3aa
Author: Bas Nieuwenhuizen 
Date:   Wed Jan 30 02:53:19 2019 +0100

    drm/sched: Fix entities with 0 rqs.

    Some blocks in amdgpu can have 0 rqs.

    Job creation already fails with -ENOENT when entity->rq is NULL,
    so jobs cannot be pushed. Without a rq there is no scheduler to
    pop jobs, and rq selection already does the right thing with a
    list of length 0.

    So the operations we need to fix are:
  - Creation, do not set rq to rq_list[0] if the list can have 
length 0.

  - Do not flush any jobs when there is no rq.
  - On entity destruction handle the rq = NULL case.
  - on set_priority, do not try to change the rq if it is NULL.



Regards,
Christian.

  entity->rq = 
>sched_list[0]->sched_rq[entity->priority];
  @@ -312,7 +305,6 @@ void drm_sched_entity_fini(struct 
drm_sched_entity *entity)

    dma_fence_put(entity->last_scheduled);
  entity->last_scheduled = NULL;
-    kfree(entity->sched_list);
  }
  EXPORT_SYMBOL(drm_sched_entity_fini);



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Re: [PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Christian König]

Am 10.12.19 um 14:00 schrieb Christian König:

Am 10.12.19 um 13:53 schrieb Nirmoy Das:

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
  1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c

index f9b6ce29c58f..a5f729f421f8 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -67,17 +67,10 @@ int drm_sched_entity_init(struct drm_sched_entity 
*entity,

  entity->guilty = guilty;
  entity->num_sched_list = num_sched_list;
  entity->priority = priority;
-    entity->sched_list =  kcalloc(num_sched_list,
-  sizeof(struct drm_gpu_scheduler *), GFP_KERNEL);
+    entity->sched_list =  sched_list;


Maybe make this "num_sched_list > 1 ? sched_list : NULL" to avoid 
accidentally dereferencing a stale pointer to the stack.



  -    if(!entity->sched_list)
-    return -ENOMEM;
    init_completion(>entity_idle);
-
-    for (i = 0; i < num_sched_list; i++)
-    entity->sched_list[i] = sched_list[i];
-
  if (num_sched_list)


That check can actually be dropped as well. We return -EINVAL when the 
num_sched_list is zero.


Regards,
Christian.

  entity->rq = 
>sched_list[0]->sched_rq[entity->priority];


Forgot to note that this should then probably use 
"sched_list[0]->sched_rq[entity->priority]" directly when we change the 
assignment above.


Christian.

  @@ -312,7 +305,6 @@ void drm_sched_entity_fini(struct 
drm_sched_entity *entity)

    dma_fence_put(entity->last_scheduled);
  entity->last_scheduled = NULL;
-    kfree(entity->sched_list);
  }
  EXPORT_SYMBOL(drm_sched_entity_fini);


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Re: [PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Christian König]

Am 10.12.19 um 13:53 schrieb Nirmoy Das:

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
  1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c
index f9b6ce29c58f..a5f729f421f8 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -67,17 +67,10 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
entity->guilty = guilty;
entity->num_sched_list = num_sched_list;
entity->priority = priority;
-   entity->sched_list =  kcalloc(num_sched_list,
- sizeof(struct drm_gpu_scheduler *), 
GFP_KERNEL);
+   entity->sched_list =  sched_list;


Maybe make this "num_sched_list > 1 ? sched_list : NULL" to avoid 
accidentally dereferencing a stale pointer to the stack.


  
-	if(!entity->sched_list)

-   return -ENOMEM;
  
  	init_completion(>entity_idle);

-
-   for (i = 0; i < num_sched_list; i++)
-   entity->sched_list[i] = sched_list[i];
-
if (num_sched_list)


That check can actually be dropped as well. We return -EINVAL when the 
num_sched_list is zero.


Regards,
Christian.


entity->rq = >sched_list[0]->sched_rq[entity->priority];
  
@@ -312,7 +305,6 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
  
  	dma_fence_put(entity->last_scheduled);

entity->last_scheduled = NULL;
-   kfree(entity->sched_list);
  }
  EXPORT_SYMBOL(drm_sched_entity_fini);
  


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Re: [PATCH 3/4 v2] amd/amdgpu: add sched array to IPs with multiple run-queues

[Christian König]

Am 10.12.19 um 13:52 schrieb Nirmoy Das:

This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.

Signed-off-by: Nirmoy Das 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h|   3 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   9 +-
  7 files changed, 89 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1d6850af9908..165d1a397266 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
   struct amdgpu_ctx *ctx)
  {
unsigned num_entities = amdgpu_ctx_total_num_entities();
-   unsigned i, j, k;
+   unsigned i, j;
int r;

if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;

for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-   struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-   unsigned num_rings = 0;
-   unsigned num_rqs = 0;
+   struct drm_gpu_scheduler **scheds;
+   struct drm_gpu_scheduler *sched;
+   unsigned num_scheds = 0;

switch (i) {
case AMDGPU_HW_IP_GFX:
-   rings[0] = >gfx.gfx_ring[0];
-   num_rings = 1;
+   scheds = adev->gfx.gfx_sched;
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
-   for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-   rings[j] = >gfx.compute_ring[j];
-   num_rings = adev->gfx.num_compute_rings;
+   scheds = adev->gfx.compute_sched;
+   num_scheds = adev->gfx.num_compute_sched;
break;
case AMDGPU_HW_IP_DMA:
-   for (j = 0; j < adev->sdma.num_instances; ++j)
-   rings[j] = >sdma.instance[j].ring;
-   num_rings = adev->sdma.num_instances;
+   scheds = adev->sdma.sdma_sched;
+   num_scheds = adev->sdma.num_sdma_sched;
break;
case AMDGPU_HW_IP_UVD:
-   rings[0] = >uvd.inst[0].ring;
-   num_rings = 1;
+   sched = >uvd.inst[0].ring.sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCE:
-   rings[0] = >vce.ring[0];
-   num_rings = 1;
+   sched = >vce.ring[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
-   rings[0] = >uvd.inst[0].ring_enc[0];
-   num_rings = 1;
+   sched = >uvd.inst[0].ring_enc[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCN_DEC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   rings[num_rings++] = 
>vcn.inst[j].ring_dec;
-   }
+   scheds = adev->vcn.vcn_dec_sched;
+   num_scheds =  adev->vcn.num_vcn_dec_sched;
break;
case AMDGPU_HW_IP_VCN_ENC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-   rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];
-   }
+   scheds = adev->vcn.vcn_enc_sched;
+   num_scheds =  adev->vcn.num_vcn_enc_sched;
break;
case AMDGPU_HW_IP_VCN_JPEG:
-   for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-   if 

Re: [PATCH 3/4] amd/amdgpu: add sched list to IPs with multiple run-queues

[Christian König]

Yeah, but you are to fast for me. I was still looking into comments for 
patch #4 :)


Christian.

Am 10.12.19 um 13:55 schrieb Nirmoy:

Thanks Christian. That make sense, resent modified patches.

On 12/10/19 12:28 PM, Christian König wrote:

Am 09.12.19 um 22:53 schrieb Nirmoy Das:

This sched list can be passed on to entity creation routine
instead of manually creating such sched list on every context creation.


Please drop the "_list" from the names here. A list usually means a 
linked list and those are actually arrays.


Additional to that amdgpu_device_init_sched_list() should probably go 
into amdgpu_ctx.c instead. That is actually not really device 
related, but more UAPI/ctx stuff.


Apart from that looks good to me,
Christian.



Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c    | 69 
--

  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h    |  4 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |  2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |  2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h    |  9 ++-
  6 files changed, 85 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

index 1d6850af9908..c1fc75299b7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device 
*adev,

 struct amdgpu_ctx *ctx)
  {
  unsigned num_entities = amdgpu_ctx_total_num_entities();
-    unsigned i, j, k;
+    unsigned i, j;
  int r;
    if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct 
amdgpu_device *adev,

  ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
    for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-    struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-    struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-    unsigned num_rings = 0;
-    unsigned num_rqs = 0;
+    struct drm_gpu_scheduler **sched_list;
+    struct drm_gpu_scheduler *sched;
+    unsigned num_scheds = 0;
    switch (i) {
  case AMDGPU_HW_IP_GFX:
-    rings[0] = >gfx.gfx_ring[0];
-    num_rings = 1;
+    sched_list = adev->gfx.gfx_sched_list;
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_COMPUTE:
-    for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-    rings[j] = >gfx.compute_ring[j];
-    num_rings = adev->gfx.num_compute_rings;
+    sched_list = adev->gfx.compute_sched_list;
+    num_scheds = adev->gfx.num_compute_rings;
  break;
  case AMDGPU_HW_IP_DMA:
-    for (j = 0; j < adev->sdma.num_instances; ++j)
-    rings[j] = >sdma.instance[j].ring;
-    num_rings = adev->sdma.num_instances;
+    sched_list = adev->sdma.sdma_sched_list;
+    num_scheds = adev->sdma.num_instances;
  break;
  case AMDGPU_HW_IP_UVD:
-    rings[0] = >uvd.inst[0].ring;
-    num_rings = 1;
+    sched = >uvd.inst[0].ring.sched;
+    sched_list = 
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_VCE:
-    rings[0] = >vce.ring[0];
-    num_rings = 1;
+    sched = >vce.ring[0].sched;
+    sched_list = 
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_UVD_ENC:
-    rings[0] = >uvd.inst[0].ring_enc[0];
-    num_rings = 1;
+    sched = >uvd.inst[0].ring_enc[0].sched;
+    sched_list = 
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_VCN_DEC:
-    for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-    if (adev->vcn.harvest_config & (1 << j))
-    continue;
-    rings[num_rings++] = >vcn.inst[j].ring_dec;
-    }
+    sched_list = adev->vcn.vcn_dec_sched_list;
+    num_scheds = adev->vcn.num_vcn_dec_sched_list;
  break;
  case AMDGPU_HW_IP_VCN_ENC:
-    for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-    if (adev->vcn.harvest_config & (1 << j))
-    continue;
-    for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-    rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];

-    }
+    sched_list = adev->vcn.vcn_enc_sched_list;
+    num_scheds = adev->vcn.num_vcn_enc_sched_list;
  break;
  case AMDGPU_HW_IP_VCN_JPEG:
-    for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-    if (adev->vcn.harvest_config & (1 << j))
-    continue;
-    rings[num_rings++] = >jpeg.inst[j].ring_dec;
-    }
+    sched_list = adev->jpeg.jpeg_sched_list;
+    

Re: [PATCH 3/4] amd/amdgpu: add sched list to IPs with multiple run-queues

[Nirmoy]

Thanks Christian. That make sense, resent modified patches.

On 12/10/19 12:28 PM, Christian König wrote:

Am 09.12.19 um 22:53 schrieb Nirmoy Das:

This sched list can be passed on to entity creation routine
instead of manually creating such sched list on every context creation.


Please drop the "_list" from the names here. A list usually means a 
linked list and those are actually arrays.


Additional to that amdgpu_device_init_sched_list() should probably go 
into amdgpu_ctx.c instead. That is actually not really device related, 
but more UAPI/ctx stuff.


Apart from that looks good to me,
Christian.



Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c    | 69 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h    |  4 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |  2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |  2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h    |  9 ++-
  6 files changed, 85 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

index 1d6850af9908..c1fc75299b7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 struct amdgpu_ctx *ctx)
  {
  unsigned num_entities = amdgpu_ctx_total_num_entities();
-    unsigned i, j, k;
+    unsigned i, j;
  int r;
    if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device 
*adev,

  ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
    for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-    struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-    struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-    unsigned num_rings = 0;
-    unsigned num_rqs = 0;
+    struct drm_gpu_scheduler **sched_list;
+    struct drm_gpu_scheduler *sched;
+    unsigned num_scheds = 0;
    switch (i) {
  case AMDGPU_HW_IP_GFX:
-    rings[0] = >gfx.gfx_ring[0];
-    num_rings = 1;
+    sched_list = adev->gfx.gfx_sched_list;
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_COMPUTE:
-    for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-    rings[j] = >gfx.compute_ring[j];
-    num_rings = adev->gfx.num_compute_rings;
+    sched_list = adev->gfx.compute_sched_list;
+    num_scheds = adev->gfx.num_compute_rings;
  break;
  case AMDGPU_HW_IP_DMA:
-    for (j = 0; j < adev->sdma.num_instances; ++j)
-    rings[j] = >sdma.instance[j].ring;
-    num_rings = adev->sdma.num_instances;
+    sched_list = adev->sdma.sdma_sched_list;
+    num_scheds = adev->sdma.num_instances;
  break;
  case AMDGPU_HW_IP_UVD:
-    rings[0] = >uvd.inst[0].ring;
-    num_rings = 1;
+    sched = >uvd.inst[0].ring.sched;
+    sched_list = 
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_VCE:
-    rings[0] = >vce.ring[0];
-    num_rings = 1;
+    sched = >vce.ring[0].sched;
+    sched_list = 
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_UVD_ENC:
-    rings[0] = >uvd.inst[0].ring_enc[0];
-    num_rings = 1;
+    sched = >uvd.inst[0].ring_enc[0].sched;
+    sched_list = 
+    num_scheds = 1;
  break;
  case AMDGPU_HW_IP_VCN_DEC:
-    for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-    if (adev->vcn.harvest_config & (1 << j))
-    continue;
-    rings[num_rings++] = >vcn.inst[j].ring_dec;
-    }
+    sched_list = adev->vcn.vcn_dec_sched_list;
+    num_scheds =  adev->vcn.num_vcn_dec_sched_list;
  break;
  case AMDGPU_HW_IP_VCN_ENC:
-    for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-    if (adev->vcn.harvest_config & (1 << j))
-    continue;
-    for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-    rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];

-    }
+    sched_list = adev->vcn.vcn_enc_sched_list;
+    num_scheds =  adev->vcn.num_vcn_enc_sched_list;
  break;
  case AMDGPU_HW_IP_VCN_JPEG:
-    for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-    if (adev->vcn.harvest_config & (1 << j))
-    continue;
-    rings[num_rings++] = >jpeg.inst[j].ring_dec;
-    }
+    sched_list = adev->jpeg.jpeg_sched_list;
+    num_scheds =  adev->jpeg.num_jpeg_sched_list;
  break;
  }
  -    for (j = 0; j < num_rings; ++j) {
-    if 

Re: [PATCH 3/4] amd/amdgpu: add sched list to IPs with multiple run-queues

[Christian König]

Am 09.12.19 um 22:53 schrieb Nirmoy Das:

This sched list can be passed on to entity creation routine
instead of manually creating such sched list on every context creation.


Please drop the "_list" from the names here. A list usually means a 
linked list and those are actually arrays.


Additional to that amdgpu_device_init_sched_list() should probably go 
into amdgpu_ctx.c instead. That is actually not really device related, 
but more UAPI/ctx stuff.


Apart from that looks good to me,
Christian.



Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 69 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|  4 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |  2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |  2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|  9 ++-
  6 files changed, 85 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1d6850af9908..c1fc75299b7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
   struct amdgpu_ctx *ctx)
  {
unsigned num_entities = amdgpu_ctx_total_num_entities();
-   unsigned i, j, k;
+   unsigned i, j;
int r;
  
  	if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)

@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
  
  	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

-   struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-   unsigned num_rings = 0;
-   unsigned num_rqs = 0;
+   struct drm_gpu_scheduler **sched_list;
+   struct drm_gpu_scheduler *sched;
+   unsigned num_scheds = 0;
  
  		switch (i) {

case AMDGPU_HW_IP_GFX:
-   rings[0] = >gfx.gfx_ring[0];
-   num_rings = 1;
+   sched_list = adev->gfx.gfx_sched_list;
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
-   for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-   rings[j] = >gfx.compute_ring[j];
-   num_rings = adev->gfx.num_compute_rings;
+   sched_list = adev->gfx.compute_sched_list;
+   num_scheds = adev->gfx.num_compute_rings;
break;
case AMDGPU_HW_IP_DMA:
-   for (j = 0; j < adev->sdma.num_instances; ++j)
-   rings[j] = >sdma.instance[j].ring;
-   num_rings = adev->sdma.num_instances;
+   sched_list = adev->sdma.sdma_sched_list;
+   num_scheds = adev->sdma.num_instances;
break;
case AMDGPU_HW_IP_UVD:
-   rings[0] = >uvd.inst[0].ring;
-   num_rings = 1;
+   sched = >uvd.inst[0].ring.sched;
+   sched_list = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCE:
-   rings[0] = >vce.ring[0];
-   num_rings = 1;
+   sched = >vce.ring[0].sched;
+   sched_list = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
-   rings[0] = >uvd.inst[0].ring_enc[0];
-   num_rings = 1;
+   sched = >uvd.inst[0].ring_enc[0].sched;
+   sched_list = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCN_DEC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   rings[num_rings++] = 
>vcn.inst[j].ring_dec;
-   }
+   sched_list = adev->vcn.vcn_dec_sched_list;
+   num_scheds =  adev->vcn.num_vcn_dec_sched_list;
break;
case AMDGPU_HW_IP_VCN_ENC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-   rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];
-   }
+   

Re: [PATCH] drm/amdgpu: avoid using invalidate semaphore for picasso(v2)

[Christian König]

Am 10.12.19 um 12:03 schrieb Zhu, Changfeng:

[AMD Official Use Only - Internal Distribution Only]

OK, Chris.

What's about SRIOV?

Should we skip using semaphore registers for SRIOV now?

I add REG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM, i, 0x0);
in mmhub_v1_0_program_invalidation.

However, the problem still happens.


Sorry totally missed that reply. Do we have an idea of the root cause?

I mean we should probably commit a workaround, but investigate what's 
going on here.


Regards,
Christian.



BR,
Changfeng,

-Original Message-
From: Koenig, Christian 
Sent: Tuesday, December 10, 2019 6:55 PM
To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org; Huang, Ray 
; Huang, Shimmer ; Deucher, Alexander 

Subject: Re: [PATCH] drm/amdgpu: avoid using invalidate semaphore for 
picasso(v2)

Am 10.12.19 um 03:55 schrieb Changfeng.Zhu:

From: changzhu 

It may cause timeout waiting for sem acquire in VM flush when using
invalidate semaphore for picasso. So it needs to avoid using
invalidate semaphore for piasso.

It would probably be better to add a small helper function to decide if the 
semaphore registers should be used or not.

E.g. something like "bool gmc_v9_0_use_semaphore(adev, vmhub...)"

Apart from that looks good to me,
Christian.


Change-Id: I6dc552bde180919cd5ba6c81c6d9e3f800043b03
Signed-off-by: changzhu 
---
   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 +++
   1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 231ea9762cb5..601667246a1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -464,8 +464,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 */
   
   	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8))) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); @@ 
-495,8
+498,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 
uint32_t vmid,
}
   
   	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1)
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release @@ -527,8 +533,11 @@
static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 */
   
   	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 
0x1); @@ -544,8 +553,11 @@
static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
req, 1 << vmid);
   
   	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release


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RE: [PATCH] drm/amdgpu: avoid using invalidate semaphore for picasso(v2)

[Zhu, Changfeng]

[AMD Official Use Only - Internal Distribution Only]

OK, Chris.

What's about SRIOV?

Should we skip using semaphore registers for SRIOV now?

I add REG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM, i, 0x0);
in mmhub_v1_0_program_invalidation.

However, the problem still happens.

BR,
Changfeng,

-Original Message-
From: Koenig, Christian  
Sent: Tuesday, December 10, 2019 6:55 PM
To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org; 
Huang, Ray ; Huang, Shimmer ; Deucher, 
Alexander 
Subject: Re: [PATCH] drm/amdgpu: avoid using invalidate semaphore for 
picasso(v2)

Am 10.12.19 um 03:55 schrieb Changfeng.Zhu:
> From: changzhu 
>
> It may cause timeout waiting for sem acquire in VM flush when using 
> invalidate semaphore for picasso. So it needs to avoid using 
> invalidate semaphore for piasso.

It would probably be better to add a small helper function to decide if the 
semaphore registers should be used or not.

E.g. something like "bool gmc_v9_0_use_semaphore(adev, vmhub...)"

Apart from that looks good to me,
Christian.

>
> Change-Id: I6dc552bde180919cd5ba6c81c6d9e3f800043b03
> Signed-off-by: changzhu 
> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 +++
>   1 file changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 231ea9762cb5..601667246a1c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -464,8 +464,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
> *adev, uint32_t vmid,
>*/
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (vmhub == AMDGPU_MMHUB_0 ||
> - vmhub == AMDGPU_MMHUB_1) {
> + if ((vmhub == AMDGPU_MMHUB_0 ||
> +  vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8))) {
>   for (j = 0; j < adev->usec_timeout; j++) {
>   /* a read return value of 1 means semaphore acuqire */
>   tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); @@ 
> -495,8 
> +498,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 
> uint32_t vmid,
>   }
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (vmhub == AMDGPU_MMHUB_0 ||
> - vmhub == AMDGPU_MMHUB_1)
> + if ((vmhub == AMDGPU_MMHUB_0 ||
> +  vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8)))
>   /*
>* add semaphore release after invalidation,
>* write with 0 means semaphore release @@ -527,8 +533,11 @@ 
> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>*/
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> - ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> +  ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8)))
>   /* a read return value of 1 means semaphore acuqire */
>   amdgpu_ring_emit_reg_wait(ring,
> hub->vm_inv_eng0_sem + eng, 0x1, 
> 0x1); @@ -544,8 +553,11 @@ 
> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>   req, 1 << vmid);
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> - ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> +  ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8)))
>   /*
>* add semaphore release after invalidation,
>* write with 0 means semaphore release
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Re: [PATCH] drm/amdgpu: avoid using invalidate semaphore for picasso(v2)

[Christian König]

Am 10.12.19 um 03:55 schrieb Changfeng.Zhu:

From: changzhu 

It may cause timeout waiting for sem acquire in VM flush when using
invalidate semaphore for picasso. So it needs to avoid using invalidate
semaphore for piasso.


It would probably be better to add a small helper function to decide if 
the semaphore registers should be used or not.


E.g. something like "bool gmc_v9_0_use_semaphore(adev, vmhub...)"

Apart from that looks good to me,
Christian.



Change-Id: I6dc552bde180919cd5ba6c81c6d9e3f800043b03
Signed-off-by: changzhu 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 +++
  1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 231ea9762cb5..601667246a1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -464,8 +464,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8))) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -495,8 +498,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
}
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1)
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -527,8 +533,11 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -544,8 +553,11 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release


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[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Yintian Tao]

Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 235 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 --
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 162 
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 -
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 16 files changed, 406 insertions(+), 302 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9ca7e728d3e..465156a12d88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2819,7 +2819,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3040,9 +3039,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3187,8 +3183,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3669,6 +3663,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3686,7 +3681,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, 
false) * 10;
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, 
false) * 10;
-   } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
-