RE: [PATCH] drm/amdgpu fix incorrect sysfs remove behavior for xgmi
[AMD Official Use Only - Internal Distribution Only]
[AMD Official Use Only - Internal Distribution Only]
+ if (adev != hive->adev) {
+ sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
+ }
Please drop the braces in above code segment. Other than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: amd-gfx On Behalf Of Zhang, Jack
(Jian)
Sent: Wednesday, May 20, 2020 08:14
To: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu fix incorrect sysfs remove behavior for xgmi
[AMD Official Use Only - Internal Distribution Only]
[AMD Official Use Only - Internal Distribution Only]
ping
Outlook for
Android
From: Jack Zhang mailto:jack.zha...@amd.com>>
Sent: Monday, May 18, 2020 5:00:53 PM
To: amd-gfx@lists.freedesktop.org
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Zhang, Jack (Jian) mailto:jack.zha...@amd.com>>
Subject: [PATCH] drm/amdgpu fix incorrect sysfs remove behavior for xgmi
Under xgmi setup,some sysfs fail to create for the second time of kmd
driver loading. It's due to sysfs nodes are not removed appropriately
in the last unlod time.
Changes of this patch:
1. remove sysfs for dev_attr_xgmi_error
2. remove sysfs_link adev->dev->kobj with target name.
And it only needs to be removed once for a xgmi setup
3. remove sysfs_link hive->kobj with target name
In amdgpu_xgmi_remove_device:
1. amdgpu_xgmi_sysfs_rem_dev_info needs to be run per device
2. amdgpu_xgmi_sysfs_destroy needs to be run on the last node of
device.
v2: initialize array with memset
Signed-off-by: Jack Zhang mailto:jack.zha...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index e9e59bc..3b46ea8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -325,9 +325,19 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct
amdgpu_device *adev,
static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
struct amdgpu_hive_info *hive)
{
+ char node[10];
+ memset(node, 0, sizeof(node));
+
device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
- sysfs_remove_link(&adev->dev->kobj, adev->ddev->unique);
- sysfs_remove_link(hive->kobj, adev->ddev->unique);
+ device_remove_file(adev->dev, &dev_attr_xgmi_error);
+
+ if (adev != hive->adev) {
+ sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
+ }
+
+ sprintf(node, "node%d", hive->number_devices);
+ sysfs_remove_link(hive->kobj, node);
+
}
@@ -583,14 +593,14 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
if (!hive)
return -EINVAL;
- if (!(hive->number_devices--)) {
+ task_barrier_rem_task(&hive->tb);
+ amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
+ mutex_unlock(&hive->hive_lock);
+
+ if(!(--hive->number_devices)){
amdgpu_xgmi_sysfs_destroy(adev, hive);
mutex_destroy(&hive->hive_lock);
mutex_destroy(&hive->reset_lock);
- } else {
- task_barrier_rem_task(&hive->tb);
- amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
- mutex_unlock(&hive->hive_lock);
}
return psp_xgmi_terminate(&adev->psp);
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven
[Problem description]
1. Boot up picasso platform, launches desktop, Don't do anything (APU enter
into "gfxoff" state)
2. Remote login to platform using SSH, then type the command line:
sudo su -c "echo manual >
/sys/class/drm/card0/device/power_dpm_force_performance_level"
sudo su -c "echo 2 > /sys/class/drm/card0/device/pp_dpm_sclk" (fix SCLK
to 1400MHz)
3. Move the mouse around in Window
4. Phenomenon : The screen frozen
Tester will switch sclk level during glmark2 run time.
APU will enter "gfxoff" state intermittently during glmark2 run time.
The system got hanged if fix GFXCLK to 1400MHz when APU is in "gfxoff"
state.
[Debug]
1. Fix SCLK to X MHz
1400: screen frozen, screen black, then OS will reboot.
1300: screen frozen.
1200: screen frozen, screen black.
1100: screen frozen, screen black, then OS will reboot.
1000: screen frozen, screen black.
900: screen frozen, screen black, then OS will reboot.
800: Situation Nomal, issue disappear.
700: Situation Nomal, issue disappear.
2. SBIOS setting: AMD CBS --> SMU Debug Options -->SMU Debug --> "GFX DLDO Psm
Margin Control":
50 : Situation Nomal, issue disappear.
45 : Situation Nomal, issue disappear.
40 : Situation Nomal, issue disappear.
35 : Situation Nomal, issue disappear.
30 : screen black.
25 : screen frozen, then blurred screen.
20 : screen frozen.
15 : screen black.
10 : screen frozen.
5 : screen frozen, then blurred screen.
3. Disable GFXOFF feature
Situation Nomal, issue disappear.
[Why]
Through a period of time debugging with Sys Eng team and SMU team, Sys
Eng team said this is voltage/frequency marginal issue not a F/W or H/W
bug. This experiment proves that default targetPsm [for f=1400MHz] is
not sufficient when GFXOFF is enabled on Picasso.
SMU team think it is an odd test conditions to force sclk="1400MHz" when
GPU is in "gfxoff" state，then wake up the GFX. SCLK should be in the
"lowest frequency" when gfxoff.
[How]
Disable gfxoff when setting manual mode.
Enable gfxoff when setting other mode(exiting manual mode) again.
By the way, from the user point of view, now that user switch to manual
mode and force SCLK Frequency, he don't want SCLK be controlled by
workload.It becomes meaningless to "switch to manual mode" if APU enter "gfxoff"
due to lack of workload at this point.
Tips: Same issue observed on Raven.
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 17bc7f5..d45394c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -371,6 +371,15 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
return count;
}
+ if(adev->asic_type == CHIP_RAVEN){
+ if (adev->rev_id < 8){
+ if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
level == AMD_DPM_FORCED_LEVEL_MANUAL)
+ amdgpu_gfx_off_ctrl(adev, false);
+ else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL
&& level != AMD_DPM_FORCED_LEVEL_MANUAL)
+ amdgpu_gfx_off_ctrl(adev, true);
+ }
+ }
+
/* profile_exit setting is valid only when current mode is in profile
mode */
if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: change memory training to common function
From: Likun Gao
Change memory training init and finit a common function, as it only have
software behavior do not relay on the IP version of PSP.
Signed-off-by: Likun Gao
Change-Id: I0a81d3c3cd1813480781876101e9bfb6787bce3b
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 42 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 6
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 40 ---
3 files changed, 40 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7301fdcfb8bc..679d96719410 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -115,6 +115,44 @@ static int psp_early_init(void *handle)
return 0;
}
+static void psp_memory_training_fini(struct psp_context *psp)
+{
+ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
+
+ ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
+ kfree(ctx->sys_cache);
+ ctx->sys_cache = NULL;
+}
+
+static int psp_memory_training_init(struct psp_context *psp)
+{
+ int ret;
+ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
+
+ if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
+ DRM_DEBUG("memory training is not supported!\n");
+ return 0;
+ }
+
+ ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
+ if (ctx->sys_cache == NULL) {
+ DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
+ ret = -ENOMEM;
+ goto Err_out;
+ }
+
+
DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
+ ctx->train_data_size,
+ ctx->p2c_train_data_offset,
+ ctx->c2p_train_data_offset);
+ ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
+ return 0;
+
+Err_out:
+ psp_memory_training_fini(psp);
+ return ret;
+}
+
static int psp_sw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -127,7 +165,7 @@ static int psp_sw_init(void *handle)
return ret;
}
- ret = psp_mem_training_init(psp);
+ ret = psp_memory_training_init(psp);
if (ret) {
DRM_ERROR("Failed to initialize memory training!\n");
return ret;
@@ -152,7 +190,7 @@ static int psp_sw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- psp_mem_training_fini(&adev->psp);
+ psp_memory_training_fini(&adev->psp);
release_firmware(adev->psp.sos_fw);
adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 2a56ad996d83..e19b98d48c98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -95,8 +95,6 @@ struct psp_funcs
enum psp_ring_type ring_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
int (*mode1_reset)(struct psp_context *psp);
- int (*mem_training_init)(struct psp_context *psp);
- void (*mem_training_fini)(struct psp_context *psp);
int (*mem_training)(struct psp_context *psp, uint32_t ops);
uint32_t (*ring_get_wptr)(struct psp_context *psp);
void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
@@ -306,10 +304,6 @@ struct amdgpu_psp_funcs {
((psp)->funcs->smu_reload_quirk ?
(psp)->funcs->smu_reload_quirk((psp)) : false)
#define psp_mode1_reset(psp) \
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) :
false)
-#define psp_mem_training_init(psp) \
- ((psp)->funcs->mem_training_init ?
(psp)->funcs->mem_training_init((psp)) : 0)
-#define psp_mem_training_fini(psp) \
- ((psp)->funcs->mem_training_fini ?
(psp)->funcs->mem_training_fini((psp)) : 0)
#define psp_mem_training(psp, ops) \
((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops))
: 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1de89cc3c355..9ec6e3819dff 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -555,44 +555,6 @@ static int psp_v11_0_memory_training_send_msg(struct
psp_context *psp, int msg)
return ret;
}
-static void psp_v11_0_memory_training_fini(struct psp_context *psp)
-{
- struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
-
- ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
- kfree(ctx->sys_cache);
- ctx->sys_cache = NULL;
-}
-
-static int psp_v11_0_memory_training_init(struct psp_context *psp)
-{
- int ret;
- struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
-
- if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
- DRM_DEBUG("memory train
RE: [PATCH] drm/amdgpu: change memory training to common function
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Likun Gao
Sent: Thursday, May 21, 2020 19:10
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: [PATCH] drm/amdgpu: change memory training to common function
From: Likun Gao
Change memory training init and finit a common function, as it only have
software behavior do not relay on the IP version of PSP.
Signed-off-by: Likun Gao
Change-Id: I0a81d3c3cd1813480781876101e9bfb6787bce3b
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 42 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 6
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 40 ---
3 files changed, 40 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7301fdcfb8bc..679d96719410 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -115,6 +115,44 @@ static int psp_early_init(void *handle)
return 0;
}
+static void psp_memory_training_fini(struct psp_context *psp) {
+ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
+
+ ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
+ kfree(ctx->sys_cache);
+ ctx->sys_cache = NULL;
+}
+
+static int psp_memory_training_init(struct psp_context *psp) {
+ int ret;
+ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
+
+ if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
+ DRM_DEBUG("memory training is not supported!\n");
+ return 0;
+ }
+
+ ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
+ if (ctx->sys_cache == NULL) {
+ DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
+ ret = -ENOMEM;
+ goto Err_out;
+ }
+
+
DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
+ ctx->train_data_size,
+ ctx->p2c_train_data_offset,
+ ctx->c2p_train_data_offset);
+ ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
+ return 0;
+
+Err_out:
+ psp_memory_training_fini(psp);
+ return ret;
+}
+
static int psp_sw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -127,7
+165,7 @@ static int psp_sw_init(void *handle)
return ret;
}
- ret = psp_mem_training_init(psp);
+ ret = psp_memory_training_init(psp);
if (ret) {
DRM_ERROR("Failed to initialize memory training!\n");
return ret;
@@ -152,7 +190,7 @@ static int psp_sw_fini(void *handle) {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- psp_mem_training_fini(&adev->psp);
+ psp_memory_training_fini(&adev->psp);
release_firmware(adev->psp.sos_fw);
adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 2a56ad996d83..e19b98d48c98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -95,8 +95,6 @@ struct psp_funcs
enum psp_ring_type ring_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
int (*mode1_reset)(struct psp_context *psp);
- int (*mem_training_init)(struct psp_context *psp);
- void (*mem_training_fini)(struct psp_context *psp);
int (*mem_training)(struct psp_context *psp, uint32_t ops);
uint32_t (*ring_get_wptr)(struct psp_context *psp);
void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); @@
-306,10 +304,6 @@ struct amdgpu_psp_funcs {
((psp)->funcs->smu_reload_quirk ?
(psp)->funcs->smu_reload_quirk((psp)) : false) #define psp_mode1_reset(psp) \
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) :
false) -#define psp_mem_training_init(psp) \
- ((psp)->funcs->mem_training_init ?
(psp)->funcs->mem_training_init((psp)) : 0)
-#define psp_mem_training_fini(psp) \
- ((psp)->funcs->mem_training_fini ?
(psp)->funcs->mem_training_fini((psp)) : 0)
#define psp_mem_training(psp, ops) \
((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops))
: 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1de89cc3c355..9ec6e3819dff 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -555,44 +555,6 @@ static int psp_v11_0_memory_training_send_msg(struct
psp_context *psp, int msg)
return ret;
}
-static void psp_v11_0_memory_training_fini(struct psp_context *psp) -{
- struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
-
- ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
Re: [PATCH] drm/amd/amdkfd: Fix large framesize for kfd_smi_ev_read()
On 05/20, Felix Kuehling wrote: > Am 2020-05-20 um 9:53 a.m. schrieb Aurabindo Pillai: > > The buffer allocated is of 1024 bytes. Allocate this from > > heap instead of stack. > > > > Also remove check for stack size since we're allocating from heap > > > > Signed-off-by: Aurabindo Pillai > > Tested-by: Amber Lin > > See one comment inline. With that fixed, the patch is > > Reviewed-by: Felix Kuehling > > > > --- > > drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 26 +++-- > > 1 file changed, 19 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c > > b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c > > index f5fd18eacf0d..5aebe169f8c6 100644 > > --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c > > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c > > @@ -77,9 +77,11 @@ static ssize_t kfd_smi_ev_read(struct file *filep, char > > __user *user, > > int ret; > > size_t to_copy; > > struct kfd_smi_client *client = filep->private_data; > > - unsigned char buf[MAX_KFIFO_SIZE]; > > + unsigned char *buf; > > > > - BUILD_BUG_ON(MAX_KFIFO_SIZE > 1024); > > + buf = kzalloc(MAX_KFIFO_SIZE * sizeof(*buf), GFP_KERNEL); > > kzalloc is not necessary here, you could use kmalloc. The part of that > allocation that matters will be overwritten by kfifo_out. > > Regards, > Felix > > Thank you Felix, Alex for the review. I shall make that change and submit it. Thanks & Regards, Aurabindo signature.asc Description: PGP signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v1 13/25] dma-buf: Use sequence counter with associated wound/wait mutex
Am 21.05.20 um 02:09 schrieb Ahmed S. Darwish: On Wed, May 20, 2020, Christian König wrote: Am 19.05.20 um 23:45 schrieb Ahmed S. Darwish: A sequence counter write side critical section must be protected by some form of locking to serialize writers. If the serialization primitive is not disabling preemption implicitly, preemption has to be explicitly disabled before entering the sequence counter write side critical section. The dma-buf reservation subsystem uses plain sequence counters to manage updates to reservations. Writer serialization is accomplished through a wound/wait mutex. Acquiring a wound/wait mutex does not disable preemption, so this needs to be done manually before and after the write side critical section. Use the newly-added seqcount_ww_mutex_t instead: - It associates the ww_mutex with the sequence count, which enables lockdep to validate that the write side critical section is properly serialized. - It removes the need to explicitly add preempt_disable/enable() around the write side critical section because the write_begin/end() functions for this new data type automatically do this. If lockdep is disabled this ww_mutex lock association is compiled out and has neither storage size nor runtime overhead. Mhm, is the dma_resv object the only user of this new seqcount_ww_mutex variant ? If yes we are trying to get rid of this sequence counter for quite some time, so I would rather invest the additional time to finish this. In this patch series, each extra "seqcount with associated lock" data type costs us, exactly: - 1 typedef definition, seqcount_ww_mutex_t - 1 static initializer, SEQCNT_WW_MUTEX_ZERO() - 1 runtime initializer, seqcount_ww_mutex_init() Definitions for the typedef and the 2 initializers above are template-code one liners. In this case I'm perfectly fine with this. The logic which automatically disables preemption upon entering a seqcount_ww_mutex_t write side critical section is also already shared with seqcount_mutex_t and any future, preemptible, associated lock. So, yes, dma-resv is the only user of seqcount_ww_mutex. But even in that case, given the one liner template code nature of seqcount_ww_mutex_t logic, it does not make sense to block the dma_resv and amdgpu change until at some point in the future the sequence counter is completely removed. **If and when** the sequence counter gets removed, please just remove the seqcount_ww_mutex_t data type with it. It will be extremely simple. Completely agree, just wanted to prevent that we now add a lot of code which gets removed again ~3 month from now. Regards, Christian. Regards, Christian. Thanks, -- Ahmed S. Darwish Linutronix GmbH ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/1] drm/amdgpu: Sync with VM root BO when switching VM to CPU update mode
Am 21.05.20 um 00:51 schrieb Felix Kuehling:
This fixes an intermittent bug where a root PD clear operation still in
progress could overwrite a PDE update done by the CPU, resulting in a
VM fault.
Mhm, maybe better add this to amdgpu_vm_cpu_prepare().
This way we could (in theory) switch between CPU and SDMA based updates
on the fly elsewhere as well.
Christian.
Fixes: 108b4d928c03 ("drm/amd/amdgpu: Update VM function pointer")
Reported-by: Jay Cornwall
Tested-by: Jay Cornwall
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 414a0b1c2e5a..7417754e9141 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3000,10 +3000,17 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
!amdgpu_gmc_vram_full_visible(&adev->gmc)),
"CPU update of VM recommended only for large BAR system\n");
- if (vm->use_cpu_for_update)
+ if (vm->use_cpu_for_update) {
+ /* Sync with last SDMA update/clear before switching to CPU */
+ r = amdgpu_bo_sync_wait(vm->root.base.bo,
+ AMDGPU_FENCE_OWNER_UNDEFINED, true);
+ if (r)
+ goto free_idr;
+
vm->update_funcs = &amdgpu_vm_cpu_funcs;
- else
+ } else {
vm->update_funcs = &amdgpu_vm_sdma_funcs;
+ }
dma_fence_put(vm->last_update);
vm->last_update = NULL;
vm->is_compute_context = true;
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: simplify ATIF backlight handling
Ping?
On Tue, May 12, 2020 at 4:15 PM Alex Deucher wrote:
>
> Ping?
>
> Alex
>
> On Thu, May 7, 2020 at 12:09 PM Alex Deucher wrote:
> >
> > Ping?
> >
> > On Tue, May 5, 2020 at 3:48 PM Alex Deucher wrote:
> > >
> > > Just register the a pointer to the backlight device and use
> > > that. Unifies the DC and non-DC handling.
> > >
> > > Signed-off-by: Alex Deucher
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 73 ++--
> > > 1 file changed, 30 insertions(+), 43 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > index 956cbbda4793..913c8f0513bd 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > @@ -64,7 +64,9 @@ struct amdgpu_atif {
> > > struct amdgpu_atif_notifications notifications;
> > > struct amdgpu_atif_functions functions;
> > > struct amdgpu_atif_notification_cfg notification_cfg;
> > > - struct amdgpu_encoder *encoder_for_bl;
> > > +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||
> > > defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
> > > + struct backlight_device *bd;
> > > +#endif
> > > struct amdgpu_dm_backlight_caps backlight_caps;
> > > };
> > >
> > > @@ -444,45 +446,21 @@ static int amdgpu_atif_handler(struct amdgpu_device
> > > *adev,
> > >
> > > DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n",
> > > count);
> > >
> > > - if ((req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST)
> > > &&
> > > - !amdgpu_device_has_dc_support(adev)) {
> > > - struct amdgpu_encoder *enc = atif->encoder_for_bl;
> > > -
> > > - if (enc) {
> > > - struct amdgpu_encoder_atom_dig *dig =
> > > enc->enc_priv;
> > > -
> > > - DRM_DEBUG_DRIVER("Changing brightness to
> > > %d\n",
> > > -req.backlight_level);
> > > -
> > > - amdgpu_display_backlight_set_level(adev,
> > > enc, req.backlight_level);
> > > -
> > > -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||
> > > defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
> > > - backlight_force_update(dig->bl_dev,
> > > -
> > > BACKLIGHT_UPDATE_HOTKEY);
> > > -#endif
> > > - }
> > > - }
> > > -#if defined(CONFIG_DRM_AMD_DC)
> > > + if (req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) {
> > > #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||
> > > defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
> > > - if ((req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST)
> > > &&
> > > - amdgpu_device_has_dc_support(adev)) {
> > > - struct amdgpu_display_manager *dm = &adev->dm;
> > > - struct backlight_device *bd = dm->backlight_dev;
> > > -
> > > - if (bd) {
> > > + if (atif->bd) {
> > > DRM_DEBUG_DRIVER("Changing brightness to
> > > %d\n",
> > > req.backlight_level);
> > > -
> > > /*
> > > * XXX backlight_device_set_brightness()
> > > is
> > > * hardwired to post
> > > BACKLIGHT_UPDATE_SYSFS.
> > > * It probably should accept 'reason'
> > > parameter.
> > > */
> > > - backlight_device_set_brightness(bd,
> > > req.backlight_level);
> > > + backlight_device_set_brightness(atif->bd,
> > > req.backlight_level);
> > > }
> > > - }
> > > -#endif
> > > #endif
> > > + }
> > > +
> > > if (req.pending & ATIF_DGPU_DISPLAY_EVENT) {
> > > if (adev->flags & AMD_IS_PX) {
> > > pm_runtime_get_sync(adev->ddev->dev);
> > > @@ -829,23 +807,32 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
> > > adev->atif = atif;
> > >
> > > if (atif->notifications.brightness_change) {
> > > - struct drm_encoder *tmp;
> > > -
> > > - /* Find the encoder controlling the brightness */
> > > - list_for_each_entry(tmp,
> > > &adev->ddev->mode_config.encoder_list,
> > > - head) {
> > > - struct amdgpu_encoder *enc =
> > > to_amdgpu_encoder(tmp);
> > > -
> > > - if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
> > > - enc->enc_priv) {
> > > - struct amdgpu_encoder_atom_dig *dig =
> > > enc->enc_priv;
>
[PATCH] drm/amdgpu: fix pp_clk_voltage handling
Fix a typo with pp_clk_voltage that prevented it from
showing up.
Fixes: 4e01847c38f7a5 ("drm/amdgpu: optimize amdgpu device attribute code")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1150
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2fc51f815eaa..88dfc61fa084 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1746,7 +1746,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
attr->states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
- attr->states = ATTR_STATE_UNSUPPORTED;
+ attr->states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED;
--
2.25.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/7] drm/amdgpu/sdma4: add renoir to powergating setup
Ping on this series?
Alex
On Tue, May 19, 2020 at 11:44 AM Alex Deucher wrote:
>
> Looks like renoir should be handled here as well.
>
> Signed-off-by: Alex Deucher
> ---
>
> Can someone test this on renoir?
>
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 9077507b425a..a8cad03b1c42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2203,6 +2203,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
>
> switch (adev->asic_type) {
> case CHIP_RAVEN:
> + case CHIP_RENOIR:
> sdma_v4_1_update_power_gating(adev,
> state == AMD_PG_STATE_GATE ? true : false);
> break;
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/3] drm/amdgpu: move discovery gfx config fetching
Ping on this series? It fixes an ordering issue for raven2.
Alex
On Fri, May 15, 2020 at 2:31 PM Alex Deucher wrote:
>
> Move it into the fw_info function since it's logically part
> of the same functionality.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index cc41e8f5ad14..bab1be7abdf0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1617,8 +1617,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct
> amdgpu_device *adev)
> (const struct gpu_info_firmware_v1_0
> *)(adev->firmware.gpu_info_fw->data +
>
> le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>
> - if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
> + if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
> + amdgpu_discovery_get_gfx_info(adev);
> goto parse_soc_bounding_box;
> + }
>
> adev->gfx.config.max_shader_engines =
> le32_to_cpu(gpu_info_fw->gc_num_se);
> adev->gfx.config.max_cu_per_sh =
> le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
> @@ -1768,9 +1770,6 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> if (r)
> return r;
>
> - if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
> - amdgpu_discovery_get_gfx_info(adev);
> -
> amdgpu_amdkfd_device_probe(adev);
>
> if (amdgpu_sriov_vf(adev)) {
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdkfd: fix restore worker race condition
In free memory of gpu path, remove bo from validate_list to make sure restore worker don't access the BO any more, then unregister bo MMU interval notifier. Otherwise, the restore worker will crash in the middle of validating BO user pages if MMU interval notifer is gone. Signed-off-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index da8b31a53291..68e6e1bc8f3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1302,15 +1302,15 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( return -EBUSY; } - /* No more MMU notifiers */ - amdgpu_mn_unregister(mem->bo); - /* Make sure restore workers don't access the BO any more */ bo_list_entry = &mem->validate_list; mutex_lock(&process_info->lock); list_del(&bo_list_entry->head); mutex_unlock(&process_info->lock); + /* No more MMU notifiers */ + amdgpu_mn_unregister(mem->bo); + ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); if (unlikely(ret)) return ret; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: Flaky brightness on Renoir
[AMD Official Use Only - Internal Distribution Only] Hi Harry, " Michael, does this "fix" your issue?" Yes, the change "fixes" the issue. It has the same effect as removing renoir_dmcu.bin work-around, where backlight control starts to work. Thanks again, Michael -Original Message- From: Wentland, Harry Sent: Wednesday, May 20, 2020 5:53 PM To: Alex Deucher ; Alexander Monakov ; Kazlauskas, Nicholas ; Li, Sun peng (Leo) Cc: amd-gfx list ; Deucher, Alexander ; Chiu, Michael ; Koo, Anthony Subject: Re: Flaky brightness on Renoir We've seen similar problems internally. Michael, does this "fix" your issue? Anthony, looks like smooth_brightness is problematic on (some) renoir systems. Thoughts? Thanks, Harry On 2020-05-20 5:47 p.m., Alex Deucher wrote: > Adding some display people. > > On Wed, May 20, 2020 at 5:46 PM Alexander Monakov wrote: >> >> Hello, >> >> I have a laptop with the recent Renoir SoC. Screen brightness is >> controlled via the amdgpu driver. Unfortunately it doesn't work >> properly: brightness doesn't go below a certain threshold. In one >> experiment I've found the threshold to be about 95 (of 255), which is >> quite high. >> >> There's a bugreport on the tracker from a person with the same laptop >> model as mine that says that the threshold may vary from boot to boot. >> >> So far I was able to find a workaround: avoiding >> dmcu_set_backlight_level like in the patch below gives more reliable >> backlight control (but at the expense of breaking "actual_brightness" >> sysfs file, because it reads from DMCU registers). >> >> What might be the problem and can I help investigate this further? >> Would really like to see this work properly. >> >> Alexander >> >> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c >> b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c >> index b8a3fc505c9b..3274b0d15893 100644 >> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c >> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c >> @@ -428,7 +428,7 @@ static bool dce_abm_set_backlight_level_pwm( >> backlight_pwm_u16_16, backlight_pwm_u16_16); >> >> /* If DMCU is in reset state, DMCU is uninitialized */ >> - if (use_smooth_brightness) >> + if (0 && use_smooth_brightness) >> dmcu_set_backlight_level(abm_dce, >> backlight_pwm_u16_16, >> frame_ramp, >> ___ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdkfd: fix restore worker race condition
Am 2020-05-21 um 10:42 a.m. schrieb Philip Yang: > In free memory of gpu path, remove bo from validate_list to make sure > restore worker don't access the BO any more, then unregister bo MMU > interval notifier. Otherwise, the restore worker will crash in the > middle of validating BO user pages if MMU interval notifer is gone. > > Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > index da8b31a53291..68e6e1bc8f3a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > @@ -1302,15 +1302,15 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( > return -EBUSY; > } > > - /* No more MMU notifiers */ > - amdgpu_mn_unregister(mem->bo); > - > /* Make sure restore workers don't access the BO any more */ > bo_list_entry = &mem->validate_list; > mutex_lock(&process_info->lock); > list_del(&bo_list_entry->head); > mutex_unlock(&process_info->lock); > > + /* No more MMU notifiers */ > + amdgpu_mn_unregister(mem->bo); > + > ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); > if (unlikely(ret)) > return ret; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix pm sysfs node handling (v2)
Fix typos that prevented them from showing up.
v2: switch other files in addition to pp_clk_voltage
Fixes: 4e01847c38f7a5 ("drm/amdgpu: optimize amdgpu device attribute code")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1150
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2fc51f815eaa..e06fef6174e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1731,10 +1731,10 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
#define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name))
if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
- if (asic_type <= CHIP_VEGA10)
+ if (asic_type < CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
- if (asic_type <= CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
+ if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
attr->states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
if (asic_type < CHIP_VEGA20)
@@ -1746,7 +1746,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
attr->states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
- attr->states = ATTR_STATE_UNSUPPORTED;
+ attr->states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED;
@@ -1758,7 +1758,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
if (!adev->unique_id)
attr->states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_features)) {
- if (adev->flags & AMD_IS_APU || asic_type <= CHIP_VEGA10)
+ if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED;
}
--
2.25.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu: drop navi pcie bw callback
Ping on this series?
On Tue, May 19, 2020 at 5:10 PM Alex Deucher wrote:
>
> It's not implemented yet so just drop it so the sysfs
> pcie bw file returns an appropriate error instead of
> garbage.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 9c42316c47c0..6655dd2009b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -548,13 +548,6 @@ static bool nv_need_full_reset(struct amdgpu_device
> *adev)
> return true;
> }
>
> -static void nv_get_pcie_usage(struct amdgpu_device *adev,
> - uint64_t *count0,
> - uint64_t *count1)
> -{
> - /*TODO*/
> -}
> -
> static bool nv_need_reset_on_init(struct amdgpu_device *adev)
> {
> #if 0
> @@ -629,7 +622,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
> .invalidate_hdp = &nv_invalidate_hdp,
> .init_doorbell_index = &nv_init_doorbell_index,
> .need_full_reset = &nv_need_full_reset,
> - .get_pcie_usage = &nv_get_pcie_usage,
> .need_reset_on_init = &nv_need_reset_on_init,
> .get_pcie_replay_count = &nv_get_pcie_replay_count,
> .supports_baco = &nv_asic_supports_baco,
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven
On Thu, May 21, 2020 at 6:43 AM chen gong wrote:
>
> [Problem description]
> 1. Boot up picasso platform, launches desktop, Don't do anything (APU enter
> into "gfxoff" state)
> 2. Remote login to platform using SSH, then type the command line:
> sudo su -c "echo manual >
> /sys/class/drm/card0/device/power_dpm_force_performance_level"
> sudo su -c "echo 2 > /sys/class/drm/card0/device/pp_dpm_sclk" (fix
> SCLK to 1400MHz)
> 3. Move the mouse around in Window
> 4. Phenomenon : The screen frozen
>
> Tester will switch sclk level during glmark2 run time.
> APU will enter "gfxoff" state intermittently during glmark2 run time.
> The system got hanged if fix GFXCLK to 1400MHz when APU is in "gfxoff"
> state.
>
> [Debug]
> 1. Fix SCLK to X MHz
> 1400: screen frozen, screen black, then OS will reboot.
> 1300: screen frozen.
> 1200: screen frozen, screen black.
> 1100: screen frozen, screen black, then OS will reboot.
> 1000: screen frozen, screen black.
> 900: screen frozen, screen black, then OS will reboot.
> 800: Situation Nomal, issue disappear.
> 700: Situation Nomal, issue disappear.
> 2. SBIOS setting: AMD CBS --> SMU Debug Options -->SMU Debug --> "GFX DLDO
> Psm Margin Control":
> 50 : Situation Nomal, issue disappear.
> 45 : Situation Nomal, issue disappear.
> 40 : Situation Nomal, issue disappear.
> 35 : Situation Nomal, issue disappear.
> 30 : screen black.
> 25 : screen frozen, then blurred screen.
> 20 : screen frozen.
> 15 : screen black.
> 10 : screen frozen.
> 5 : screen frozen, then blurred screen.
> 3. Disable GFXOFF feature
> Situation Nomal, issue disappear.
>
> [Why]
> Through a period of time debugging with Sys Eng team and SMU team, Sys
> Eng team said this is voltage/frequency marginal issue not a F/W or H/W
> bug. This experiment proves that default targetPsm [for f=1400MHz] is
> not sufficient when GFXOFF is enabled on Picasso.
>
> SMU team think it is an odd test conditions to force sclk="1400MHz" when
> GPU is in "gfxoff" state，then wake up the GFX. SCLK should be in the
> "lowest frequency" when gfxoff.
>
> [How]
> Disable gfxoff when setting manual mode.
> Enable gfxoff when setting other mode(exiting manual mode) again.
>
> By the way, from the user point of view, now that user switch to manual
> mode and force SCLK Frequency, he don't want SCLK be controlled by
> workload.It becomes meaningless to "switch to manual mode" if APU enter
> "gfxoff"
> due to lack of workload at this point.
>
> Tips: Same issue observed on Raven.
>
> Signed-off-by: chen gong
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 17bc7f5..d45394c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -371,6 +371,15 @@ static ssize_t
> amdgpu_set_power_dpm_force_performance_level(struct device *dev,
> return count;
> }
>
> + if(adev->asic_type == CHIP_RAVEN){
missing spaces around (). I.e., should be:
+ if (adev->asic_type == CHIP_RAVEN) {
> + if (adev->rev_id < 8){
Missing space after ). I.e., should be:
+ if (adev->rev_id < 8) {
With those fixed, patch is:
Reviewed-by: Alex Deucher
> + if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
> level == AMD_DPM_FORCED_LEVEL_MANUAL)
> + amdgpu_gfx_off_ctrl(adev, false);
> + else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL
> && level != AMD_DPM_FORCED_LEVEL_MANUAL)
> + amdgpu_gfx_off_ctrl(adev, true);
> + }
> + }
> +
> /* profile_exit setting is valid only when current mode is in profile
> mode */
> if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/1] drm/amdgpu: Sync with VM root BO when switching VM to CPU update mode
Am 2020-05-21 um 9:50 a.m. schrieb Christian König:
> Am 21.05.20 um 00:51 schrieb Felix Kuehling:
>> This fixes an intermittent bug where a root PD clear operation still in
>> progress could overwrite a PDE update done by the CPU, resulting in a
>> VM fault.
>
> Mhm, maybe better add this to amdgpu_vm_cpu_prepare().
>
> This way we could (in theory) switch between CPU and SDMA based
> updates on the fly elsewhere as well.
That won't work. I want to wait for FENCE_OWNER_VM fences, so I need to
use FENCE_OWNER_UNDEFINED. But then I would also end up waiting for
FENCE_OWNER_KFD eviction fences, which would trigger unwanted evictions.
This works OK in amdgpu_vm_make_compute because it runs before the
eviction fence is attached to the VM.
Regards,
Felix
>
> Christian.
>
>>
>> Fixes: 108b4d928c03 ("drm/amd/amdgpu: Update VM function pointer")
>> Reported-by: Jay Cornwall
>> Tested-by: Jay Cornwall
>> Signed-off-by: Felix Kuehling
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 +--
>> 1 file changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 414a0b1c2e5a..7417754e9141 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -3000,10 +3000,17 @@ int amdgpu_vm_make_compute(struct
>> amdgpu_device *adev, struct amdgpu_vm *vm,
>> !amdgpu_gmc_vram_full_visible(&adev->gmc)),
>> "CPU update of VM recommended only for large BAR system\n");
>> - if (vm->use_cpu_for_update)
>> + if (vm->use_cpu_for_update) {
>> + /* Sync with last SDMA update/clear before switching to CPU */
>> + r = amdgpu_bo_sync_wait(vm->root.base.bo,
>> + AMDGPU_FENCE_OWNER_UNDEFINED, true);
>> + if (r)
>> + goto free_idr;
>> +
>> vm->update_funcs = &amdgpu_vm_cpu_funcs;
>> - else
>> + } else {
>> vm->update_funcs = &amdgpu_vm_sdma_funcs;
>> + }
>> dma_fence_put(vm->last_update);
>> vm->last_update = NULL;
>> vm->is_compute_context = true;
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu: drop navi pcie bw callback
[AMD Official Use Only - Internal Distribution Only]
The series are
Reviewed-by: Yong Zhao
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, May 21, 2020 12:52 PM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 2/2] drm/amdgpu: drop navi pcie bw callback
Ping on this series?
On Tue, May 19, 2020 at 5:10 PM Alex Deucher wrote:
>
> It's not implemented yet so just drop it so the sysfs
> pcie bw file returns an appropriate error instead of
> garbage.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 9c42316c47c0..6655dd2009b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -548,13 +548,6 @@ static bool nv_need_full_reset(struct amdgpu_device
> *adev)
> return true;
> }
>
> -static void nv_get_pcie_usage(struct amdgpu_device *adev,
> - uint64_t *count0,
> - uint64_t *count1)
> -{
> - /*TODO*/
> -}
> -
> static bool nv_need_reset_on_init(struct amdgpu_device *adev)
> {
> #if 0
> @@ -629,7 +622,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
> .invalidate_hdp = &nv_invalidate_hdp,
> .init_doorbell_index = &nv_init_doorbell_index,
> .need_full_reset = &nv_need_full_reset,
> - .get_pcie_usage = &nv_get_pcie_usage,
> .need_reset_on_init = &nv_need_reset_on_init,
> .get_pcie_replay_count = &nv_get_pcie_replay_count,
> .supports_baco = &nv_asic_supports_baco,
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cyong.zhao%40amd.com%7C1a6de00e60b447bad54a08d7fda76316%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256767681371342&sdata=EWwfgYQtOR1TGw6%2BL6w8Cw7Y9e7ixVI1xDJoWTUsWtk%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu: drop navi pcie bw callback
Sorry I missed this.
Series is Reviewed-By: Kent Russell
Kent
KENT RUSSELL
Sr. Software Engineer | Linux Compute Kernel
1 Commerce Valley Drive East
Markham, ON L3T 7X6
O +(1) 289-695-2122 | Ext 72122
From: amd-gfx on behalf of Zhao, Yong
Sent: Thursday, May 21, 2020 1:27 PM
To: Alex Deucher ; amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 2/2] drm/amdgpu: drop navi pcie bw callback
[AMD Official Use Only - Internal Distribution Only]
[AMD Official Use Only - Internal Distribution Only]
The series are
Reviewed-by: Yong Zhao
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, May 21, 2020 12:52 PM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 2/2] drm/amdgpu: drop navi pcie bw callback
Ping on this series?
On Tue, May 19, 2020 at 5:10 PM Alex Deucher wrote:
>
> It's not implemented yet so just drop it so the sysfs
> pcie bw file returns an appropriate error instead of
> garbage.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 9c42316c47c0..6655dd2009b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -548,13 +548,6 @@ static bool nv_need_full_reset(struct amdgpu_device
> *adev)
> return true;
> }
>
> -static void nv_get_pcie_usage(struct amdgpu_device *adev,
> - uint64_t *count0,
> - uint64_t *count1)
> -{
> - /*TODO*/
> -}
> -
> static bool nv_need_reset_on_init(struct amdgpu_device *adev)
> {
> #if 0
> @@ -629,7 +622,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
> .invalidate_hdp = &nv_invalidate_hdp,
> .init_doorbell_index = &nv_init_doorbell_index,
> .need_full_reset = &nv_need_full_reset,
> - .get_pcie_usage = &nv_get_pcie_usage,
> .need_reset_on_init = &nv_need_reset_on_init,
> .get_pcie_replay_count = &nv_get_pcie_replay_count,
> .supports_baco = &nv_asic_supports_baco,
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cyong.zhao%40amd.com%7C1a6de00e60b447bad54a08d7fda76316%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256767681371342&sdata=EWwfgYQtOR1TGw6%2BL6w8Cw7Y9e7ixVI1xDJoWTUsWtk%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: slow rx 5600 xt fps
Alex, yea, youre totally right i was overcomplicating it lol so i was able to get the radeon to run super fast, by doing as you suggested and blacklisting i915. (had to use module_blacklist= though because modprobe.blacklist still allows i915, if a dependency wants to load it) but with one caveat: using the amdgpu driver, there was some error saying something about telling me that i need to add BusID to my device or something. maybe amdgpu wasnt able to find the card or something, i dont remember. so i used modesetting instead and it seemed to work. i will try going back to amdgpu and seeing what that error message was. i recall you saying that modesetting doesnt have some features that amdgpu provides. what are some examples of that? is the direction that graphics drivers are going, to be simply used as "modesetting" via xorg? On Wed, May 20, 2020 at 10:12 PM Alex Deucher wrote: > > I think you are overcomplicating things. Just try and get X running > on just the AMD GPU on bare metal. Introducing virtualization is just > adding more uncertainty. If you can't configure X to not use the > integrated GPU, just blacklist the i915 driver (append > modprobe.blacklist=i915 to the kernel command line in grub) and X > should come up on the dGPU. > > Alex > > On Wed, May 20, 2020 at 6:05 PM Javad Karabi wrote: > > > > Thanks Alex, > > Here's my plan: > > > > since my laptop's os is pretty customized, e.g. compiling my own kernel, > > building latest xorg, latest xorg-driver-amdgpu, etc etc, > > im going to use the intel iommu and pass through my rx 5600 into a virtual > > machine, which will be a 100% stock ubuntu installation. > > then, inside that vm, i will continue to debug > > > > does that sound like it would make sense for testing? for example, with > > that scenario, it adds the iommu into the mix, so who knows if that causes > > performance issues. but i think its worth a shot, to see if a stock kernel > > will handle it better > > > > also, quick question: > > from what i understand, a thunderbolt 3 pci express connection should > > handle 8 GT/s x4, however, along the chain of bridges to my device, i > > notice that the bridge closest to the graphics card is at 2.5 GT/s x4, and > > it also says "downgraded" (this is via the lspci output) > > > > now, when i boot into windows, it _also_ says 2.5 GT/s x4, and it runs > > extremely well. no issues at all. > > > > so my question is: the fact that the bridge is at 2.5 GT/s x4, and not at > > its theoretical "full link speed" of 8 GT/s x4, do you suppose that _could_ > > be an issue? > > i do not think so, because, like i said, in windows it also reports that > > link speed. > > i would assume that you would want the fastest link speed possible, because > > i would assume that of _all_ tb3 pci express devices, a GPU would be the #1 > > most demanding on the link > > > > just curious if you think 2.5 GT/s could be the bottleneck > > > > i will pass through the device into a ubuntu vm and let you know how it > > goes. thanks > > > > > > > > On Tue, May 19, 2020 at 9:29 PM Alex Deucher wrote: > >> > >> On Tue, May 19, 2020 at 9:16 PM Javad Karabi wrote: > >> > > >> > thanks for the answers alex. > >> > > >> > so, i went ahead and got a displayport cable to see if that changes > >> > anything. and now, when i run monitor only, and the monitor connected > >> > to the card, it has no issues like before! so i am thinking that > >> > somethings up with either the hdmi cable, or some hdmi related setting > >> > in my system? who knows, but im just gonna roll with only using > >> > displayport cables now. > >> > the previous hdmi cable was actually pretty long, because i was > >> > extending it with an hdmi extension cable, so maybe the signal was > >> > really bad or something :/ > >> > > >> > but yea, i guess the only real issue now is maybe something simple > >> > related to some sysfs entry about enabling some powermode, voltage, > >> > clock frequency, or something, so that glxgears will give me more than > >> > 300 fps. but atleast now i can use a single monitor configuration with > >> > the monitor displayported up to the card. > >> > > >> > >> The GPU dynamically adjusts the clocks and voltages based on load. No > >> manual configuration is required. > >> > >> At this point, we probably need to see you xorg log and dmesg output > >> to try and figure out exactly what is going on. I still suspect there > >> is some interaction going on with both GPUs and the integrated GPU > >> being the primary, so as I mentioned before, you should try and run X > >> on just the amdgpu rather than trying to use both of them. > >> > >> Alex > >> > >> > >> > also, one other thing i think you might be interested in, that was > >> > happening before. > >> > > >> > so, previously, with laptop -tb3-> egpu-hdmi> monitor, there was a > >> > funny thing happening which i never could figure out. > >> > when i would look at the X logs, i would see that "modesettin
Re: slow rx 5600 xt fps
Please provide your dmesg output and xorg log. Alex On Thu, May 21, 2020 at 3:03 PM Javad Karabi wrote: > > Alex, > yea, youre totally right i was overcomplicating it lol > so i was able to get the radeon to run super fast, by doing as you > suggested and blacklisting i915. > (had to use module_blacklist= though because modprobe.blacklist still > allows i915, if a dependency wants to load it) > but with one caveat: > using the amdgpu driver, there was some error saying something about > telling me that i need to add BusID to my device or something. > maybe amdgpu wasnt able to find the card or something, i dont > remember. so i used modesetting instead and it seemed to work. > i will try going back to amdgpu and seeing what that error message was. > i recall you saying that modesetting doesnt have some features that > amdgpu provides. > what are some examples of that? > is the direction that graphics drivers are going, to be simply used as > "modesetting" via xorg? > > On Wed, May 20, 2020 at 10:12 PM Alex Deucher wrote: > > > > I think you are overcomplicating things. Just try and get X running > > on just the AMD GPU on bare metal. Introducing virtualization is just > > adding more uncertainty. If you can't configure X to not use the > > integrated GPU, just blacklist the i915 driver (append > > modprobe.blacklist=i915 to the kernel command line in grub) and X > > should come up on the dGPU. > > > > Alex > > > > On Wed, May 20, 2020 at 6:05 PM Javad Karabi wrote: > > > > > > Thanks Alex, > > > Here's my plan: > > > > > > since my laptop's os is pretty customized, e.g. compiling my own kernel, > > > building latest xorg, latest xorg-driver-amdgpu, etc etc, > > > im going to use the intel iommu and pass through my rx 5600 into a > > > virtual machine, which will be a 100% stock ubuntu installation. > > > then, inside that vm, i will continue to debug > > > > > > does that sound like it would make sense for testing? for example, with > > > that scenario, it adds the iommu into the mix, so who knows if that > > > causes performance issues. but i think its worth a shot, to see if a > > > stock kernel will handle it better > > > > > > also, quick question: > > > from what i understand, a thunderbolt 3 pci express connection should > > > handle 8 GT/s x4, however, along the chain of bridges to my device, i > > > notice that the bridge closest to the graphics card is at 2.5 GT/s x4, > > > and it also says "downgraded" (this is via the lspci output) > > > > > > now, when i boot into windows, it _also_ says 2.5 GT/s x4, and it runs > > > extremely well. no issues at all. > > > > > > so my question is: the fact that the bridge is at 2.5 GT/s x4, and not at > > > its theoretical "full link speed" of 8 GT/s x4, do you suppose that > > > _could_ be an issue? > > > i do not think so, because, like i said, in windows it also reports that > > > link speed. > > > i would assume that you would want the fastest link speed possible, > > > because i would assume that of _all_ tb3 pci express devices, a GPU would > > > be the #1 most demanding on the link > > > > > > just curious if you think 2.5 GT/s could be the bottleneck > > > > > > i will pass through the device into a ubuntu vm and let you know how it > > > goes. thanks > > > > > > > > > > > > On Tue, May 19, 2020 at 9:29 PM Alex Deucher > > > wrote: > > >> > > >> On Tue, May 19, 2020 at 9:16 PM Javad Karabi > > >> wrote: > > >> > > > >> > thanks for the answers alex. > > >> > > > >> > so, i went ahead and got a displayport cable to see if that changes > > >> > anything. and now, when i run monitor only, and the monitor connected > > >> > to the card, it has no issues like before! so i am thinking that > > >> > somethings up with either the hdmi cable, or some hdmi related setting > > >> > in my system? who knows, but im just gonna roll with only using > > >> > displayport cables now. > > >> > the previous hdmi cable was actually pretty long, because i was > > >> > extending it with an hdmi extension cable, so maybe the signal was > > >> > really bad or something :/ > > >> > > > >> > but yea, i guess the only real issue now is maybe something simple > > >> > related to some sysfs entry about enabling some powermode, voltage, > > >> > clock frequency, or something, so that glxgears will give me more than > > >> > 300 fps. but atleast now i can use a single monitor configuration with > > >> > the monitor displayported up to the card. > > >> > > > >> > > >> The GPU dynamically adjusts the clocks and voltages based on load. No > > >> manual configuration is required. > > >> > > >> At this point, we probably need to see you xorg log and dmesg output > > >> to try and figure out exactly what is going on. I still suspect there > > >> is some interaction going on with both GPUs and the integrated GPU > > >> being the primary, so as I mentioned before, you should try and run X > > >> on just the amdgpu rather than trying to use both of them. > > >> >
[PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should
not program CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
@@ -6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
{
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev,
{
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */
@@ -6953,6 +6962,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
{
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/3] Revert "drm/amdgpu: optimize amdgpu device attribute code"
This reverts commit 3fc62b9b9cfed72fd7acf2f594c9a4930dbc0467.
This breaks multi-GPU. Since the attribute array is global
whatever gets set for the first device more or less ends up
what gets set all the other GPUs in the system.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 494 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 46 ---
2 files changed, 278 insertions(+), 262 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 63e3e6534913..3c8c56d0dbd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -154,9 +154,9 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum
amd_pp_sensors senso
*
*/
-static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_dpm_state(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -189,10 +189,10 @@ static ssize_t amdgpu_get_power_dpm_state(struct device
*dev,
(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" :
"performance");
}
-static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_dpm_state(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -294,9 +294,9 @@ static ssize_t amdgpu_set_power_dpm_state(struct device
*dev,
*
*/
-static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
- struct
device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -332,10 +332,10 @@ static ssize_t
amdgpu_get_power_dpm_force_performance_level(struct device *dev,
"unknown");
}
-static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
- struct
device_attribute *attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
+ struct device_attribute
*attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -873,10 +873,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device
*dev,
* the corresponding bit from original ppfeature masks and input the
* new ppfeature masks.
*/
-static ssize_t amdgpu_set_pp_features(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t count)
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -917,9 +917,9 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
return count;
}
-static ssize_t amdgpu_get_pp_features(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
@@ -1663,9 +1663,9 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct
device *dev,
* The SMU firmware computes a percentage of load based on the
[PATCH 2/3] Revert "drm/amdgpu: cleanup unnecessary virt sriov check in amdgpu attribute"
This reverts commit e04aba8a382d86646a2a2cc194c3fc2441b64917.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 105 +
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 72bbb8175b22..63e3e6534913 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -163,6 +163,9 @@ static ssize_t amdgpu_get_power_dpm_state(struct device
*dev,
enum amd_pm_state_type pm;
int ret;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return 0;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -196,6 +199,9 @@ static ssize_t amdgpu_set_power_dpm_state(struct device
*dev,
enum amd_pm_state_type state;
int ret;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return -EINVAL;
+
if (strncmp("battery", buf, strlen("battery")) == 0)
state = POWER_STATE_TYPE_BATTERY;
else if (strncmp("balanced", buf, strlen("balanced")) == 0)
@@ -297,6 +303,9 @@ static ssize_t
amdgpu_get_power_dpm_force_performance_level(struct device *dev,
enum amd_dpm_forced_level level = 0xff;
int ret;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return 0;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -334,6 +343,9 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return -EINVAL;
+
if (strncmp("low", buf, strlen("low")) == 0) {
level = AMD_DPM_FORCED_LEVEL_LOW;
} else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -463,6 +475,9 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
enum amd_pm_state_type pm = 0;
int i = 0, ret = 0;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return 0;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -499,6 +514,9 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return 0;
+
if (adev->pp_force_state_enabled)
return amdgpu_get_pp_cur_state(dev, attr, buf);
else
@@ -516,6 +534,9 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
unsigned long idx;
int ret;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return -EINVAL;
+
if (strlen(buf) == 1)
adev->pp_force_state_enabled = false;
else if (is_support_sw_smu(adev))
@@ -571,6 +592,9 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
char *table = NULL;
int size, ret;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return 0;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -610,6 +634,9 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
int ret = 0;
+ if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+ return -EINVAL;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -712,6 +739,9 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device
*dev,
const char delimiter[3] = {' ', '\n', '\0'};
uint32_t type;
+ if (amdgpu_sriov_vf(adev))
+ return -EINVAL;
+
if (count > 127)
return -EINVAL;
@@ -801,6 +831,9 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device
*dev,
ssize_t size;
int ret;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -850,6 +883,9 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
uint64_t featuremask;
int ret;
+ if (amdgpu_sriov_vf(adev))
+ return -EINVAL;
+
ret = kstrtou64(buf, 0, &featuremask);
if (ret)
return -EINVAL;
@@ -890,6 +926,9 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
ssize_t size;
int ret;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0)
return ret;
@@ -946,6 +985,9 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct d
[PATCH 1/3] Revert "drm/amdgpu: off by one in amdgpu_device_attr_create_groups() error handling"
This reverts commit b41d9df2b680b96913cc3ccf929252e2dce71b24.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2fc51f815eaa..72bbb8175b22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1843,8 +1843,9 @@ static int amdgpu_device_attr_create_groups(struct
amdgpu_device *adev,
return 0;
failed:
- while (i--)
+ for (; i > 0; i--) {
amdgpu_device_attr_remove(adev, &attrs[i]);
+ }
return ret;
}
--
2.25.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
On Thu, May 21, 2020 at 3:53 PM Gavin Wan wrote:
>
> For SRIOV, since the CGCG is set on host side. The Guest should
> not program CGCG again.
>
> The patch ignores setting CGCG for SRIOV.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..52b6e4759cf3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct
> amdgpu_device *adev)
> static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
>bool enable)
> {
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
> @@ -6842,6 +6845,9 @@ static void
> gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
> {
> uint32_t data, def;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* It is disabled by HW by default */
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
> /* 0 - Disable some blocks' MGCG */
> @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
> amdgpu_device *adev,
> {
> uint32_t data, def;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* Enable 3D CGCG/CGLS */
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> /* write cmd to clear cgcg/cgls ov */
> @@ -6953,6 +6962,9 @@ static void
> gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
> {
> uint32_t def, data;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> /* unset CGCG override */
> @@ -6994,6 +7006,9 @@ static void
> gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
> static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> bool enable)
> {
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> amdgpu_gfx_rlc_enter_safe_mode(adev);
>
> if (enable) {
> --
> 2.25.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdkfd: Track SDMA utilization per process
Hi Mukul,
This looks pretty good. See some suggestions inline.
Am 2020-05-14 um 4:33 p.m. schrieb Mukul Joshi:
> Track SDMA usage on a per process basis and report it through sysfs.
> The value in the sysfs file indicates the amount of time SDMA has
> been in-use by this process since the creation of the process.
> This value is in microsecond granularity.
>
> Signed-off-by: Mukul Joshi
> ---
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 57
> .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 16 ++-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 130 --
> 4 files changed, 193 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index e9c4867abeff..49f72d0f7be7 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -153,6 +153,52 @@ void decrement_queue_count(struct device_queue_manager
> *dqm,
> dqm->active_cp_queue_count--;
> }
>
> +int read_sdma_queue_counter(struct queue *q, uint64_t *val)
> +{
> + int ret;
> + uint64_t tmp = 0;
> +
> + if (!q || !val)
> + return -EINVAL;
> + /*
> + * SDMA activity counter is stored at queue's RPTR + 0x8 location.
> + */
> + if (!access_ok((const void __user *)((uint64_t)q->properties.read_ptr +
> + sizeof(uint64_t)), sizeof(uint64_t))) {
> + pr_err("Can't access sdma queue activity counter\n");
> + return -EFAULT;
> + }
> +
> + ret = get_user(tmp, (uint64_t *)((uint64_t)(q->properties.read_ptr) +
> + sizeof(uint64_t)));
> + if (!ret) {
> + *val = tmp;
> + }
> +
> + return ret;
> +}
> +
> +static int update_sdma_queue_past_activity_stats(struct kfd_process_device
> *pdd,
> + struct queue *q)
> +{
> + int ret;
> + uint64_t val = 0;
> +
> + if (!pdd)
> + return -ENODEV;
> +
> + ret = read_sdma_queue_counter(q, &val);
> + if (ret) {
> + pr_err("Failed to read SDMA queue counter for queue: %d\n",
> + q->properties.queue_id);
> + return ret;
> + }
> +
> + WRITE_ONCE(pdd->sdma_past_activity_counter,
> pdd->sdma_past_activity_counter + val);
> +
> + return ret;
> +}
> +
> static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
> {
> struct kfd_dev *dev = qpd->dqm->dev;
> @@ -487,6 +533,12 @@ static int destroy_queue_nocpsch_locked(struct
> device_queue_manager *dqm,
> if (retval == -ETIME)
> qpd->reset_wavefronts = true;
>
> + /* Get the SDMA queue stats */
> +if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
> +(q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
> +update_sdma_queue_past_activity_stats(qpd_to_pdd(qpd), q);
> +}
> +
> mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
>
> list_del(&q->list);
> @@ -1468,6 +1520,11 @@ static int destroy_queue_cpsch(struct
> device_queue_manager *dqm,
> }
> }
>
> + /* Get the SDMA queue stats */
> + if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
> + (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
> + update_sdma_queue_past_activity_stats(qpd_to_pdd(qpd), q);
> + }
> /*
>* Unconditionally decrement this counter, regardless of the queue's
>* type
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
> index 4afa015c69b1..894bcf877f9e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
> @@ -251,4 +251,6 @@ static inline void dqm_unlock(struct device_queue_manager
> *dqm)
> mutex_unlock(&dqm->lock_hidden);
> }
>
> +int read_sdma_queue_counter(struct queue *q, uint64_t *val);
> +
> #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index f70f789c3cb3..fae139b77c0a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -633,7 +633,14 @@ enum kfd_pdd_bound {
> PDD_BOUND_SUSPENDED,
> };
>
> -#define MAX_VRAM_FILENAME_LEN 11
> +#define MAX_SYSFS_FILENAME_LEN 11
> +
> +/*
> + * SDMA counter runs at 100MHz frequency.
> + * We display SDMA activity in microsecond granularity in sysfs.
> + * As a result, the divisor is 100.
> + */
> +#define SDMA_ACTIVITY_DIVISOR 100
>
> /* Data that is per-process-per device. */
> struct kfd_process_device {
> @@ -681,7 +688,12 @@ struct kfd_process_device {
> /* VRAM usage */
>
[PATCH 2/2] drm/amdgpu: Advise if unable to resize BAR
Even with the "Above 4G decoding" (or similar) BIOS option enabled,
many BIOS do not assign the PCI root bus a 64-bit address space.
If available, "MMIOH Base" and "MMIO High Size" (or similar) BIOS
options should allow mapping to the desired address spaces.
Signed-off-by: Alan Swanson
---
Useful to know why bar resizing isn't happening.
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2f0e8da7b..39a7f7212 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -919,8 +919,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
}
/* Trying to resize is pointless without a root hub window above 4GB */
- if (!res)
+ if (!res) {
+ DRM_INFO("Unable to resize BAR as PCI bus address space below
4GB.");
return 0;
+ }
/* Disable memory decoding while we change the BAR addresses and size */
pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
--
2.26.2
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu: resize VRAM BAR for CPU access on gfx10
Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs
code with previous gfx generations from commit d6895ad39f3b39
("drm/amdgpu: resize VRAM BAR for CPU access v6").
Signed-off-by: Alan Swanson
---
Unfortunately cannot test this with my RX5700 on my AMD X470
motherboard as its BIOS "Above 4G decoding" option does not
remap the PCI root bus. Trying "pci=nocrs" also unsuccessful.
However, I assume it's just absent due to missed commit
overlap during gfx10 bring up and should work.
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index edaa50d85..ba2b7ac0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -686,17 +686,23 @@ static void gmc_v10_0_vram_gtt_location(struct
amdgpu_device *adev,
*/
static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
{
- /* Could aper size report 0 ? */
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+ int r;
/* size in MB on si */
adev->gmc.mc_vram_size =
adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+
+ if (!(adev->flags & AMD_IS_APU)) {
+ r = amdgpu_device_resize_fb_bar(adev);
+ if (r)
+ return r;
+ }
+ adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
/* In case the PCI BAR is larger than the actual amount of vram */
+ adev->gmc.visible_vram_size = adev->gmc.aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
--
2.26.2
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdgpu: resize VRAM BAR for CPU access on gfx10
On Thu, May 21, 2020 at 4:48 PM Alan Swanson wrote:
>
> Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs
> code with previous gfx generations from commit d6895ad39f3b39
> ("drm/amdgpu: resize VRAM BAR for CPU access v6").
>
> Signed-off-by: Alan Swanson
Tested and applied. Thanks!
Alex
> ---
> Unfortunately cannot test this with my RX5700 on my AMD X470
> motherboard as its BIOS "Above 4G decoding" option does not
> remap the PCI root bus. Trying "pci=nocrs" also unsuccessful.
> However, I assume it's just absent due to missed commit
> overlap during gfx10 bring up and should work.
>
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index edaa50d85..ba2b7ac0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -686,17 +686,23 @@ static void gmc_v10_0_vram_gtt_location(struct
> amdgpu_device *adev,
> */
> static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
> {
> - /* Could aper size report 0 ? */
> - adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
> - adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
> + int r;
>
> /* size in MB on si */
> adev->gmc.mc_vram_size =
> adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
> adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
> - adev->gmc.visible_vram_size = adev->gmc.aper_size;
> +
> + if (!(adev->flags & AMD_IS_APU)) {
> + r = amdgpu_device_resize_fb_bar(adev);
> + if (r)
> + return r;
> + }
> + adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
> + adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
>
> /* In case the PCI BAR is larger than the actual amount of vram */
> + adev->gmc.visible_vram_size = adev->gmc.aper_size;
> if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
> adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
>
> --
> 2.26.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu: Advise if unable to resize BAR
On Thu, May 21, 2020 at 4:45 PM Alan Swanson wrote:
>
> Even with the "Above 4G decoding" (or similar) BIOS option enabled,
> many BIOS do not assign the PCI root bus a 64-bit address space.
>
> If available, "MMIOH Base" and "MMIO High Size" (or similar) BIOS
> options should allow mapping to the desired address spaces.
>
> Signed-off-by: Alan Swanson
> ---
> Useful to know why bar resizing isn't happening.
This will spam a lot of people and probably cause confusion. I'd
prefer to drop this one.
Alex
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2f0e8da7b..39a7f7212 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -919,8 +919,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device
> *adev)
> }
>
> /* Trying to resize is pointless without a root hub window above 4GB
> */
> - if (!res)
> + if (!res) {
> + DRM_INFO("Unable to resize BAR as PCI bus address space below
> 4GB.");
> return 0;
> + }
>
> /* Disable memory decoding while we change the BAR addresses and size
> */
> pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
> --
> 2.26.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix sysfs power controls with multi-GPU
Reset the SUPPORTED attribute. Signed-off-by: Alex Deucher --- This fixes multi-GPU, but I think we could still race without some sort of locking around the attr array. drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index e06fef6174e5..4c65444e9ef7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1790,6 +1790,8 @@ static int amdgpu_device_attr_create(struct amdgpu_device *adev, BUG_ON(!attr); + attr->states = ATTR_STATE_SUPPORTED; + attr_update = attr->attr_update ? attr_update : default_attr_update; ret = attr_update(adev, attr, mask); -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: Handle GPU reset for DC block
[Why]
Previously we used the s3 codepath for gpu reset. This can lead to issues in
certain case where we end of waiting for fences which will never come (because
parts of the hw are off due to gpu reset) and we end up waiting forever causing
a deadlock.
[How]
Handle GPU reset separately from normal s3 case. We essentially need to redo
everything we do in s3, but avoid any drm calls.
For GPU reset case
suspend:
-Acquire DC lock
-Cache current dc_state
-Commit 0 stream/planes to dc (this puts dc into a state where it can be
powered off)
-Disable interrupts
resume
-Edit cached state to force full update
-Commit cached state from suspend
-Build stream and plane updates from the cached state
-Commit stream/plane updates
-Enable interrupts
-Release DC lock
v2:
-Formatting
-Release dc_state
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 182 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
2 files changed, 182 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 60fe64aef11b..4110ff8580b7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1521,10 +1521,114 @@ static int dm_hw_fini(void *handle)
return 0;
}
+
+static int dm_enable_vblank(struct drm_crtc *crtc);
+static void dm_disable_vblank(struct drm_crtc *crtc);
+
+static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
+struct dc_state *state, bool enable)
+{
+ enum dc_irq_source irq_source;
+ struct amdgpu_crtc *acrtc;
+ int rc = -EBUSY;
+ int i = 0;
+
+ for (i = 0; i < state->stream_count; i++) {
+ acrtc = get_crtc_by_otg_inst(
+ adev, state->stream_status[i].primary_otg_inst);
+
+ if (acrtc && state->stream_status[i].plane_count != 0) {
+ irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
+ rc = dc_interrupt_set(adev->dm.dc, irq_source, enable)
? 0 : -EBUSY;
+ DRM_DEBUG("crtc %d - vupdate irq %sabling: r=%d\n",
+ acrtc->crtc_id, enable ? "en" : "dis", rc);
+ if (rc)
+ DRM_WARN("Failed to %s pflip interrupts\n",
+enable ? "enable" : "disable");
+
+ if (enable) {
+ rc = dm_enable_vblank(&acrtc->base);
+ if (rc)
+ DRM_WARN("Failed to enable vblank
interrupts\n");
+ } else {
+ dm_disable_vblank(&acrtc->base);
+ }
+
+ }
+ }
+
+}
+
+enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
+{
+ struct dc_state *context = NULL;
+ enum dc_status res = DC_ERROR_UNEXPECTED;
+ int i;
+ struct dc_stream_state *del_streams[MAX_PIPES];
+ int del_streams_count = 0;
+
+ memset(del_streams, 0, sizeof(del_streams));
+
+ context = dc_create_state(dc);
+ if (context == NULL)
+ goto context_alloc_fail;
+
+ dc_resource_state_copy_construct_current(dc, context);
+
+ /* First remove from context all streams */
+ for (i = 0; i < context->stream_count; i++) {
+ struct dc_stream_state *stream = context->streams[i];
+
+ del_streams[del_streams_count++] = stream;
+ }
+
+ /* Remove all planes for removed streams and then remove the streams */
+ for (i = 0; i < del_streams_count; i++) {
+ if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context))
{
+ res = DC_FAIL_DETACH_SURFACES;
+ goto fail;
+ }
+
+ res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
+ if (res != DC_OK)
+ goto fail;
+ }
+
+
+ res = dc_validate_global_state(dc, context, false);
+
+ if (res != DC_OK) {
+ DRM_ERROR("%s:resource validation failed, dc_status:%d\n",
__func__, res);
+ goto fail;
+ }
+
+ res = dc_commit_state(dc, context);
+
+fail:
+ dc_release_state(context);
+
+context_alloc_fail:
+ return res;
+}
+
static int dm_suspend(void *handle)
{
struct amdgpu_device *adev = handle;
struct amdgpu_display_manager *dm = &adev->dm;
+ int ret = 0;
+
+ if (adev->in_gpu_reset) {
+ mutex_lock(&dm->dc_lock);
+ dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
+
+ dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
+
+ amdgpu_dm_
[pull] amdgpu drm-fixes-5.7
Hi Dave, Daniel, Fixes for 5.7. The following changes since commit 5a3f610877e9d08968ea7237551049581f02b163: drm/edid: Add Oculus Rift S to non-desktop list (2020-05-20 12:56:49 +1000) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.7-2020-05-21 for you to fetch changes up to 31ecebee9c36d5e5e113a357a655d993fa916174: drm/amd/display: Defer cursor lock until after VUPDATE (2020-05-20 17:32:13 -0400) amd-drm-fixes-5.7-2020-05-21: amdgpu: - DP fix - Floating point fix - Fix cursor stutter issue Nicholas Kazlauskas (1): drm/amd/display: Defer cursor lock until after VUPDATE Rodrigo Siqueira (1): drm/amd/display: Remove dml_common_def file Vladimir Stempen (1): drm/amd/display: DP training to set properly SCRAMBLING_DISABLE drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 27 + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 69 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 5 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 + drivers/gpu/drm/amd/display/dc/dml/Makefile| 2 - .../display/dc/dml/dcn20/display_rq_dlg_calc_20.h | 1 - .../dc/dml/dcn20/display_rq_dlg_calc_20v2.h| 1 - .../display/dc/dml/dcn21/display_rq_dlg_calc_21.h | 2 +- .../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 6 +- .../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 - .../amd/display/dc/dml/display_rq_dlg_helpers.h| 1 - .../amd/display/dc/dml/dml1_display_rq_dlg_calc.h | 2 - .../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 43 -- .../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 37 .../gpu/drm/amd/display/dc/dml/dml_inline_defs.h | 15 - drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 ++ 18 files changed, 126 insertions(+), 95 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/radeon/dpm: Replace one-element array and use struct_size() helper
The current codebase makes use of one-element arrays in the following
form:
struct something {
int length;
u8 data[1];
};
struct something *instance;
instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
instance->length = size;
memcpy(instance->data, source, size);
but the preferred mechanism to declare variable-length types such as
these ones is a flexible array member[1][2], introduced in C99:
struct foo {
int stuff;
struct boo array[];
};
By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on. So, replace
the one-element array with a flexible-array member.
Also, make use of the new struct_size() helper to properly calculate the
size of struct NISLANDS_SMC_SWSTATE.
This issue was found with the help of Coccinelle and, audited and fixed
_manually_.
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/amd/amdgpu/si_dpm.h | 2 +-
drivers/gpu/drm/radeon/ni_dpm.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.h
b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
index 6b7d292b919f3..bc0be6818e218 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
@@ -781,7 +781,7 @@ struct NISLANDS_SMC_SWSTATE
uint8_t levelCount;
uint8_t padding2;
uint8_t padding3;
-NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1];
+NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[];
};
typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index b57c37ddd164c..7d81dde509dc9 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -2685,11 +2685,12 @@ static int ni_upload_sw_state(struct radeon_device
*rdev,
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
u16 address = pi->state_table_start +
offsetof(NISLANDS_SMC_STATETABLE, driverState);
- u16 state_size = sizeof(NISLANDS_SMC_SWSTATE) +
- ((NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1) *
sizeof(NISLANDS_SMC_HW_PERFORMANCE_LEVEL));
+ NISLANDS_SMC_SWSTATE *smc_state;
+ u16 state_size = struct_size(smc_state, levels,
+ NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE);
int ret;
- NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL);
+ smc_state = kzalloc(state_size, GFP_KERNEL);
if (smc_state == NULL)
return -ENOMEM;
--
2.26.2
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/3] Revert "drm/amdgpu: off by one in amdgpu_device_attr_create_groups() error handling"
[AMD Official Use Only - Internal Distribution Only]
Series is:
Reviewed-by: Kevin Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, May 22, 2020 4:23 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/3] Revert "drm/amdgpu: off by one in
amdgpu_device_attr_create_groups() error handling"
This reverts commit b41d9df2b680b96913cc3ccf929252e2dce71b24.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2fc51f815eaa..72bbb8175b22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1843,8 +1843,9 @@ static int amdgpu_device_attr_create_groups(struct
amdgpu_device *adev,
return 0;
failed:
- while (i--)
+ for (; i > 0; i--) {
amdgpu_device_attr_remove(adev, &attrs[i]);
+ }
return ret;
}
--
2.25.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CLikun.Gao%40amd.com%7C6bb02ce265514761907d08d7fdc4ce0c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256894700890419&sdata=jiAa7VaiOak3oRjY4xd19fHlEnOWi%2Fed66AXfwVdGUo%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Reviewed-by: Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0539b7a16a5f488b7ddf08d7fdc09f30%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256876073183596&sdata=gIakEeKOfji3Z29RdDojiPDtCegcfcCvFP0%2FOVFeSaQ%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cguchun.chen%40amd.com%7C0539b7a16a5f488b7ddf08d7fdc09f30%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256876068046189&sdata=wMjQV6VwTBu8pCfQjXf39e1ffQSkQHKkZdXyWjue%2FJk%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Chawking.zhang%40amd.com%7Cab787c659a654d8e6f9c08d7fe02c725%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257160214567792&sdata=gTreRUn9%2Br1sS%2FrMEA7bJ630LusX1396szicn2ZDwrg%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Chawking.zhang%40amd.com%7Cab787c659a654d8e6f9c08d7fe02c725%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63725716021459&sdata=yVL3hqGTscc9HtIj6YHRxo113b0VO0rqtorm1blUa4U%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerplay: skip i2c eeprom init/fini under sriov mode
i2c eeprom init/fini is only needed under bare mental mode.
Signed-off-by: Hua Zhang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 24 +-
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 8017386d3c33..a78a1f542ea9 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1363,9 +1363,11 @@ static int smu_hw_init(void *handle)
if (ret)
goto failed;
- ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
- if (ret)
- goto failed;
+ if (!amdgpu_sriov_vf(adev)) {
+ ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
+ if (ret)
+ goto failed;
+ }
adev->pm.dpm_enabled = true;
@@ -1406,9 +1408,9 @@ static int smu_hw_fini(void *handle)
adev->pm.dpm_enabled = false;
- smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
-
if (!amdgpu_sriov_vf(adev)){
+ smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
+
ret = smu_stop_thermal_control(smu);
if (ret) {
pr_warn("Fail to stop thermal control!\n");
@@ -1549,9 +1551,9 @@ static int smu_suspend(void *handle)
adev->pm.dpm_enabled = false;
- smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
+ if (!amdgpu_sriov_vf(adev)) {
+ smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
- if(!amdgpu_sriov_vf(adev)) {
ret = smu_disable_dpm(smu);
if (ret)
return ret;
@@ -1596,9 +1598,11 @@ static int smu_resume(void *handle)
if (ret)
goto failed;
- ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
- if (ret)
- goto failed;
+ if (!amdgpu_sriov_vf(adev)) {
+ ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
+ if (ret)
+ goto failed;
+ }
if (smu->is_apu)
smu_set_gfx_cgpg(&adev->smu, true);
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: fix sysfs power controls with multi-GPU
[AMD Official Use Only - Internal Distribution Only] Acked-by: Evan Quan -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Friday, May 22, 2020 5:38 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu: fix sysfs power controls with multi-GPU Reset the SUPPORTED attribute. Signed-off-by: Alex Deucher --- This fixes multi-GPU, but I think we could still race without some sort of locking around the attr array. drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index e06fef6174e5..4c65444e9ef7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1790,6 +1790,8 @@ static int amdgpu_device_attr_create(struct amdgpu_device *adev, BUG_ON(!attr); +attr->states = ATTR_STATE_SUPPORTED; + attr_update = attr->attr_update ? attr_update : default_attr_update; ret = attr_update(adev, attr, mask); -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7C4f723e2ec23445c7cb1b08d7fdcf4618%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256939010091750&sdata=pZgnlqdAqOFNIX%2FfDKUiB1J%2FoOIFz72E3pEaTgpTg2I%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: fix pm sysfs node handling (v2)
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, May 22, 2020 12:27 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: fix pm sysfs node handling (v2)
Fix typos that prevented them from showing up.
v2: switch other files in addition to pp_clk_voltage
Fixes: 4e01847c38f7a5 ("drm/amdgpu: optimize amdgpu device attribute code")
Bug:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1150&data=02%7C01%7Cevan.quan%40amd.com%7Cf0caf70513f64f2e30fc08d7fda3ce90%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256753077066180&sdata=HPUaGNSuRuqo4YndKafc5hAwTI88lalIOBXoUtJ3DPA%3D&reserved=0
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2fc51f815eaa..e06fef6174e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1731,10 +1731,10 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
#define DEVICE_ATTR_IS(_name)(!strcmp(attr_name, #_name))
if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
-if (asic_type <= CHIP_VEGA10)
+if (asic_type < CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
-if (asic_type <= CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
+if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
attr->states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
if (asic_type < CHIP_VEGA20)
@@ -1746,7 +1746,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
attr->states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
-attr->states = ATTR_STATE_UNSUPPORTED;
+attr->states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED; @@ -1758,7 +1758,7 @@ static int
default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
if (!adev->unique_id)
attr->states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_features)) {
-if (adev->flags & AMD_IS_APU || asic_type <= CHIP_VEGA10)
+if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED;
}
--
2.25.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7Cf0caf70513f64f2e30fc08d7fda3ce90%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256753077066180&sdata=qenyCI1dUTbVXWeXiPWH2qKvSd9bVlytNeED9IR%2BX00%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: fix pp_clk_voltage handling
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 21, 2020 10:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: fix pp_clk_voltage handling
Fix a typo with pp_clk_voltage that prevented it from showing up.
Fixes: 4e01847c38f7a5 ("drm/amdgpu: optimize amdgpu device attribute code")
Bug:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1150&data=02%7C01%7Cevan.quan%40amd.com%7Cf9ce40dd1bbe4648398508d7fd916496%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256673966766036&sdata=LDdO5lyk8CBtzTwIk6WPWvHFAnQFRByAyfPK4dyR9hU%3D&reserved=0
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2fc51f815eaa..88dfc61fa084 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1746,7 +1746,7 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
attr->states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
-attr->states = ATTR_STATE_UNSUPPORTED;
+attr->states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
attr->states = ATTR_STATE_UNSUPPORTED;
--
2.25.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7Cf9ce40dd1bbe4648398508d7fd916496%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256673966766036&sdata=DGtoAsuqvILkQcxB6cqhtXXi54gmGgWDAlBf0Rr1ZsA%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/powerplay: skip i2c eeprom init/fini under sriov mode
[AMD Official Use Only - Internal Distribution Only]
please add a detailed description of the reason for this patch,
after finshed, the patch is
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Hua Zhang
Sent: Friday, May 22, 2020 1:31 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hua
Subject: [PATCH] drm/amd/powerplay: skip i2c eeprom init/fini under sriov mode
i2c eeprom init/fini is only needed under bare mental mode.
Signed-off-by: Hua Zhang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 24 +-
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 8017386d3c33..a78a1f542ea9 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1363,9 +1363,11 @@ static int smu_hw_init(void *handle)
if (ret)
goto failed;
- ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
- if (ret)
- goto failed;
+ if (!amdgpu_sriov_vf(adev)) {
+ ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
+ if (ret)
+ goto failed;
+ }
adev->pm.dpm_enabled = true;
@@ -1406,9 +1408,9 @@ static int smu_hw_fini(void *handle)
adev->pm.dpm_enabled = false;
- smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
-
if (!amdgpu_sriov_vf(adev)){
+ smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
+
ret = smu_stop_thermal_control(smu);
if (ret) {
pr_warn("Fail to stop thermal control!\n");
@@ -1549,9 +1551,9 @@ static int smu_suspend(void *handle)
adev->pm.dpm_enabled = false;
- smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
+ if (!amdgpu_sriov_vf(adev)) {
+ smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
- if(!amdgpu_sriov_vf(adev)) {
ret = smu_disable_dpm(smu);
if (ret)
return ret;
@@ -1596,9 +1598,11 @@ static int smu_resume(void *handle)
if (ret)
goto failed;
- ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
- if (ret)
- goto failed;
+ if (!amdgpu_sriov_vf(adev)) {
+ ret = smu_i2c_eeprom_init(smu, &adev->pm.smu_i2c);
+ if (ret)
+ goto failed;
+ }
if (smu->is_apu)
smu_set_gfx_cgpg(&adev->smu, true);
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CKevin1.Wang%40amd.com%7Cc8e0d6a298474263093c08d7fe115797%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257222795940615&sdata=LR7lQJ3I2XorNFokkz%2FRe6JK6H3TT3hlprc6EWHNPpI%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/7] drm/amdgpu/sdma4: add renoir to powergating setup
[AMD Official Use Only - Internal Distribution Only]
Series is reviewed-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 21, 2020 10:17 PM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 1/7] drm/amdgpu/sdma4: add renoir to powergating setup
Ping on this series?
Alex
On Tue, May 19, 2020 at 11:44 AM Alex Deucher wrote:
>
> Looks like renoir should be handled here as well.
>
> Signed-off-by: Alex Deucher
> ---
>
> Can someone test this on renoir?
>
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 9077507b425a..a8cad03b1c42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2203,6 +2203,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
>
> switch (adev->asic_type) {
> case CHIP_RAVEN:
> + case CHIP_RENOIR:
> sdma_v4_1_update_power_gating(adev,
> state == AMD_PG_STATE_GATE ? true : false);
> break;
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7C318853dc869c41a81b8f08d7fd919b67%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256674158399008&sdata=8wJnYwuJbMYQTMCMRUzUE0W2XeSQ239x44Hh5bRXXOE%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C99086e3adedb45ad03ea08d7fe0e3fc9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257210092457510&sdata=ntHm%2Bgwj4Q9Tv30c1irg%2BWf7y9QxQUSTO4%2FWMhpjK6g%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C99086e3adedb45ad03ea08d7fe0e3fc9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257210092457510&sdata=ntHm%2Bgwj4Q9Tv30
Re: [PATCH] drm/amdgpu: fix sysfs power controls with multi-GPU
[AMD Official Use Only - Internal Distribution Only] Hi Alex, the flag of "ATTR_STATE_[UN]SUPPORTED" should be binding to device not device attribute node, when inserting two different video cards, the driver may be need to create different node according device type (vega, navi,...), and when unload driver, the driver also need remove different node according device type and the state of ATTR_STATE_SUPPORTED. so i think the ATTR_STATE_XXX is not work well on multi gpu, so we'd better revert previous patch. thanks. Best Regards, Kevin From: amd-gfx on behalf of Quan, Evan Sent: Friday, May 22, 2020 1:35 PM To: Alex Deucher ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: RE: [PATCH] drm/amdgpu: fix sysfs power controls with multi-GPU [AMD Official Use Only - Internal Distribution Only] [AMD Official Use Only - Internal Distribution Only] Acked-by: Evan Quan -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Friday, May 22, 2020 5:38 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu: fix sysfs power controls with multi-GPU Reset the SUPPORTED attribute. Signed-off-by: Alex Deucher --- This fixes multi-GPU, but I think we could still race without some sort of locking around the attr array. drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index e06fef6174e5..4c65444e9ef7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1790,6 +1790,8 @@ static int amdgpu_device_attr_create(struct amdgpu_device *adev, BUG_ON(!attr); +attr->states = ATTR_STATE_SUPPORTED; + attr_update = attr->attr_update ? attr_update : default_attr_update; ret = attr_update(adev, attr, mask); -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CKevin1.Wang%40amd.com%7Cd86afa6ac5ab49bd75d208d7fe11ed8d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257225315854026&sdata=TMiKBdpSF4wPgkLgbRBtTloPLFBHyyLXuO%2BxSgSE%2BeY%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CKevin1.Wang%40amd.com%7Cd86afa6ac5ab49bd75d208d7fe11ed8d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257225315864023&sdata=MtypjxOmgqJhKwNEMH75r3Z%2F9M3Uv7qTpOjQo1yBSVk%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: simplify ATIF backlight handling
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, May 6, 2020 3:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: simplify ATIF backlight handling
Just register the a pointer to the backlight device and use that. Unifies the
DC and non-DC handling.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 73 ++--
1 file changed, 30 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 956cbbda4793..913c8f0513bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -64,7 +64,9 @@ struct amdgpu_atif {
struct amdgpu_atif_notifications notifications;
struct amdgpu_atif_functions functions;
struct amdgpu_atif_notification_cfg notification_cfg;
-struct amdgpu_encoder *encoder_for_bl;
+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
+struct backlight_device *bd;
+#endif
struct amdgpu_dm_backlight_caps backlight_caps; };
@@ -444,45 +446,21 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n", count);
-if ((req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) &&
-!amdgpu_device_has_dc_support(adev)) {
-struct amdgpu_encoder *enc = atif->encoder_for_bl;
-
-if (enc) {
-struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;
-
-DRM_DEBUG_DRIVER("Changing brightness to %d\n",
- req.backlight_level);
-
-amdgpu_display_backlight_set_level(adev, enc, req.backlight_level);
-
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-backlight_force_update(dig->bl_dev,
- BACKLIGHT_UPDATE_HOTKEY);
-#endif
-}
-}
-#if defined(CONFIG_DRM_AMD_DC)
+if (req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) {
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-if ((req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) &&
-amdgpu_device_has_dc_support(adev)) {
-struct amdgpu_display_manager *dm = &adev->dm;
-struct backlight_device *bd = dm->backlight_dev;
-
-if (bd) {
+if (atif->bd) {
DRM_DEBUG_DRIVER("Changing brightness to %d\n",
req.backlight_level);
-
/*
* XXX backlight_device_set_brightness() is
* hardwired to post BACKLIGHT_UPDATE_SYSFS.
* It probably should accept 'reason' parameter.
*/
-backlight_device_set_brightness(bd, req.backlight_level);
+backlight_device_set_brightness(atif->bd, req.backlight_level);
}
-}
-#endif
#endif
+}
+
if (req.pending & ATIF_DGPU_DISPLAY_EVENT) {
if (adev->flags & AMD_IS_PX) {
pm_runtime_get_sync(adev->ddev->dev);
@@ -829,23 +807,32 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
adev->atif = atif;
if (atif->notifications.brightness_change) {
-struct drm_encoder *tmp;
-
-/* Find the encoder controlling the brightness */
-list_for_each_entry(tmp, &adev->ddev->mode_config.encoder_list,
-head) {
-struct amdgpu_encoder *enc = to_amdgpu_encoder(tmp);
-
-if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
-enc->enc_priv) {
-struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;
-if (dig->bl_dev) {
-atif->encoder_for_bl = enc;
-break;
+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
+if (amdgpu_device_has_dc_support(adev)) { #if
+defined(CONFIG_DRM_AMD_DC)
+struct amdgpu_display_manager *dm = &adev->dm;
+atif->bd = dm->backlight_dev;
+#endif
+} else {
+struct drm_encoder *tmp;
+
+/* Find the encoder controlling the brightness */
+list_for_each_entry(tmp, &adev->ddev->mode_config.encoder_list,
+head) {
+struct amdgpu_encoder *enc = to_amdgpu_encoder(tmp);
+
+if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
+enc->enc_priv) {
+struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;
+if (dig->bl_dev) {
+atif->bd = dig->bl_dev;
+break;
+}
}
}
}
}
+#endif
if (atif->functions.sbios_requests && !atif->functions.system_params) {
/* XXX check this workraround, if sbios request function is
--
2.25.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7Cf8a40f42e8ec4ea3c9e008d7f12d4592%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637243050173626661&sdata=yj1OgR%2FXj4X0VvZ3%2F%2FOIGgA0RDN4JP%2FG7IOuBM9xEaA%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/3] drm/amdgpu: move discovery gfx config fetching
[AMD Official Use Only - Internal Distribution Only]
Patch1, 2 are reviewed-by: Evan Quan
Patch3 is acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 21, 2020 10:16 PM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH 1/3] drm/amdgpu: move discovery gfx config fetching
Ping on this series? It fixes an ordering issue for raven2.
Alex
On Fri, May 15, 2020 at 2:31 PM Alex Deucher wrote:
>
> Move it into the fw_info function since it's logically part of the
> same functionality.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index cc41e8f5ad14..bab1be7abdf0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1617,8 +1617,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct
> amdgpu_device *adev)
> (const struct gpu_info_firmware_v1_0
> *)(adev->firmware.gpu_info_fw->data +
>
> le32_to_cpu(hdr->header.ucode_array_offset_bytes));
>
> - if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
> + if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
> + amdgpu_discovery_get_gfx_info(adev);
> goto parse_soc_bounding_box;
> + }
>
> adev->gfx.config.max_shader_engines =
> le32_to_cpu(gpu_info_fw->gc_num_se);
> adev->gfx.config.max_cu_per_sh =
> le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
> @@ -1768,9 +1770,6 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> if (r)
> return r;
>
> - if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
> - amdgpu_discovery_get_gfx_info(adev);
> -
> amdgpu_amdkfd_device_probe(adev);
>
> if (amdgpu_sriov_vf(adev)) {
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7Cb692d163dea04a8d9f3208d7fd918cbd%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256673921983400&sdata=mkNxi6pmkJCpIWNmzHhdmMk6%2BcYR%2BAYJcwwCvoDhlqs%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Friday, May 22, 2020 1:52 PM
To: Zhang, Hawking ; Chen, Guchun ;
Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b370
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Yes, please try best effort to not introduce guest/one_vf/mult_vf check.
Regards,
Hawking
-Original Message-
From: Liu, Monk
Sent: Friday, May 22, 2020 14:12
To: Liu, Monk ; Zhang, Hawking ; Chen,
Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Friday, May 22, 2020 1:52 PM
To: Zhang, Hawking ; Chen, Guchun ;
Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Or make it in more reasonable place.
Regards,
Hawking
-Original Message-
From: Zhang, Hawking
Sent: Friday, May 22, 2020 14:16
To: Liu, Monk ; Chen, Guchun ; Wan,
Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Yes, please try best effort to not introduce guest/one_vf/mult_vf check.
Regards,
Hawking
-Original Message-
From: Liu, Monk
Sent: Friday, May 22, 2020 14:12
To: Liu, Monk ; Zhang, Hawking ; Chen,
Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Friday, May 22, 2020 1:52 PM
To: Zhang, Hawking ; Chen, Guchun ;
Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT
