[AMD Public Use]
Ping for the series.
Regards,
Guchun
-Original Message-
From: Chen, Guchun
Sent: Wednesday, July 29, 2020 10:56 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ; Li, Dennis
; Grodzovsky, Andrey ; Zhou1, Tao
; Clements, John ; Lazar, Lijo
Am 28.07.20 um 11:00 schrieb Monk Liu:
what:
the MQD's save and restore of KCQ (kernel compute queue)
cost lots of clocks during world switch which impacts a lot
to multi-VF performance
how:
introduce a paramter to control the number of KCQ to avoid
performance drop if there is no kernel
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: Ie6e9377f5984c3c09737b323c52249f9189bcaf5
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 74 +---
1 file
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: I8836f7f096dceb08a90dd3c899d2e9ccea1ef1f3
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 31 ---
1 file
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: I780aba0be35a35bd9c9727118b33625e7cc9bf1f
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++
1 file
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: Ic9d5f10b470584c82d4ca9035ab27fed44f0ac20
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 73 +--
1 file
Am 30.07.20 um 12:25 schrieb Pierre-Eric Pelloux-Prayer:
Allows UMD to know if TMZ is supported and enabled.
This commit also bumps KMS_DRIVER_MINOR so UMD knows if it can rely on
AMDGPU_IDS_FLAGS_TMZ.
---
Patch for using it in Mesa is at
The other debugfs functions should probably be updated as well... I
just did this one as an example of how these functions are normally
implemented.
There are some other warnings we could look at as well.
regards,
dan carpenter
Am 30.07.20 um 13:50 schrieb Christian König:
Am 30.07.20 um 13:40 schrieb Daniel Vetter:
On Wed, Jul 29, 2020 at 5:34 PM Koenig, Christian
wrote:
Sure.
Note that drm-misc-next isn't the right branch for cc: stable stuff, see
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: I281b4de9262b98f0c52131feb39ba9e101b548b7
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 60 ++
1 file
Enable gpu_metrics support on legacy powerplay routines.
Change-Id: Ic2f09babe7e6bead9a838b7ce3c94bf8d4110991
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 +++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
2 files changed, 20
Add Vega20 gpu metrics export interface.
Change-Id: I7b4ab850358cc6d7455889d9031a7111cba35ebd
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 121 +-
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.h| 1 +
2 files changed, 115 insertions(+), 7
Add Vega12 gpu metrics export interface.
Change-Id: I2c910f523049f0f90eecb8d74cb73ebb39a22bd9
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 109 ++
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.h| 1 +
2 files changed, 110 insertions(+)
diff
One comment on patch #17, apart from that the series is Reviewed-by:
Christian König .
Regards,
Christian.
Am 29.07.20 um 19:34 schrieb Alex Deucher:
Split the allocations into two so we can still support the S3
workarounds required on some platforms while also avoiding
any artifacts when
Am 29.07.20 um 19:34 schrieb Alex Deucher:
It's related to the memory manager so move it there.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 4 ++--
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: Ic2a27ebc90f0a7cf581d0697c121b6d7df030f3b
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 29 ---
1 file
Enable GFXOFF for navy_flounder.
Signed-off-by: Jiansong Chen
Change-Id: Ia49c1ad70e3521447b9db101f5c0eae70b1df665
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
2 files changed, 2 insertions(+)
diff --git
Allows UMD to know if TMZ is supported and enabled.
This commit also bumps KMS_DRIVER_MINOR so UMD knows if it can rely on
AMDGPU_IDS_FLAGS_TMZ.
---
Patch for using it in Mesa is at
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049
(ac/gpu_info: add detection of TMZ support).
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Jiansong Chen
> Sent: Thursday, July 30, 2020 6:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao ; Chen, Jiansong (Simon)
>
> Subject: [PATCH] drm/amdgpu: enable GFXOFF
On Wed, Jul 29, 2020 at 5:34 PM Koenig, Christian
wrote:
>
> Sure.
Note that drm-misc-next isn't the right branch for cc: stable stuff, see
https://drm.pages.freedesktop.org/maintainer-tools/committer-drm-misc.html#where-do-i-apply-my-patch
Just to avoid confusion and needless cherrypicking
There are problems with the dp_dsc_clock_en_read() function. Only one
of the memory leak is a runtime bug.
1) It leaks memory on the -ENXIO and -EFAULT error paths.
2) There is a discrepency between rd_buf_size (10) and str_len (30).
Static analysis complain that this could lead to a
Hi Christian,
On 30/07/2020 12:30, Christian König wrote:
> Am 30.07.20 um 12:25 schrieb Pierre-Eric Pelloux-Prayer:
>> Allows UMD to know if TMZ is supported and enabled.
>> This commit also bumps KMS_DRIVER_MINOR so UMD knows if it can rely on
>> AMDGPU_IDS_FLAGS_TMZ.
>> ---
>> Patch for using
Am 30.07.20 um 12:59 schrieb Pierre-Eric Pelloux-Prayer:
Hi Christian,
On 30/07/2020 12:30, Christian König wrote:
Am 30.07.20 um 12:25 schrieb Pierre-Eric Pelloux-Prayer:
Allows UMD to know if TMZ is supported and enabled.
This commit also bumps KMS_DRIVER_MINOR so UMD knows if it can rely
[AMD Official Use Only - Internal Distribution Only]
This patch is Reviewed-by: Likun Gao
Regards,
Likun
-Original Message-
From: amd-gfx On Behalf Of Jiansong Chen
Sent: Thursday, July 30, 2020 6:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chen, Jiansong (Simon)
Am 30.07.20 um 13:40 schrieb Daniel Vetter:
On Wed, Jul 29, 2020 at 5:34 PM Koenig, Christian
wrote:
Sure.
Note that drm-misc-next isn't the right branch for cc: stable stuff, see
https://drm.pages.freedesktop.org/maintainer-tools/committer-drm-misc.html#where-do-i-apply-my-patch
So this
[AMD Public Use]
Thanks Hawking.
I will conduct more tests today before pushing the patches.
Regards,
Guchun
-Original Message-
From: Zhang, Hawking
Sent: Thursday, July 30, 2020 10:21 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ; Li, Dennis ;
what:
the MQD's save and restore of KCQ (kernel compute queue)
cost lots of clocks during world switch which impacts a lot
to multi-VF performance
how:
introduce a paramter to control the number of KCQ to avoid
performance drop if there is no kernel compute queue needed
notes:
this paramter only
[AMD Official Use Only - Internal Distribution Only]
Thanks for reporting this. I will check it.
BR
Evan
-Original Message-
From: Matt Coffin
Sent: Thursday, July 30, 2020 10:25 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Alex Deucher
Subject: [Bug][Regression][Bisected]
Am 2020-07-30 um 10:11 p.m. schrieb Liu, Monk:
> [AMD Official Use Only - Internal Distribution Only]
>
Indentation looks wrong. Did you use the wrong TAB size?
> My TAB size is 4 space, and I don't know why it looks strange , but I can use
> space to replace the TABs anyway
The linux
Although it does not bring any problem for now, the coming gpu
metrics interface needs to handle them differently based on the
asic type.
Change-Id: I88ee78c26795267588f944d4f1983e4dbf23ba85
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
.../powerplay/inc/smu11_driver_if_navi10.h|
Add Arcturus gpu metrics export interface.
Change-Id: I372337f31e2b7174d41fb4e3af180deb94b5ec06
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 92 +++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 +
Thus we can provide an interface for UMD to retrieve gpu metrics data.
V2: better naming and comments
V3: two structures created for dGPU and APU separately
V4: add driver attached timestamp
Change-Id: Ibc2d5c642eff732c082f8447348749a44dc35be3
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Add Sienna Cichlid gpu metrics export interface.
Change-Id: I89e6a4415fe467e7e4aaabe07d9e8cee379caa25
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 91 ++-
1 file changed, 89 insertions(+), 2 deletions(-)
diff --git
A new interface for UMD to retrieve gpu metrics data.
V2: rich the documentation
Change-Id: If7f3523915505c0ece0a56dfd476d2b8473440d4
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
Documentation/gpu/amdgpu.rst | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h |
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: Ic9d5f10b470584c82d4ca9035ab27fed44f0ac20
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 73 +--
1 file
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: Ie6e9377f5984c3c09737b323c52249f9189bcaf5
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 74 +---
1 file
Add Renoir gpu metrics export interface.
V2: use memcpy to make code more compact
Change-Id: Ic83265536eeaa9e458dc395b2be18ea49da4c68a
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 +
drivers/gpu/drm/amd/powerplay/renoir_ppt.c|
Add Navi1x gpu metrics export interface.
Change-Id: I9028fb925e70c36fb2a0b00968c462c0bbc822db
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 93 +-
1 file changed, 91 insertions(+), 2 deletions(-)
diff --git
Add Vega20 gpu metrics export interface.
Change-Id: I7b4ab850358cc6d7455889d9031a7111cba35ebd
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 123 +-
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.h| 1 +
2 files changed, 117 insertions(+), 7
Add Vega12 gpu metrics export interface.
Change-Id: I2c910f523049f0f90eecb8d74cb73ebb39a22bd9
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 111 ++
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.h| 1 +
2 files changed, 112 insertions(+)
diff
This will be shared around all SMU V11 asics.
Change-Id: Iaa4554fb0e011b9f565d89375ac7b6a7eb525420
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 9 +---
Hello Matt,
Thank you for your testing. It seems that my gpu (RX 570) does not support the
vc setting so I can not exactly reproduce the issue. However I did trace the
code path the test case takes and it seems to correctly pass through the while
loop that parses the input and fails only in
[AMD Official Use Only - Internal Distribution Only]
>>> Indentation looks wrong. Did you use the wrong TAB size?
My TAB size is 4 space, and I don't know why it looks strange , but I can use
space to replace the TABs anyway
Will send v4 patch against other suggestions from your side soon
what:
the MQD's save and restore of KCQ (kernel compute queue)
cost lots of clocks during world switch which impacts a lot
to multi-VF performance
how:
introduce a paramter to control the number of KCQ to avoid
performance drop if there is no kernel compute queue needed
notes:
this paramter only
[AMD Official Use Only - Internal Distribution Only]
My latest patch was already based on visually 8 SPACE per TAB config, but the
TAB was *not* replaced by real eight spaces
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From:
Hey Pawel,
I did confirm that this patch *introduced* the issue both with the
bisect, and by testing reverting it.
Now, there's a lot of fragile pieces in the dpm handling, so it could be
this patch's interaction with something else that's causing it and it
may well not be the fault of this
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: I8836f7f096dceb08a90dd3c899d2e9ccea1ef1f3
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 31 ---
1 file
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: I281b4de9262b98f0c52131feb39ba9e101b548b7
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 60 ++
1 file
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: I780aba0be35a35bd9c9727118b33625e7cc9bf1f
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++
1 file
As for the gpu metric export, metrics cache makes no sense. It's up to
user to decide how often the metrics should be retrieved.
Change-Id: Ic2a27ebc90f0a7cf581d0697c121b6d7df030f3b
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 29 ---
1 file
Enable gpu_metrics support on legacy powerplay routines.
Change-Id: Ic2f09babe7e6bead9a838b7ce3c94bf8d4110991
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 +++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
2 files changed, 20
Hi Dave, Daniel,
A few fixes for 5.8. It would be nice to get these in for 5.8 final. Take
2 just reverts the original fix because the fix for the fix seems to cause
other problems.
The following changes since commit a4a2739beb8933a19281bca077fdb852598803ed:
Merge tag
[AMD Public Use]
The new series looks good to me in general, but still the following nitpicks
Patch #1
Default typical value --> default value
Patch #4
+ DRM_ERROR("Exceeding the bad_page_threshold parameter, "
+ "disabling the GPU.\n");
Let's use
On Wed, Jul 29, 2020 at 11:36 PM Alex Deucher wrote:
>
> Hi Dave, Daniel,
>
> A few fixes for 5.8. It would be nice to get these in for 5.8 final, but if
> it's too late, they can go back via stable from 5.9.
Ignore this one. The NULL pointer regression fix didn't fully fix the
issue, so I'm
I already replied to v3 of your patch on Tuesday. Did you see my
comments about further simplifying the two queue allocation policies?
Regards,
Felix
Am 2020-07-29 um 11:03 p.m. schrieb Liu, Monk:
> [AMD Official Use Only - Internal Distribution Only]
>
> Ping
>
>
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hey Evan,
I've been having an issue with uploading `pp_table`s on recent
`amd-staging-drm-next` kernels. I bisected the issue, and it came back
to a commit of yours - ec8ee23f610578c71885a36ddfcf58d35cccab67.
I didn't have your gitlab handle to CC
Am 30.07.20 um 15:54 schrieb Pierre-Eric Pelloux-Prayer:
Allows UMD to know if TMZ is supported and enabled.
This commit also bumps KMS_DRIVER_MINOR because if we don't
UMD can't tell if "ids_flags & AMDGPU_IDS_FLAGS_TMZ == 0" means
"tmz is not enabled" or "tmz may be enabled but the kernel
Hello all, I just did some testing with this applied, and while it no
longer returns -EINVAL, running `sudo sh -c 'echo "vc 2 2150 1195" >
/sys/class/drm/card1/device/pp_od_clk_voltage'` results in `sh` spiking
to, and staying at 100% CPU usage, with no indicating information in
`dmesg` from the
Allows UMD to know if TMZ is supported and enabled.
This commit also bumps KMS_DRIVER_MINOR because if we don't
UMD can't tell if "ids_flags & AMDGPU_IDS_FLAGS_TMZ == 0" means
"tmz is not enabled" or "tmz may be enabled but the kernel doesn't
report it".
v2: use amdgpu_is_tmz() and reworded
On 7/30/20 9:26 AM, Nirmoy wrote:
memcpy() would this much more compact.
memcpy() would make this much more compact.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
On 7/30/20 5:28 AM, Evan Quan wrote:
Add Renoir gpu metrics export interface.
Change-Id: Ic83265536eeaa9e458dc395b2be18ea49da4c68a
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 +
drivers/gpu/drm/amd/powerplay/renoir_ppt.c|
From: George Shen
[Why]
During SetPathMode and UpdatePlanes, the plane state can be null. We default
to linear swizzle mode when plane state is null. This resulted in bandwidth
validation failing when trying to set 8K60 mode (which previously passed
validation
during rebuild timing list).
From: Victor Lu
[why]
There's currently no method to enable multi-stream synchronization from
userspace and we don't check the VSDB bits to know whether or not
specific displays should have the feature enable.
[how]
Add a debugfs entry that controls a new DM debug option,
"force_timing_sync".
From: Eryk Brol
[why]
Some of the DSC debugfs read enteries are missing comments
explaining how to use and how to comprehend the results.
Signed-off-by: Eryk Brol
Signed-off-by: Mikita Lipski
Reviewed-by: Mikita Lipski
Acked-by: Aurabindo Pillai
---
From: Igor Kravchenko
[why]
Display goes blank after driver installation.
Aux tuning parameters must be used for 2.x only.
Wrong dc_golden_table offset was used.
[How]
Implement a new enc3_hw_init function without VBIOS constants usage to
be called for 3.x
Calculate dc_golden_table offset using
From: Anthony Koo
| [Header Changes]
| - Reworked the FW versioning to include hotfix
| and test bits
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 15 ---
1 file changed, 12
From: Alvin Lee
[Why]
When changing pixel formats for HDR (e.g. ARGB -> FP16)
there are configurations that change from 2 pipes to 1 pipe.
In these cases, it seems that disconnecting MPCC and doing
a surface update at the same time(after unlocking) causes
some registers to be updated slightly
From: Eryk Brol
[Why]
We need to be able to specify slice height for any connector's DSC
[How]
Overwrite computed parameters in dsc_cfg, with the value needed/
Overwrites for both SST and MST connectors, but in different places, but the
process is identical. Overwrites only if DSC is decided
From: Igor Kravchenko
[Why]
For ver.4.4 and higher VBIOS contains default setting table.
{How]
Read Golden Settings Table from VBIOS, apply Aux tuning parameters.
Signed-off-by: Igor Kravchenko
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Chris Park
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
From: "JinZe.Xu"
[How]
Use dc_is_hdmi_signal to determine signal type.
Signed-off-by: JinZe.Xu
Reviewed-by: Charlene Liu
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Aric Cyr
[Why]
Sink OUI supported cap is not set so driver skips programming it.
[How]
Revert the change the skips OUI programming if the cap is not set
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c |
From: Harry Wentland
[Why]
use correct logger context
Signed-off-by: Harry Wentland
Reviewed-by: Roman Li
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Eryk Brol
[Why]
We need to be able to specify bits per pixel for DSC on any
connector.
[How]
Overwrite computed DSC target rate in dsc_cfg, with requested value.
Overwrites for both SST and MST connectors, but in different places, but the
process is identical. Overwrites only if DSC is
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Display Core version 3.2.97
* New firmware release
* DSC improvements
* Bug fixes across DML, pipe managment
* Regression fixes for DP
--
Alvin Lee (1):
drm/amd/display: Separate pipe disconnect from rest of
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
---
.../amd/display/dc/virtual/virtual_stream_encoder.c | 13 +
1 file changed, 13 insertions(+)
diff --git
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
The i2c init/fini functions just register the i2c adapter.
There is no need to call them during hw init/fini. They only
need to be called once per driver init/fini. The previous
behavior broke runtime pm because we unregistered the i2c
adapter during suspend.
Signed-off-by: Alex Deucher
---
The new helper centralizes the logic in one place.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 112 +-
1 file changed, 38 insertions(+), 74 deletions(-)
diff --git
Just return early to match other bo_create functions.
v2: check if the bo_ptr is NULL rather than checking the size.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling (v1)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +++
1 file changed, 3
This will allow us to split the allocation for systems
where we have to keep the stolen memory around to avoid
S3 issues. This way we don't waste as much memory and
still avoid any screen artifacts during the bios to
driver transition.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
The new helper centralizes the logic in one place.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 57 +++---
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git
Should be functionally the same since nothing else is
allocated at that point, but let's be exact.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Rather than leaving this as a gmc v9 specific hack.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 -
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11
I suspect the only reason this was set was to avoid touching
the display related registers on arcturus. Someone should
double check this on arcturus with S3.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 -
It's related to the memory manager so move it there.
v2: inline the structure
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 4 ++--
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 4 ++--
This adds a new gmc callback to get the size reserved by the pre-OS
console and provides a helper function for use by gmc IP drivers.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 43 +
Since that is where we store the other data related to
the stolen vga memory.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 ++-
The new helper centralizes the logic in one place.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
Rather than open coding it everywhere.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
The new helper centralizes the logic in one place.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
Split the allocations into two so we can still support the S3
workarounds required on some platforms while also avoiding
any artifacts when transitioning from bios to driver.
In the future we could integrate handling of the ip discovery
data and other vbios allocations into this helper function
The new helper centralizes the logic in one place.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
We never use them.
Reviewed-by: Christian König
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
It's more related to memory management than memory
controller.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20
It's related to the memory manager so move it there.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 --
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 54 +--
Am 2020-07-30 um 11:42 p.m. schrieb Monk Liu:
> what:
> the MQD's save and restore of KCQ (kernel compute queue)
> cost lots of clocks during world switch which impacts a lot
> to multi-VF performance
>
> how:
> introduce a paramter to control the number of KCQ to avoid
> performance drop if
From: Evan Quan
Different mclk dpm policy will be applied based on the VRAM
width.
Signed-off-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
[Why]
DM atomic check was structured in a way that we required old DC state
in order to dynamically add and remove planes and streams from the
context to build the DC state context for validation.
DRM private objects were used to carry over the last DC state and
were added to the context on
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