From: Tom Rix
A semicolon is not needed after a switch statement.
Signed-off-by: Tom Rix
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
From: Tom Rix
A semicolon is not needed after a switch statement.
Signed-off-by: Tom Rix
---
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Eryk Brol
[Why]
We want to trigger atomic check on connector when
DSC debugfs properties are changed. The previous
method was reverted because it accessed connector
properties unsafely and would also heavily
impact performance.
[How]
Add a flag for forcing DSC update in CRTC state
and add
From: Wayne Lin
[why]
Currently, we only support calculating CRC on whole frame.
We want to extend the capability to calculate CRC on
specific frame area.
[how]
Calculate CRC on specific area once it's specified from the
input parameter.
Signed-off-by: Wayne Lin
Reviewed-by: Nicholas
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Alvin Lee
[Why]
When enabling PIP in Heaven, the PIP planes are VSYNC
flip and is also the top-most pipe. In this case GSL
will be disabled because we only check immediate flip
for the top pipe. However, the desktop planes are still
flip immediate so we should at least keep GSL on until
From: Hugo Hu
[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.
[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.
Signed-off-by: Hugo Hu
From: Dmytro Laktyushkin
Recout calculation does not corrrectly handle plane
clip rect that extends beyond the left most border
of stream source rect. This change adds handling by
truncating the invisible clip rect.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Hersen Wu
Acked-by: Qingqing
From: Anthony Koo
[Header Changes]
- Add command for retrieving PSR residency
- Add command for forcing PSR static
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +--
1 file changed, 9
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Chris Park
[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.
[How]
Implement same register space to future
resource files.
Signed-off-by: Chris Park
Reviewed-by: Joshua Aberback
Acked-by: Qingqing Zhuo
---
From: Yongqiang Sun
[Why & How]
1. only need to check first ODM pipe.
2. Only need to check eDP which is on.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
From: Jacky Liao
[Why]
The MPC memory blocks in DCN3 should be powered down completely when
they are not in use. This will reduce power consumption.
[How]
This commits changes behaviour for dcn3 and does the following:
1. Write to MPC_RMU_LOW_PWR_MODE and MPCC_OGAM_MEM_LOW_PWR_MODE to
From: Alvin Lee
[Why]
When checking if we want to disable GSL or not,
we should reset flip_immediate to be the flip type
of the topmost plane before looping through the
other planes.
[How]
Set flip_immediate to be the flip type of the topmost
plane before looping through the other planes.
From: Jacky Liao
[Why]
The OPTC memory blocks should be powered down when they are not in use.
This will reduce power consumption.
[How]
1. Set ODM_MEM_UNASSIGNED_PWR_MODE to shutdown memory when unassigned
2. Set ODM_MEM_VBLANK_PWR_MODE to light sleep mode when in vblank
3. Added a debug
From: Jake Wang
[Why]
Fail and restart timing for HDCP1 retry occurs too quickly.
This would cause some MST monitors to show black screen.
[How]
Adjusted timing of fail and restart to 200ms.
Signed-off-by: Jake Wang
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
From: Victor Lu
[why]
There is a DRM_ERROR when the dc_sink is NULL and
there should not be this warning when the connector
is forced.
[how]
Do not warn if dc_sink is NULL if the connector
is forced.
Signed-off-by: Victor Lu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
From: Joshua Aberback
[Why]
There are some timings for which we support p-state
switching in active, but not in blank. There was a
previous issue where a timing that had active-only
support would hang a p-state request when we were in
an extended blanking period. The workaround for that
issue
From: Joshua Aberback
[Why]
Commit "Blank HUBP during pixel data blank for DCN30 v2"
modifies HW behaviour during blank, which might have OS
dependencies. We need to assess the impact on amdgpu_dm
and only re-enable HUBP blanking when all necessary
changes are understood.
[How]
- revert
From: Isabel Zhang
[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.
[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Lewis Huang
[Why]
Driver keeps the invalid information cause report the
incorrect monitor which save in remote sink to OS
[How]
When connector type change from MST to non-MST,
stop the topology manager.
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
From: "Tao.Huang"
[Why]
The C standard does not specify whether an enum is signed or unsigned.
In the function prototype, one of the argument is defined as an enum
but its declaration was unit32_t. Fix this by changing the function
argument to enum in the declaration.
Signed-off-by: Tao.Huang
From: Ashley Thomas
[why]
If pbn_per_slot is 0, fail instead of dividing by zero and
bugchecking.
[how]
Check for zero divisor before division operation.
Signed-off-by: Ashley Thomas
Reviewed-by: Wyatt Wood
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 ++
From: Joshua Aberback
[Why]
Prior commit "Blank HUBP during pixel data blank for DCN30"
missed the call to set_disp_pattern_generator from
set_crtc_test_pattern, which re-exposed the issue for which
we initially blocked active-only p-state switching.
[How]
- remove dcn30_blank_pixel_data, set
This DC patchset brings improvements in multiple areas. In summary, we have:
* DC 3.2.110
* Firmware release 0.0.40
* Enable CRC calculation on specific frame region
* Bug fixes on GSL, recout calculation, missing pflip irq and more.
---
Alvin Lee (2):
drm/amd/display: Keep GSL for
From: Bhawanpreet Lakha
If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c | 4 ++--
1 file changed, 2
From: Dale Zhao
[Why]
Customer make a request to add this WA by driver.
Some MUX chips will power down with eDP 1.4 panel and
lose previous supported link rates(DPCD 0x010) in
customer's hybrid-GPU designs. As a result, during sleep
resuming and screen turns on from idle, link training
will be
[AMD Official Use Only - Internal Distribution Only]
Hi Sandeep,
Did you run the tests on Hawaii?
And can you help to confirm which method is used for gpu reset? "BACO reset" or
" PCI CONFIG reset" (you can grep these keywords in dmesg)?
BR
Evan
-Original Message-
From: Sandeep
Sent:
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, October 27, 2020 1:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/display: fix indentation
- When we are under SRIOV setup, the rev_id cannot be read
properly. Therefore, we will return default value for it
Change-Id: I188d8e1b77f97c2eb29ef01aaf9ff9ea396a51c2
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
1 file changed, 13 insertions(+),
Fix the compile warnings below:
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13:
>> warning: variable 'min' is used uninitialized whenever 'if' condition is
>> false [-Wsometimes-uninitialized]
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13:
>>
Fix the warning below:
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:29:
>> warning: no previous prototype for function 'asic_internal_ss_get_ss_table'
>> [-Wmissing-prototypes]
ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
[AMD Official Use Only - Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Tuesday, October 27, 2020 10:45 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
; kernel test robot
Subject: [PATCH 2/2]
[AMD Official Use Only - Internal Distribution Only]
Fix performace drop while streaming Doom
Signed-off-by: Li, Xin (Justin) mailto:xin2...@amd.com>>
Signed-off-by: Zhao, Jiange mailto:jiange.z...@amd.com>>
---
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 14 ++
1 file
[AMD Official Use Only - Internal Distribution Only]
Add checksum checking for pf2vf message
Signed-off-by: Li, Xin (Justin) mailto:xin2...@amd.com>>
Signed-off-by: Zhou, Tiecheng
mailto:tiecheng.z...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 ++---
1 file changed, 2
On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
> Which can be used for S4(hibernation) support.
>
> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
>
On Tue, 27 Oct, 2020, 17:01 Sandeep, wrote:
>
> On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
>
>> Which can be used for S4(hibernation) support.
>>
>> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
>> Signed-off-by: Evan Quan
>> ---
>> drivers/gpu/drm/amd/amdgpu/cik.c |
Running "make htmldocs: produce lots of warnings on those files:
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess
function parameter 'man' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess
function
Because bad pages saving has been moved to UMC error interrupt callback,
which will trigger a new GPU reset after saving.
Signed-off-by: Dennis Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h| 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 16
2 files
In amdgpu_ras_reset_gpu, because bad pages may not be freed,
it has high probability to reserve bad pages failed.
Change to reserve bad pages when freeing VRAM.
v2:
1. avoid allocating the drm_mm node outside of amdgpu_vram_mgr.c
2. move bad page reserving into amdgpu_ras_add_bad_pages, if vram
Instead of saving bad pages in amdgpu_ras_reset_gpu, it will reduce
the unnecessary calling of amdgpu_ras_save_bad_pages.
Signed-off-by: Dennis Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 7
Beside umc, others' UE interrupt callback could enter into amdgpu_ras_reset_gpu,
so the first patch change to save bad pages in UMC error interrupt callback.
When bad page error happens, the bad page mostly still be hold by some
process, therefore driver will fail to reserve the bad page. The
This patch is to add UMD Pstate Msg Parameters for vangogh temporarily,
the values refer to renoir.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 5 +
1 file changed, 5 insertions(+)
diff --git
This patch is to enable the rest functions of swSMU for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
This patch is to remove some redundant smu message mapping for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
This patch is to add one new function to get 32 bit feature mask for
vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 55 +++---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4 ++
2 files changed, 54 insertions(+), 5
This patch is to set the initial value of pm info to zero.
The "value64" is ported to the hwmon and debugfs node, it is a uint64 type.
When it is used for NV10/VEGA10/VEGA20, its word size is appropriate,
because NV10/VEGA10/VEGA20 has a 64bit smu feature mask, which is separated to
high 32bit
dm_comressor_info -> dm_compressor_info
The kernel-doc markup is right, but the struct itself
and their references contain a typo.
Signed-off-by: Mauro Carvalho Chehab
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6
A kernel-doc markup can't be mixed with a random comment,
as it causes parsing problems.
While here, change an invalid kernel-doc markup into
a common comment.
Signed-off-by: Mauro Carvalho Chehab
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +---
1 file changed, 5 insertions(+), 3
This patch is to update the smu v11.5 driver interface header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
.../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 70 +--
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 2 +-
2 files
This patch is to add new smc message mapping for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
This patch is to update the smu v11.5 smc header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 114 +++
1 file changed, 68 insertions(+), 46 deletions(-)
diff --git
This patch is to update the smu v11.5 firmware header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This patch is to add some swSMU functions for vangogh, to support the
sensor info on "hwmon" and pm info.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 411 ++
1 file changed, 338 insertions(+), 73 deletions(-)
diff
Am 27.10.20 um 10:05 schrieb Dennis Li:
In amdgpu_ras_reset_gpu, because bad pages may not be freed,
it has high probability to reserve bad pages failed.
Change to reserve bad pages when freeing VRAM.
v2:
1. avoid allocating the drm_mm node outside of amdgpu_vram_mgr.c
2. move bad page
[AMD Public Use]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Dennis Li
Sent: Tuesday, October 27, 2020 17:04
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Kuehling, Felix ; Zhang,
Hawking ; Koenig, Christian
Cc: Li, Dennis
Subject:
Is this really a patch for kernel.org? Seems like a hack for Stadia or
something. (And the patch description is not very good...)
This should really be made into a generic solution.
Regards
//Ernst
Den tis 27 okt. 2020 kl 07:38 skrev Li, Xin (Justin) :
> [AMD Official Use Only - Internal
On Tue, 27 Oct 2020 at 17:04, Sandeep wrote:
>
>
>
> On Tue, 27 Oct, 2020, 17:01 Sandeep, wrote:
>>
>>
>> On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
>>>
>>> Which can be used for S4(hibernation) support.
>>>
>>> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
>>> Signed-off-by: Evan
On Mon, Oct 26, 2020 at 10:43 PM Evan Quan wrote:
>
> Which can be used for S4(hibernation) support.
>
> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
>
Ping?
On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher wrote:
>
> This is required for MALL. Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is
> enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
>
On Mon, Oct 26, 2020 at 7:06 PM Luben Tuikov wrote:
>
> Consolidating DCN seems like a good idea.
>
> Reviewed-by: Luben Tuikov
Is this for the whole series or just this patch?
Thanks!
Alex
>
> Regards,
> Luben
>
> On 2020-10-26 12:35 p.m., Alex Deucher wrote:
> > Ping again?
> >
> > On Thu,
[AMD Official Use Only - Internal Distribution Only]
Looks sane to me.
Acked-by: Slava Abramov
From: amd-gfx on behalf of Alex Deucher
Sent: Tuesday, October 27, 2020 11:20 AM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu/display:
Properly protect the relevant code with CONFIG_DRM_AMD_DC_DCN.
Fixes: 0b08c54bb7a3 ("drm/amd/display: Fix the display corruption issue on
Navi10")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
Ping?
On Mon, Oct 26, 2020 at 1:50 PM Alex Deucher wrote:
>
> Fixes this warning:
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c: In function
> ‘defer_delay_converter_wa’:
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:285:2: warning:
> this ‘if’ clause does not
This rfc will describe
An upcoming treewide cleanup.
How clang tooling was used to programatically do the clean up.
Solicit opinions on how to generally use clang tooling.
The clang warning -Wextra-semi-stmt produces about 10k warnings.
Reviewing these, a subset of semicolon after a switch looks
66 matches
Mail list logo