it could also be insufficient vram that makes
amdgpu_amdkfd_reserve_mem_limit fail.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
skip load smu and sdma fw on sriov due to sos,
ta and asd fw have been skipped for SIENNA_CICHLID.
V2:
move asic check into smu11
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 +++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 --
Am 12.12.20 um 16:45 schrieb Hawking Zhang:
For all the ASICs that integrate psp v11, vega20
doesn't support ih reroute. arcturus and later will
allow kernel driver to program ih_cfg_index/data
through mmio directly. navi1x and onwards will only
support grb_ih_set command in sriov configuration.
On 11/12/2020 21:44, Luben Tuikov wrote:
On 2020-12-10 4:46 a.m., Steven Price wrote:
On 10/12/2020 02:14, Luben Tuikov wrote:
This patch does not change current behaviour.
The driver's job timeout handler now returns
status indicating back to the DRM layer whether
the task (job) was
Am 11.12.20 um 21:44 schrieb Luben Tuikov:
On 2020-12-10 4:41 a.m., Christian König wrote:
Am 10.12.20 um 10:31 schrieb Lucas Stach:
Hi Luben,
Am Mittwoch, den 09.12.2020, 21:14 -0500 schrieb Luben Tuikov:
[SNIP]
-static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job)
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Stanley.Yang
Sent: Monday, December 14, 2020 6:35 PM
To: amd-gfx@lists.freedesktop.org ; Jian, Jane
Cc: Yang, Stanley
Subject:
[AMD Public Use]
>-Original Message-
>From: amd-gfx On Behalf Of Likun
>Gao
>Sent: Monday, December 14, 2020 1:08 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deucher, Alexander ; Gao, Likun
>; Feng, Kenneth ; Zhang,
>Hawking
>Subject: [v2] drm/amdgpu: skip vram operation for BAMACO
We need to move the check under the non-headless case, otherwise
we always reserve the VGA save size.
Fixes: 157fe68d74c2ad ("drm/amdgpu: fix size calculation with stolen vga
memory")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +
1 file changed, 5
[AMD Public Use]
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Stanley.Yang
Sent: Monday, December 14, 2020 6:35 PM
To: amd-gfx@lists.freedesktop.org; Jian, Jane
Cc: Yang, Stanley
Subject: [PATCH V2 1/1] drm/amdgpu: skip load smu and sdma
I guess Christian didn't compile test amdkfd.
Fixes: e11bfb99d6ec ("drm/ttm: cleanup BO size handling v3")
Cc: Christian König
Cc: Huang Rui (v1)
Cc: Daniel Vetter
Cc: Felix Kuehling
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Daniel Vetter
---
On Mon, Dec 14, 2020 at 02:20:39PM -0500, Alex Deucher wrote:
> On Mon, Dec 14, 2020 at 2:17 PM Daniel Vetter wrote:
> >
> > I guess Christian didn't compile test amdkfd.
> >
> > Fixes: e11bfb99d6ec ("drm/ttm: cleanup BO size handling v3")
> > Cc: Christian König
> > Cc: Huang Rui (v1)
> > Cc:
Am 14.12.20 um 16:46 schrieb Darren Salt:
I demand that Christian König may or may not have written...
Am 11.12.20 um 18:31 schrieb Darren Salt:
< [SNIP]
If that isn't the case use fls() to get the highest set bit < 13.
That suggests that it'll be easiest to clear each bit after the
This reverts commit c38d444e44badc557cf29fdfdfb823604890ccfa.
Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the
On 03.12.20 22:30, Alex Deucher wrote:
> On Tue, Sep 29, 2020 at 4:04 PM Alex Deucher wrote:
>>
>> On Tue, Sep 29, 2020 at 8:31 AM Jan Kiszka wrote:
>>>
>>> On 10.09.20 20:18, Deucher, Alexander wrote:
[AMD Public Use]
> -Original Message-
> From: amd-gfx On
Am 2020-12-14 um 4:52 a.m. schrieb Yifan Zhang:
> it could also be insufficient vram that makes
> amdgpu_amdkfd_reserve_mem_limit fail.
>
> Signed-off-by: Yifan Zhang
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
> 1 file changed, 1
I demand that Christian König may or may not have written...
> Am 11.12.20 um 18:31 schrieb Darren Salt:
>< [SNIP]
>>> If that isn't the case use fls() to get the highest set bit < 13.
>> That suggests that it'll be easiest to clear each bit after the
>> corresponding size is checked, I think.
>
Am 14.12.20 um 20:17 schrieb Daniel Vetter:
I guess Christian didn't compile test amdkfd.
Scratching my head what has happened here. When I tested everything was
at least building fine.
Fixes: e11bfb99d6ec ("drm/ttm: cleanup BO size handling v3")
Cc: Christian König
Cc: Huang Rui (v1)
Am 2020-12-14 um 3:27 p.m. schrieb Christian König:
> Am 14.12.20 um 20:17 schrieb Daniel Vetter:
>> I guess Christian didn't compile test amdkfd.
>
> Scratching my head what has happened here. When I tested everything
> was at least building fine.
Looks like you were missing CONFIG_HSA_AMD in
[AMD Public Use]
Hi Simon,
Just to keep you updated, I've reproduced issue '[1] - Overlay plane: position
not updated when CRTC_X is negative' on Ubuntu using IGT. Seems to happen only
with smaller FBs (so far tried 24x24 and I can repro, but 300x300 is OK).
I'll look into fixing this.
Intended for devices which are misreporting available/supported BAR sizes.
This may be insufficient to identify some devices. The inclusion of the
reported BAR sizes bitmap is to assist with identification.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 43 --
1 file
This is to assist driver modules which do BAR resizing.
Signed-off-by: Darren Salt
---
drivers/pci/pci.h | 4
include/linux/pci.h | 9 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 640ae7d74fc3..0fa31ff3d4e4 100644
This is intended for devices which are known to work with BAR sizes other
than those which they advertise; usually larger.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/pci/setup-res.c| 4 ++--
include/linux/pci.h| 2 +-
3 files
Some cards don't advertise a BAR size which covers all of the VRAM.
Mine, a Sapphire RX 5600 XT Pulse, advertises only 256MB, 512MB and 1GB.
Despite this, it appears to work fine with the full 6GB visible via an 8GB
BAR.
v3: changed implementation due to changes in preceding patches.
v2:
This is coarse, applying to all dGPUs.
[v3] On -ENOSPC, include the size attempted in the logged error.
[v2] If there are no advertised sizes small enough, limit to the smallest
available.
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 32
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fde1dfdacd04..b4f3e5a2763e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++
This patch series improves the existing BAR resizing support in amdgpu. By
default, it will attempt to resize BAR0 for each supported dGPU present to
cover the VRAM.
Basic boot-time (or module load time) options to control this resizing are
implemented: one to control the maximum BAR size (may
This allows BAR0 resizing to be done for cards which don't advertise support
for a size large enough to cover the VRAM but which do advertise at least
one size larger than the default. For example, my RX 5600 XT, which
advertises 256MB, 512MB and 1GB.
[v5] Drop the retry loop…
[v4] Use bit ops
This is to assist driver modules which do BAR resizing.
Signed-off-by: Darren Salt
---
drivers/pci/pci.c | 1 +
drivers/pci/pci.h | 1 -
include/linux/pci.h | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index
[AMD Public Use]
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, December 15, 2020 12:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: fix regression in vbios reservation
On Fri, Dec 11, 2020 at 2:34 PM Souptick Joarder wrote:
>
> Kernel test robot throws below warning ->
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5:
> warning: no previous prototype for 'amdgpu_dm_crtc_atomic_set_property'
> [-Wmissing-prototypes]
>
On Mon, Dec 14, 2020 at 2:17 PM Daniel Vetter wrote:
>
> I guess Christian didn't compile test amdkfd.
>
> Fixes: e11bfb99d6ec ("drm/ttm: cleanup BO size handling v3")
> Cc: Christian König
> Cc: Huang Rui (v1)
> Cc: Daniel Vetter
> Cc: Felix Kuehling
> Cc: amd-gfx@lists.freedesktop.org
>
Am 2020-12-14 um 2:17 p.m. schrieb Daniel Vetter:
> I guess Christian didn't compile test amdkfd.
>
> Fixes: e11bfb99d6ec ("drm/ttm: cleanup BO size handling v3")
> Cc: Christian König
> Cc: Huang Rui (v1)
> Cc: Daniel Vetter
> Cc: Felix Kuehling
> Cc: amd-gfx@lists.freedesktop.org
>
On 15/12/20 3:50 am, Aurabindo Pillai wrote:
> [Why]
> If experimental freesync video mode module parameter is enabled, add
> few extra display modes into the driver's mode list corresponding to common
> video frame rates. When userspace sets these modes, no modeset will be
> performed (if
The series is
Reviewed-by: Felix Kuehling
Am 2020-12-12 um 10:45 a.m. schrieb Hawking Zhang:
> amdgpu_ih_regs holds all the registers for
> an ih ring
>
> Signed-off-by: Hawking Zhang
> Reviewed-by: Christian König
> Acked-by: Felix Kuehling
> Reviewed-by: Dennis Li
> Reviewed-by: Feifei Xu
Applied. Thanks!
Alex
On Mon, Dec 14, 2020 at 3:18 AM Souptick Joarder wrote:
>
> Kernel test robot throws below warning ->
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c:46:6:
> warning: no previous prototype for 'dccg21_update_dpp_dto'
> [-Wmissing-prototypes]
>
> Adding
On Mon, Dec 14, 2020 at 06:52:25PM +0100, Ard Biesheuvel wrote:
> This reverts commit c38d444e44badc557cf29fdfdfb823604890ccfa.
>
> Simply disabling -mgeneral-regs-only left and right is risky, given that
> the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
> and GCC is known
On Fri, Dec 11, 2020 at 11:49 AM Borislav Petkov wrote:
>
> Hi,
>
> patch in $Subject breaks booting on a laptop here, GPU details are
> below. The machine stops booting right when it attempts to switch modes
> during boot, to a higher mode than the default VGA one. Machine doesn't
> ping and is
This reverts commit 8353d30e747f4e5cdd867c6b054dbb85cdcc76a9.
This causes a hang on a carrizo based laptop. Revert until we can fix
it properly.
Cc: Borislav Petkov
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Changes in V3
=
1) Add freesync video modes based on preferred modes:
* Cache base freesync video mode during the first iteration to avoid
iterating over modelist again later.
* Add mode for 60 fps videos
2) Skip modeset for front porch change
* Fixes for bug exposed by caching
[Why]
Inorder to enable freesync video mode, driver adds extra
modes based on preferred modes for common freesync frame rates.
When commiting these mode changes, a full modeset is not needed.
If the change in only in the front porch timing value, skip full
modeset and continue using the same
[Why]
Adds a module parameter to enable experimental freesync video mode modeset
optimization. Enabling this mode allows the driver to skip a full modeset when
freesync compatible modes are requested by the userspace. This paramters also
adds some standard modes based on the connected monitor's
[Why]
If experimental freesync video mode module parameter is enabled, add
few extra display modes into the driver's mode list corresponding to common
video frame rates. When userspace sets these modes, no modeset will be
performed (if current mode was one of freesync modes or the base freesync
On Mon, Dec 14, 2020 at 04:53:39PM -0500, Alex Deucher wrote:
> This reverts commit 8353d30e747f4e5cdd867c6b054dbb85cdcc76a9.
>
> This causes a hang on a carrizo based laptop. Revert until we can fix
> it properly.
>
> Cc: Borislav Petkov
Reported-by: me
> Signed-off-by: Alex Deucher
> ---
This patch is to correct the sensor value of power for vangogh.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
On Tuesday, December 15th, 2020 at 5:09 AM, Cornij, Nikola
wrote:
> [AMD Public Use]
>
> Hi Simon,
>
> Just to keep you updated, I've reproduced issue '[1] - Overlay plane:
> position not updated when CRTC_X is negative' on Ubuntu using IGT.
> Seems to happen only with smaller FBs (so far tried
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
Best Regards
Kenneth
-Original Message-
From: Gao, Likun
Sent: Monday, December 14, 2020 3:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Feng, Kenneth ; Gao, Likun
Am 11.12.20 um 18:31 schrieb Darren Salt:
[SNIP]
If that isn't the case use fls() to get the highest set bit < 13.
That suggests that it'll be easiest to clear each bit after the corresponding
size is checked, I think.
Ok, well you don't seem to understand my constrain here: Never check
Am 13.12.20 um 23:53 schrieb Darren Salt:
This allows BAR0 resizing to be done for cards which don't advertise support
for a size large enough to cover the VRAM but which do advertise at least
one size larger than the default. For example, my RX 5600 XT, which
advertises 256MB, 512MB and 1GB.
Kernel test robot throws below warning ->
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c:46:6:
warning: no previous prototype for 'dccg21_update_dpp_dto'
[-Wmissing-prototypes]
Adding prototype for dccg21_update_dpp_dto().
Reported-by: kernel test robot
Signed-off-by: Souptick
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