Fix the following checkincludes.pl warning:
./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
35 #include "dce110_hw_sequencer.h"
69 #include "dce110_hw_sequencer.h"
Signed-off-by: Wan Jiabing
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 -
1 file
* Alex Sierra [210607 16:43]:
> From: Ralph Campbell
>
> There are several places where ZONE_DEVICE struct pages assume a reference
> count == 1 means the page is idle and free. Instead of open coding this,
> add a helper function to hide this detail.
>
> Signed-off-by: Ralph Campbell
> ---
>
On Fri, Jun 04, 2021 at 12:38:07PM -0700, Joe Perches wrote:
> The __assign_str macro has an unusual ending semicolon but the vast
> majority of uses of the macro already have semicolon termination.
>
> $ git grep -P '\b__assign_str\b' | wc -l
> 551
> $ git grep -P '\b__assign_str\b.*;' | wc -l
>
[AMD Official Use Only]
Patch is
Reviewed-by: Boyuan Zhang
Thanks,
Boyuan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: June 7, 2021 4:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/vcn: drop gfxoff control for VCN2+
Device generic type case added for migrate_vma_pages and
migrate_vma_check_page helpers.
Both, generic and private device types have the same
conditions to decide to migrate pages from/to device
memory.
Signed-off-by: Alex Sierra
---
mm/migrate.c | 8
1 file changed, 4 insertions(+), 4
From: Ralph Campbell
ZONE_DEVICE struct pages have an extra reference count that complicates the
code for put_page() and several places in the kernel that need to check the
reference count to see that a page is not being used (gup, compaction,
migration, etc.). Clean up the code so the reference
Generic device type memory on VRAM to RAM migration,
has similar access as System RAM from the CPU. This flag sets
the source from the sender. Which in Generic type case,
should be set as SYSTEM.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
---
Two helpers added. One checks if zone device page is generic
type. The other if page is either private or generic type.
Signed-off-by: Alex Sierra
---
include/linux/mm.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index
When CPU is connected throug XGMI, it has coherent
access to VRAM resource. In this case that resource
is taken from a table in the device gmc aperture base.
This resource is used along with the device type, which could
be DEVICE_PRIVATE or DEVICE_GENERIC to create the device
page map region.
Add MEMORY_DEVICE_GENERIC case to free_zone_device_page
callback.
Device generic type memory case is now able to free its
pages properly.
Signed-off-by: Alex Sierra
---
mm/memremap.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/mm/memremap.c b/mm/memremap.c
index
The AMD architecture for the Frontier supercomputer will
have device memory which can be coherently accessed by
the CPU. The system BIOS advertises this memory as SPM
(special purpose memory) in the UEFI system address map.
The AMDGPU driver needs to be able to lookup this resource
in order to
v1:
https://lore.kernel.org/linux-mm/20210529064022.gb15...@lst.de/T/
v2:
This patch series version has merged "[RFC PATCH v3 0/2]
mm: remove extra ZONE_DEVICE struct page refcount" patch series made by
Ralph Campbell. It also applies at the top of these series, our changes
to support device
From: Ralph Campbell
There are several places where ZONE_DEVICE struct pages assume a reference
count == 1 means the page is idle and free. Instead of open coding this,
add a helper function to hide this detail.
Signed-off-by: Ralph Campbell
---
fs/dax.c| 4 ++--
fs/ext4/inode.c
Drop disabling of gfxoff during VCN use. This allows gfxoff
to kick in and potentially save power if the user is not using
gfx for color space conversion or scaling.
VCN1.0 had a bug which prevented it from working properly with
gfxoff, so we disabled it while using VCN. That said, most apps
Am 07.06.21 um 21:39 schrieb Rohit Khaire:
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 +++-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git
need to load xgmi ta for aldebaran sriov vf.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 47ceb783e2a5..29c365160043
On 2021-06-07 2:19 p.m., Sean Paul wrote:
> On Tue, May 18, 2021 at 2:58 PM Rodrigo Siqueira
> wrote:
>>
>> On 05/14, Mark Yacoub wrote:
>>> On Fri, May 14, 2021 at 12:31 PM Mark Yacoub wrote:
On Fri, May 14, 2021 at 11:28 AM Harry Wentland
wrote:
>
> On 2021-05-14 7:47
[AMD Public Use]
OK.
I will just skip the function call for SRIOV and resend.
Rohit
-Original Message-
From: Koenig, Christian
Sent: June 7, 2021 12:42 PM
To: Kuehling, Felix ; Khaire, Rohit
; amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ; Deng,
Emily ; Liu,
On Mon, Jun 7, 2021 at 4:54 PM Ernst Sjöstrand wrote:
>
> Hi,
>
> doesn't this patch apply the change to VCN1.0 also, which has that bug you
> mentioned?
>
Nope. VCN1.0 uses vcn_v1_0_idle_work_handler() and
vcn_v1_0_ring_begin_use() as they have other special handling in
addition to this.
Hi,
doesn't this patch apply the change to VCN1.0 also, which has that bug you
mentioned?
Regards
//Ernst
Den mån 7 juni 2021 kl 22:29 skrev Alex Deucher :
> Drop disabling of gfxoff during VCN use. This allows gfxoff
> to kick in and potentially save power if the user is not using
> gfx for
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: "Dingchen (David) Zhang"
[WHY]
- Commit from userspace could cause link stream to disable and hdcp
auth to reset when the HDCP has already been enabled at the moment.
CP should fall back to DESIRED from ENABLED in such cases.
- This change was previously reverted due to a regression
From: Aric Cyr
[Why]
When calculating recout width for an MPO plane on a mode that's using
ODM combine, driver can calculate a negative value, resulting in a
crash.
[How]
For negative widths, use zero such that validation will prune the
configuration correctly and disallow MPO.
Signed-off-by:
From: Wesley Chalmers
[WHY]
DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when
changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
From: Wyatt Wood
Signed-off-by: Wyatt Wood
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Roy Chan
[Why]
Found a use case (IPKVM) that DP-VGA active dongle does
not return any EDID and the mentioned commit broke it.
[How]
This reverts "Disconnect non-DP with no EDID"
Signed-off-by: Roy Chan
Reviewed-by: Chris Park
Acked-by: Stylon Wang
---
From: Fangzhi Zuo
[Why & How]
Add debugfs entry to force dsc decoding at PCON when DSC capable
external RX is connected. In such case, it is free to test DSC
decoding at external RX or at PCON.
Signed-off-by: Fangzhi Zuo
Reviewed-by: Hersen Wu
Acked-by: Stylon Wang
---
From: Wesley Chalmers
[WHY]
HW has handed down a new sequence that requires access to these
registers.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 26 ++
From: Aric Cyr
[Why]
Rearranging pipes with multiple displays and multiple planes cannot be
done atomically and requires a much improved sequence to deal with it.
[How]
To workaround such issues, prefer avoid pipe-split policy for
multidisplay scenarios.
Signed-off-by: Aric Cyr
Reviewed-by:
From: Wesley Chalmers
[WHY]
HW has handed down a new sequence which requires access to the FIFO
ERRDET SW Override register.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 10 +++
From: Eric Bernstein
[Why]
There is an assert in cases where transition from ODM 2:1
to ODM 1:1 (bypass)
[How]
Remove assert since this case is now valid.
Update diags tests for ODM transitions.
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
From: Wesley Chalmers
[WHY]
For DCN30 and later, there is no data in DML arrays indexed by state at
index num_states.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 14 +++---
1 file
From: Vladimir Stempen
[why]
When OS overrides training link training parameters
for MST device to SST mode, MST resources are not
released and leak of the resource may result crash and
incorrect MST discovery during following hot plugs.
[how]
Retaining sink object to be reused by SST link and
From: Mikita Lipski
[why]
Allow specifying which panel to take PSR Residency
measurements from.
[how]
Pass panel instance to DMUB through GPINT in the upper
8 bits of the parameter.
Signed-off-by: Mikita Lipski
Reviewed-by: Nicholas Kazlauskas
Acked-by: Stylon Wang
---
From: Jimmy Kizito
[Why & How]
Add functionality useful for DP equalization phase of link training to
public interface.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 22 +--
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Roman Li
[Why]
We update scaling settings when scaling mode has been changed.
However when changing mode from native resolution the scaling mode previously
set gets ignored.
[How]
Perform scaling settings update on modeset.
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
From: Meenakshikumar Somasundaram
[Why & How]
SET_CONFIG transactions with DMUB is not used and removed.
Signed-off-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4
1 file changed, 4 deletions(-)
diff
From: Jayendran Ramani
[How]
Add call to get the last used VTOTAL from DC
Signed-off-by: Jayendran Ramani
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 42 +++
drivers/gpu/drm/amd/display/dc/dc_stream.h| 4 ++
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Nikola Cornij
[why]
DSCCLK validation is not necessary because DSCCLK is derrived from
DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too.
Doing DSCLK validation in addition to DISPCLK leads to modes being
wrongly rejected when DSCCLK was incorrectly set outside of DML.
From: Wenjing Liu
[why]
Some DPRX will issue CP_IRQ when user disconnects a display
that has been authenticated.
Since display is being disconnecting dpcd read will fail.
This will cause us to attempt HDCP retry on disconnection.
We are adding a 100ms delay before retry.
So we will only start
From: "JinZe.Xu"
[Why]
This disablement would be specific for Nav10 and shouldn’t be propagated to the
other programs.
[How]
Power gating is controlled by driver.
Signed-off-by: JinZe.Xu
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
.../drm/amd/display/dc/dcn302/dcn302_hwseq.c | 34
From: Mikita Lipski
[why]
Updating PSR interfaces to allow PSR enablement
per eDP panel.
[how]
- Copying PSR command structures to DC
- Changing function interfaces to pass panel instance
- Communicating with DMUB per link instead of assuming
to use a single one
-Iterating through all PSR
From: Jimmy Kizito
[Why & How]
Add support for transmitting training pattern sequences for links whose
encoders have been dynamically assigned.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 ++-
1
From: Ilya Bakoulin
[Why]
This change was found to break some high-refresh modes. Reverting
to unblock mainline.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Sung Lee
Acked-by: Stylon Wang
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 78 +++
From: Jake Wang
[Why]
During DCC on/off, stutter period is calculated before DCC has fully
transitioned.
This results in incorrect stutter period calculation.
[How]
Trigger a full update when DCC changes between on/off.
Signed-off-by: Jake Wang
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC v3.2.139
* FW v0.0.69
* Improvements across DP, eDP, DMUB, MPO, etc
--
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.68
Aric Cyr (4):
drm/amd/display: Change default policy for MPO with
Ah, good point. In this case we should probably rather save than sorry.
Then I suggest to clean up this patch, repeating the psp_reg_program()
and error message is pretty horrible coding style.
Christian.
Am 07.06.21 um 18:36 schrieb Felix Kuehling:
With SRIOV, the interrupt routing is
With SRIOV, the interrupt routing is setup by the hypervisor driver. We
need the secondary IH rings in case the hypervisor enabled rerouting of
page fault interrupts. I'm not sure what the hypervisor driver does today.
Regards,
Felix
Am 2021-06-07 um 12:29 p.m. schrieb Christian König:
>
Am 07.06.21 um 08:47 schrieb Werner Sembach:
Am 04.06.21 um 19:30 schrieb Ville Syrjälä:
On Fri, Jun 04, 2021 at 07:17:23PM +0200, Werner Sembach wrote:
This commits implements the "active bpc" drm property for the Intel
GPU driver.
Signed-off-by: Werner Sembach
---
That's a workaround for bare metal and as far as I know doesn't apply to
SRIOV.
We only need the additional IH rings for page fault handling or log
handling and as far as I know that is incompatible with SRIOV for the
moment. But Felix might have some more updates on this.
So as long as we
[AMD Public Use]
The hash is 5ea6f9c
Rohit
-Original Message-
From: Koenig, Christian
Sent: June 7, 2021 11:58 AM
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org;
Deucher, Alexander ; Zhang, Hawking
; Deng, Emily ; Liu, Monk
; Zhou, Peng Ju ; Chen, Horace
Cc: Ming, Davis
Do you have the hash for this commit?
Thanks,
Christian.
Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
[AMD Public Use]
We don't need RING1 and RING2 functionality for SRIOV afaik.
But looking at the description of the original commit message it affects RING0
too?
" drm/amdgpu: add timeout
[Public]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Xiaomeng Hou
Sent: Monday, June 7, 2021 8:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Hou, Xiaomeng (Matthew)
; Wang, Kevin(Yang)
Subject: [PATCH] drm/amd/pm: fix warning reported by
[AMD Public Use]
We don't need RING1 and RING2 functionality for SRIOV afaik.
But looking at the description of the original commit message it affects RING0
too?
" drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)
outstanding log reaches threshold will trigger IH
Great, thanks for all the feedback Lijo. Out of the new bit definitions in
amdgpu_smu.h are there any that currently exist that are more applicable for
these mappings? *_THM_GFX and *_THM_SOC only exist in VanGogh and Renoir. With
the expansion of the MEM and LIQUID bits there is not enough
On 6/7/2021 7:14 PM, Graham Sider wrote:
Perform dependent to independent throttle status translation
for vangogh.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 38 ++-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git
Why are the ring 1&2 enabled on SRIOV in the first place?
Christian.
Am 07.06.21 um 16:23 schrieb Rohit Khaire:
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
1
Hey, MR created at
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/172, please
help review.
Andrey
On 2021-06-03 10:26 p.m., Alex Deucher wrote:
Code review happens on gitlab now for libdrm.
Alex
On Thu, Jun 3, 2021 at 6:02 PM Grodzovsky, Andrey
wrote:
Is libdrm on gitlab ? I
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
Add the parameter table_freed description on function description.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index
[Public]
Okay. I will update the change as you suggested.
Thanks,
Zhigang
-Original Message-
From: Zhang, Hawking
Sent: June 7, 2021 9:52 AM
To: Luo, Zhigang ; Liu, Shaoyun ;
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and
[AMD Official Use Only]
You can call psp_init_ta_microcode directly in sriov vf case so you don't need
to initialize unnecessary psp firmware structures.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Luo, Zhigang
Sent: Thursday, June 3, 2021 23:32
To: Liu, Shaoyun ;
Perform dependent to independent throttle status translation
for renoir.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 +++
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
Perform dependent to independent throttle status translation
for sienna cichlid.
Signed-off-by: Graham Sider
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 34 ---
1 file changed, 29 insertions(+), 5 deletions(-)
diff --git
Perform dependent to independent throttle status translation
for vangogh.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 38 ++-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
Perform dependent to independent throttle status translation
for aldebaran.
Signed-off-by: Graham Sider
---
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 27 +++
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
Perform dependent to independent throttle status translation
for navi1x.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
Add new defines for thermal throttle status bits which are ASIC
independent. This bit field will be visible to userspace via
gpu_metrics alongside the previous ASIC dependent bit fields. Seperated
into four 16-bit types: power throttlers, current throttlers,
temperature, other.
Signed-off-by:
Perform dependent to independent throttle status translation
for arcturus.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 ---
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
Defines smu_cmn_get_indep_throttler_status which performs ASIC
independent translation given a corresponding lookup table.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 13 +
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4
2 files changed, 17
This patch set adds support for a new ASIC independant u64 throttler
status field (indep_throttle_status). Piggybacks off the
gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to
v2_2) to add field.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/include/kgd_pp_interface.h|
That won't work either.
We still need to initialize the control registers and tell the hardware
that we have properly setup the ring buffers.
Just add the error message to psp_reg_program() instead of duplicating
that over and over again.
Christian.
Am 07.06.21 um 19:33 schrieb Khaire,
Am 2021-06-04 um 10:54 p.m. schrieb Wan Jiabing:
> kfd_svm.h is included duplicately in commit 42de677f7
> ("drm/amdkfd: register svm range").
>
> After checking possible related header files,
> remove the former one to make the code format more reasonable.
>
> Signed-off-by: Wan Jiabing
Applied. Thanks!
Alex
On Mon, Jun 7, 2021 at 7:58 AM Colin King wrote:
>
> From: Colin Ian King
>
> There are two spelling mistakes in dml_print messages, fix these and
> clear up checkpatch warning on overly wide line length.
>
> Signed-off-by: Colin Ian King
> ---
>
Applied. Thanks!
Alex
On Mon, Jun 7, 2021 at 6:46 AM Christian König
wrote:
>
> Am 05.06.21 um 11:06 schrieb Christophe JAILLET:
> > s/than/then/
> >
> > Signed-off-by: Christophe JAILLET
>
> Acked-by: Christian König
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
> > 1 file
Applied. Thanks!
Alex
On Mon, Jun 7, 2021 at 6:27 AM Jiapeng Chong
wrote:
>
> Clean up the following includecheck warning:
>
> ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:
> dce110_hw_sequencer.h is included more than once.
>
> No functional change.
>
> Reported-by: Abaci
On Sat, Jun 5, 2021 at 8:31 AM Bernard Zhao wrote:
>
> remove no need variable, just return the DC_OK
>
> Signed-off-by: Bernard Zhao
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git
From: Po-Ting Chen
[Why]
To support a new visual confirm mode: swizzle to show the specific
color at the screen border according to different surface swizzle mode.
Currently we only support the Linear mode with red color.
Signed-off-by: Po-Ting Chen
---
From: Evgenii Krasnikov
[WHY]
Currently there is no way to visually identify if there is one or more
layers presented fullscreen on the display
[HOW]
Add new visual confirm colors in get_surface_visual_confirm_color for
planes with layer_index > 0
Signed-off-by: Evgenii Krasnikov
Reviewed-by:
From: Wyatt Wood
[Why + How]
Visual confirm has no asic-specific logic,
so we can refactor and unify these functions
that are currently spread out across multiple
dcn files.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
This will allow
Kernel test robot throws warning ->
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2:
warning: variable 'member_type' is used uninitialized whenever switch
default is taken [-Wsometimes-uninitialized]
default:
^~~
Am 07.06.21 um 14:27 schrieb Tiezhu Yang:
radeon_suspend_kms() puts the hw in the suspend state (all asics),
it should always call radeon_suspend_kms() in radeon_pci_shutdown(),
this is a normal cleanup process to avoid more operations on radeon,
just remove #ifdef CONFIG_PPC64 and the related
From: Rodrigo Siqueira
[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]
A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:
drm/amd/display: Fix two cursor duplication when using overlay
(read the commit message for more details)
After
From: Bindu Ramamurthy
[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]
[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.
[How]
As the pstate status is applicable for non
From: Victor Zhao
[ Upstream commit 2370eba9f552eaae3d8aa1f70b8e9eec5c560f9e ]
[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.
[How]
Use a psp wptr cache machanism to aovid the change made by attack.
v2: unify
From: Roman Li
[ Upstream commit c5699e2d863f58221044efdc3fa712dd32d55cde ]
[Why]
On resume we perform DMUB hw_init which allocates memory:
dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc
That results in memory leak in suspend/resume scenarios.
[How]
Allocate memory for the DC wrapper
From: Rodrigo Siqueira
[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]
A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:
drm/amd/display: Fix two cursor duplication when using overlay
(read the commit message for more details)
After
From: Jiansong Chen
[ Upstream commit 5cfc912582e13b05d71fb7acc4ec69ddfa9af320 ]
1. eliminate potential array index out of bounds.
2. return meaningful value for failure.
Signed-off-by: Jiansong Chen
Reviewed-by: Jack Gui
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Bindu Ramamurthy
[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]
[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.
[How]
As the pstate status is applicable for non
From: Victor Zhao
[ Upstream commit 2370eba9f552eaae3d8aa1f70b8e9eec5c560f9e ]
[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.
[How]
Use a psp wptr cache machanism to aovid the change made by attack.
v2: unify
From: Roman Li
[ Upstream commit c5699e2d863f58221044efdc3fa712dd32d55cde ]
[Why]
On resume we perform DMUB hw_init which allocates memory:
dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc
That results in memory leak in suspend/resume scenarios.
[How]
Allocate memory for the DC wrapper
From: Rodrigo Siqueira
[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]
A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:
drm/amd/display: Fix two cursor duplication when using overlay
(read the commit message for more details)
After
From: Jiansong Chen
[ Upstream commit 5cfc912582e13b05d71fb7acc4ec69ddfa9af320 ]
1. eliminate potential array index out of bounds.
2. return meaningful value for failure.
Signed-off-by: Jiansong Chen
Reviewed-by: Jack Gui
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Bindu Ramamurthy
[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]
[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.
[How]
As the pstate status is applicable for non
On Fri, Jun 4, 2021 at 4:17 PM Harry Wentland wrote:
>
>
>
> On 2021-06-04 1:01 p.m., Mark Yacoub wrote:
> > From: Mark Yacoub
> >
> > For each CRTC state, check the size of Gamma and Degamma LUTs so
> > unexpected and larger sizes wouldn't slip through.
> >
> > TEST:
Am 07.06.21 um 16:21 schrieb Eric Huang:
Add the parameter table_freed description on function description.
Signed-off-by: Eric Huang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On Mon, Jun 7, 2021 at 8:30 AM Christian König wrote:
>
> Am 07.06.21 um 14:27 schrieb Tiezhu Yang:
> > radeon_suspend_kms() puts the hw in the suspend state (all asics),
> > it should always call radeon_suspend_kms() in radeon_pci_shutdown(),
> > this is a normal cleanup process to avoid more
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