[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.
[How]
It could be directly read by MMIO.
v2: Add additional check to prevent carryover issue.
v3: Only check for carryover for once to prevent performance issue.
Signed-off-by: YuBiao Wang
Acked-by: Horace
Hi,
On 29/06/2021 15:58, Thomas Zimmermann wrote:
> Print the name of the DRM driver when taking over fbdev devices. Makes
> the output to dmesg more consistent. Note that the driver name is only
> used for printing a string to the kernel log. No UAPI is affected by this
> change.
>
>
[AMD Official Use Only]
Ping
--
BW
Pengju Zhou
> -Original Message-
> From: Peng Ju Zhou
> Sent: Friday, June 25, 2021 2:44 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily ; Zhou, Peng Ju
>
> Subject:
On 6/29/2021 1:12 PM, Christian König wrote:
Am 29.06.21 um 09:55 schrieb Nirmoy Das:
VM code should not be responsible for freeing pasid as pasid
gets allocated outside of VM code, before initializing a vm.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8
Am 29.06.21 um 11:47 schrieb YuBiao Wang:
[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.
[How]
It could be directly read by MMIO.
v2: Add additional check to prevent carryover issue.
Signed-off-by: YuBiao Wang
---
Thanks for the detailed commit message :)
Acked-by: Nirmoy Das
On 6/29/2021 1:15 AM, Oak Zeng wrote:
The ttm caching flags (ttm_cached, ttm_write_combined etc) are
used to determine a buffer object's mapping attributes in both
CPU page table and GPU page table (when that buffer is also
On Tue, Jun 29, 2021 at 9:58 PM Thomas Zimmermann wrote:
>
> Print the name of the DRM driver when taking over fbdev devices. Makes
> the output to dmesg more consistent. Note that the driver name is only
> used for printing a string to the kernel log. No UAPI is affected by this
> change.
>
>
Applied. Thanks!
Alex
On Tue, Jun 29, 2021 at 11:10 AM Harry Wentland wrote:
>
> On 2021-06-28 9:27 p.m., Reka Norman wrote:
> > Setting CONFIG_FRAME_WARN=0 should disable 'stack frame larger than'
> > warnings. This is useful for example in KASAN builds. Make the dml
> > Makefile respect this
[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.
[How]
It could be directly read by MMIO.
v2: Add additional check to prevent carryover issue.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++--
1 file changed, 11
[AMD Official Use Only]
Please do not use "//" in linux kernel patch , use "/* */" instead
After this part fixed the patch is : Reviewed-by: Monk Liu
Thanks
--
Monk Liu | Cloud-GPU Core team
--
-Original
On 6/29/2021 1:05 PM, Christian König wrote:
Am 29.06.21 um 09:36 schrieb Nirmoy Das:
Return early for non-TTM_PL_TT BOs so that we don't pass
wrong pointer to amdgpu_gtt_mgr_has_gart_addr() which assumes
ttm_resource argument to be TTM_PL_TT type BO's.
v2: merge if-conditions
Signed-off-by:
Am 29.06.21 um 09:36 schrieb Nirmoy Das:
Return early for non-TTM_PL_TT BOs so that we don't pass
wrong pointer to amdgpu_gtt_mgr_has_gart_addr() which assumes
ttm_resource argument to be TTM_PL_TT type BO's.
v2: merge if-conditions
Signed-off-by: Nirmoy Das
---
On 6/25/2021 1:42 PM, Evan Quan wrote:
Due to the structure layout change: "uint32_t ThrottlerStatus" -> "
uint8_t ThrottlingPercentage[THROTTLER_COUNT]".
Change-Id: Id5c148b0584d972ae73fb9d7347a312944cec13d
Signed-off-by: Evan Quan
---
.../pm/inc/smu11_driver_if_sienna_cichlid.h | 63
Applied. Thanks!
Alex
On Tue, Jun 29, 2021 at 7:42 AM Christian König
wrote:
>
> Am 29.06.21 um 13:44 schrieb Jing Xiangfeng:
> > radeon_user_framebuffer_create() misses to call drm_gem_object_put() in
> > an error path. Add the missed function call to fix it.
> >
> > Signed-off-by: Jing
On Fri, Jun 25, 2021 at 2:44 AM Peng Ju Zhou wrote:
>
> From: "Emily.Deng"
>
> After FLR, the msix will be cleared, so need to re-enable it.
Do we need to store whether we enabled msix in the first place and
then decide whether to enable it again in this case?
Alex
>
> Signed-off-by:
Am 29.06.21 um 09:49 schrieb Nirmoy Das:
Replace idr with xarray as we actually need hash functionality.
Cleanup code related to vm pasid by adding helper function.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 136 ++---
On 6/29/2021 1:06 PM, Christian König wrote:
Am 29.06.21 um 09:36 schrieb Nirmoy Das:
Be more defensive and raise error on wrong mem_type
argument in amdgpu_gtt_mgr_has_gart_addr().
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +-
1 file changed, 5
Am 29.06.21 um 13:44 schrieb Jing Xiangfeng:
radeon_user_framebuffer_create() misses to call drm_gem_object_put() in
an error path. Add the missed function call to fix it.
Signed-off-by: Jing Xiangfeng
I'm pretty sure that I already reviewed the same patch a few weeks ago,
but it looks like
Applied. Thanks.
Alex
On Mon, Jun 28, 2021 at 6:53 AM Lukas Bulwahn wrote:
>
> Commit 6b36fa6143f6 ("drm/amdgpu: add umc v8_7_0 IP headers") adds the new
> file ./drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_7_0_sh_mask.h with
> DOS line endings, which is very uncommon for the kernel
Am 29.06.21 um 09:36 schrieb Nirmoy Das:
Be more defensive and raise error on wrong mem_type
argument in amdgpu_gtt_mgr_has_gart_addr().
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
Hi Christian,
Could you please pick this up for drm-misc-next or fixes ?
Regards,
Nirmoy
On 6/29/2021 1:44 PM, Nirmoy Das wrote:
Return early for non-TTM_PL_TT BOs so that we don't pass
wrong pointer to amdgpu_gtt_mgr_has_gart_addr() which assumes
ttm_resource argument to be TTM_PL_TT
[AMD Official Use Only]
Acked-by: Horace Chen
-Original Message-
From: YuBiao Wang
Sent: Tuesday, June 29, 2021 6:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Quan, Evan
; Chen, Horace ; Tuikov, Luben
; Koenig, Christian ; Deucher,
Alexander ; Xiao, Jack ;
On 6/29/2021 1:10 PM, Christian König wrote:
Am 29.06.21 um 09:49 schrieb Nirmoy Das:
Replace idr with xarray as we actually need hash functionality.
Cleanup code related to vm pasid by adding helper function.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 136
Print the name of the DRM driver when taking over fbdev devices. Makes
the output to dmesg more consistent. Note that the driver name is only
used for printing a string to the kernel log. No UAPI is affected by this
change.
Signed-off-by: Thomas Zimmermann
---
Applied. Thanks!
Alex
On Fri, Jun 25, 2021 at 3:28 AM Mark Yacoub wrote:
>
> Fixes Commit a46b6bd5 (drm/amd/display: Verify Gamma & Degamma LUT sizes
> in amdgpu_dm_atomic_check)
>
> Tested on Zork: IGT:kms_color
>
> Signed-off-by: Mark Yacoub
> ---
>
Return early for non-TTM_PL_TT BOs so that we don't pass
wrong pointer to amdgpu_gtt_mgr_has_gart_addr() which assumes
ttm_resource argument to be TTM_PL_TT type BO's.
v3: remove extra braces.
v2: merge if-conditions.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
On 2021-06-28 9:27 p.m., Reka Norman wrote:
> Setting CONFIG_FRAME_WARN=0 should disable 'stack frame larger than'
> warnings. This is useful for example in KASAN builds. Make the dml
> Makefile respect this config.
>
> Fixes the following build warnings with CONFIG_KASAN=y and
>
Use new helper function amdgpu_vm_set_pasid() to
assign vm pasid value. This also ensures that we don't free
a pasid from vm code as pasids are allocated somewhere else.
Signed-off-by: Nirmoy Das
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 13 -
LGTM
Acked-by: Nirmoy Das
On 6/29/2021 3:58 PM, Thomas Zimmermann wrote:
Print the name of the DRM driver when taking over fbdev devices. Makes
the output to dmesg more consistent. Note that the driver name is only
used for printing a string to the kernel log. No UAPI is affected by this
On Tue, Jun 29, 2021 at 3:57 PM Ketsui wrote:
>
> I have the 3200G I'm still getting this error with that version.
I think the 3200G may be a raven or raven2 variant rather than
picasso. Can you try the latest firmware from upstream:
Am 29.06.21 um 17:19 schrieb Nirmoy Das:
Replace idr with xarray as we actually need hash functionality.
Cleanup code related to vm pasid by adding helper function.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 149 -
I have the 3200G I'm still getting this error with that version.
[ +23.754701] amdgpu :08:00.0: amdgpu: [gfxhub0] retry page fault
(src_id:0 ring:0 vmid:2 pasid:32773, for process mpv pid 5016 thread
mpv:cs0 pid 5064)
[ +0.17] amdgpu :08:00.0: amdgpu: in page starting at address
Am 2021-06-29 um 2:02 p.m. schrieb Alex Sierra:
> During GPU page table invalidation with xnack off, new ranges
> split may occur concurrently in the same prange. Creating a new
> child per split. Each child should also increment its
> invalid counter, to assure GPU page table updates in these
>
Replace idr with xarray as we actually need hash functionality.
Cleanup code related to vm pasid by adding helper function.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 149 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +-
2 files changed, 73
On 2021-06-29 10:14 a.m., Alex Deucher wrote:
> Was missing. Add it.
>
> Fixes: 6b36fa6143f6ca ("drm/amdgpu: add umc v8_7_0 IP headers")
> Signed-off-by: Alex Deucher
Reviewed-by: Harry Wentland
Harry
> ---
> .../include/asic_reg/umc/umc_8_7_0_sh_mask.h | 21 +++
> 1 file
pgmap owner member at the svm migrate init could be referenced
to either adev or hive, depending on device topology.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 +++---
drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 3 +++
2 files
This is for debug purposes only.
It conditionally generates partial migrations to test mixed
CPU/GPU memory domain pages in a prange easily.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 14 ++
1 file changed, 14 insertions(+)
Invalid pages can be the result of pages that have been migrated
already due to copy-on-write procedure or pages that were never
migrated to VRAM in first place. This is not an issue anymore,
as pranges now support mixed memory domains (CPU/GPU).
Signed-off-by: Alex Sierra
Reviewed-by: Felix
The parameter is used in the dev_private_owner to decide if device
pages in the range require to be migrated back to system memory, based
if they are or not in the same memory domain.
In this case, this reference could come from the same memory domain
with devices connected to the same hive.
Get the proper owner reference for amdgpu_hmm_range_get_pages function.
This is useful for partial migrations. To avoid migrating back to
system memory, VRAM pages, that are accessible by all devices in the
same memory domain.
Ex. multiple devices in the same hive.
Signed-off-by: Alex Sierra
Now that prange could have mixed domains (VRAM or SYSRAM),
actual_loc nor svm_bo can not be used to check its current
domain and eventually get its pfns to map them in GPU.
Instead, pfns from both domains, are now obtained from
hmm_range_fault through amdgpu_hmm_range_get_pages
call. This is done
Migration skipped for pages that are already in VRAM
domain. These could be the result of previous partial
migrations to SYS RAM, and prefetch back to VRAM.
Ex. Coherent pages in VRAM that were not written/invalidated after
a copy-on-write.
Signed-off-by: Alex Sierra
---
svm_range_prefault is called right before migrations to VRAM,
to make sure pages are resident in system memory before the migration.
With partial migrations, this reference is used by hmm range get pages
to avoid migrating pages that are already in the same VRAM domain.
Signed-off-by: Alex Sierra
[Why]
svm ranges can have mixed pages from device or system memory.
A good example is, after a prange has been allocated in VRAM and a
copy-on-write is triggered by a fork. This invalidates some pages
inside the prange. Endding up in mixed pages.
[How]
By classifying each page inside a prange,
During GPU page table invalidation with xnack off, new ranges
split may occur concurrently in the same prange. Creating a new
child per split. Each child should also increment its
invalid counter, to assure GPU page table updates in these
ranges.
Signed-off-by: Alex Sierra
---
Each zone-device page holds a reference to the SVM BO that manages its
backing storage. This is necessary to correctly hold on to the BO in
case zone_device pages are shared with a child-process.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 10 --
Was missing. Add it.
Fixes: 6b36fa6143f6ca ("drm/amdgpu: add umc v8_7_0 IP headers")
Signed-off-by: Alex Deucher
---
.../include/asic_reg/umc/umc_8_7_0_sh_mask.h | 21 +++
1 file changed, 21 insertions(+)
diff --git
From: Wesley Chalmers
This reverts commit 06a2bd7ae7238cf31faeb2216c0e8a3d9b1bedfb
Some displays are not lighting up when put in LTTPR Transparent Mode
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7
From: Aric Cyr
[Why]
When requesting clocks from SMU which takes MHz inputs, DC will round
down KHz when converting to MHz, thus potentially requesting too low a
clock value.
[How]
Round up (ceil) when converting KHz to MHz for clock requests to SMU.
Signed-off-by: Aric Cyr
Reviewed-by:
From: Anthony Koo
- Updated SCR definition for FW boot options for Separate DCN init
for DMUB FW loaded in VBL
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +++
1 file changed, 7
From: Alvin Lee
Type adjustments and formatting fixes.
Signed-off-by: Alvin Lee
Reviewed-by: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
---
.../display/dc/dml/dcn21/display_mode_vba_21.c | 11 ++-
.../display/dc/dml/dcn30/display_mode_vba_30.c | 18 ++
From: Wang
Added NULL checks before two problematic statements
Signed-off-by: Wang
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
From: Chun-Liang Chang
[Why]
dmub would notify x86 response time violation by GPINT_DATAOUT
[How]
1. Use GPINT_DATAOUT to trigger x86 interrupt
2. Register GPINT_DATAOUT interrupt handler.
3. Trigger ACR while GPINT_DATAOUT occurred.
Signed-off-by: Chun-Liang Chang
Reviewed-by: Jun Lei
From: Aric Cyr
[Why]
EDID CTS requires at least 2k (16 blocks) to be readable.
[How]
Increase EDID buffer size to 2k
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
1 file changed, 1 insertion(+), 1
From: Nicholas Kazlauskas
[Why]
We're only treating TMDS as a valid target for infoframe updates which
results in PSR being unable to transition from state 4 to state 5.
[How]
Also allow infoframe updates for DCN3.1 - following how we handle
this path for earlier ASIC as well.
Signed-off-by:
DC version 3.2.142 brings improvements in multiple areas. In summary, we
highlight:
- Freesync improvements
- Remove unnecessary assert
- Firmware release 0.0.72
- Improve the EDID manipulation and DML calculations
Alvin Lee (1):
drm/amd/display: Adjust types and formatting for future
From: Wenjing Liu
There is a difference between our default behavior and override
behavior. For default behavior we need to decide link training settings
within specs' limitation and mandates.
For override behavior we do not need to follow all these requirements.
We are isolating override
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
From: Aric Cyr
DC version 3.2.142 brings improvements in multiple areas. In summary, we
highlight:
- Freesync improvements
- Remove unnecessary assert
- Firmware release 0.0.72
- Improve the EDID manipulation and DML calculations
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by:
From: Stylon Wang
[Why]
Changes in DM needed to support Freesync HDMI on DMUB.
[How]
Change implementation to parse CEA blocks in case of DMUB-enabled ASICs.
Signed-off-by: Stylon Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
Add new PCI device id.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 1a110b06cb6e..6419d75f1f18 100644
---
Reset SDMA RAS error counts during init only if persistent
EDC harvesting is not supported.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
On Wed, Jun 30, 2021 at 12:45 AM Ketsui wrote:
>
> >I think the 3200G may be a raven or raven2 variant rather than
> picasso.
>
> Are you sure? Examining vbios_version yields this on my system:
>
> $ cat /sys/class/drm/card0/device/vbios_version
> 113-PICASSO-114
>
I could be wrong. I can't
On 6/28/21 9:46 AM, Felix Kuehling wrote:
Am 2021-06-17 um 3:16 p.m. schrieb Ralph Campbell:
On 6/17/21 8:16 AM, Alex Sierra wrote:
From: Ralph Campbell
ZONE_DEVICE struct pages have an extra reference count that
complicates the
code for put_page() and several places in the kernel that need
Remove unused variable.
Fixes: 00858131205f69 ("Revert "drm/amd/display: Fix overlay validation by
considering cursors"")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 2021-06-29 5:02 p.m., Alex Deucher wrote:
> Remove unused variable.
>
> Fixes: 00858131205f69 ("Revert "drm/amd/display: Fix overlay validation by
> considering cursors"")
> Signed-off-by: Alex Deucher
Reviewed-by: Harry Wentland
Harry
> ---
>
>I think the 3200G may be a raven or raven2 variant rather than
picasso.
Are you sure? Examining vbios_version yields this on my system:
$ cat /sys/class/drm/card0/device/vbios_version
113-PICASSO-114
>Can you try the latest firmware from
Am 2021-06-29 um 5:48 p.m. schrieb Alex Sierra:
> During GPU page table invalidation with xnack off, new ranges
> split may occur concurrently in the same prange. Creating a new
> child per split. Each child should also increment its
> invalid counter, to assure GPU page table updates in these
>
During GPU page table invalidation with xnack off, new ranges
split may occur concurrently in the same prange. Creating a new
child per split. Each child should also increment its
invalid counter, to assure GPU page table updates in these
ranges.
Signed-off-by: Alex Sierra
---
[AMD Official Use Only]
Hi Chris,
the primary use of amdgpu_device_vram_access() is to gate direct kernel access
to VRAM using the MM_INDEX/MM_DATA registers or aperture. It should by design
never deal with data sizes != 4 bytes.
[kevin]:
NOT size aligned, it is offset (address) aligned,
On Tuesday, June 22nd, 2021 at 09:15, Pekka Paalanen
wrote:
> yes, I think this makes sense, even if it is a property that one can't
> tell for sure what it does before hand.
>
> Using a pair of properties, preference and active, to ask for something
> and then check what actually worked is
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liu, Aaron
Sent: Monday, June 28, 2021 10:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Tuikov, Luben ; Koenig, Christian
; Liu, Aaron
Subject: [PATCH] drm/amdgpu: enable sdma0
Hello Thomas,
thanks for the patch.
Tested-by: Yannick Fertre
Best regards
On 6/25/21 10:22 AM, Thomas Zimmermann wrote:
The field drm_device.irq_enabled is only used by legacy drivers
with userspace modesetting. Don't set it in stm.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Laurent
Setting CONFIG_FRAME_WARN=0 should disable 'stack frame larger than'
warnings. This is useful for example in KASAN builds. Make the dml
Makefile respect this config.
Fixes the following build warnings with CONFIG_KASAN=y and
CONFIG_FRAME_WARN=0:
Am 29.06.21 um 13:17 schrieb Pekka Paalanen:
> On Tue, 29 Jun 2021 08:12:54 +
> Simon Ser wrote:
>
>> On Tuesday, June 22nd, 2021 at 09:15, Pekka Paalanen
>> wrote:
>>
>>> yes, I think this makes sense, even if it is a property that one can't
>>> tell for sure what it does before hand.
On 2021-06-28 7:16 p.m., Deucher, Alexander wrote:
>
> Thanks for narrowing this down. There is new PCO SDMA firmware available
> (attached). Can you try it?
Sure, I'll try it, thanks.
--
Earthling Michel Dänzer | https://redhat.com
Libre software enthusiast
Am 28.06.21 um 19:03 schrieb Werner Sembach:
> Am 18.06.21 um 11:11 schrieb Werner Sembach:
>> Add a new general drm property "active bpc" which can be used by graphic
>> drivers to report the applied bit depth per pixel back to userspace.
>>
>> While "max bpc" can be used to change the color
Am 29.06.21 um 09:55 schrieb Nirmoy Das:
VM code should not be responsible for freeing pasid as pasid
gets allocated outside of VM code, before initializing a vm.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8
Am 29.06.21 um 01:15 schrieb Oak Zeng:
The ttm caching flags (ttm_cached, ttm_write_combined etc) are
used to determine a buffer object's mapping attributes in both
CPU page table and GPU page table (when that buffer is also
accessed by GPU). Currently the ttm caching flags are set in
function
On Tue, 29 Jun 2021 08:12:54 +
Simon Ser wrote:
> On Tuesday, June 22nd, 2021 at 09:15, Pekka Paalanen
> wrote:
>
> > yes, I think this makes sense, even if it is a property that one can't
> > tell for sure what it does before hand.
> >
> > Using a pair of properties, preference and
Am 29.06.21 um 13:17 schrieb Pekka Paalanen:
> On Tue, 29 Jun 2021 08:12:54 +
> Simon Ser wrote:
>
>> On Tuesday, June 22nd, 2021 at 09:15, Pekka Paalanen
>> wrote:
>>
>>> yes, I think this makes sense, even if it is a property that one can't
>>> tell for sure what it does before hand.
>>>
Return early for non-TTM_PL_TT BOs so that we don't pass
wrong pointer to amdgpu_gtt_mgr_has_gart_addr() which assumes
ttm_resource argument to be TTM_PL_TT type BO's.
v2: merge if-conditions
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++-
1 file changed, 2
Be more defensive and raise error on wrong mem_type
argument in amdgpu_gtt_mgr_has_gart_addr().
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
[AMD Official Use Only]
Ping..
> -Original Message-
> From: Quan, Evan
> Sent: Friday, June 25, 2021 4:13 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Quan, Evan
>
> Subject: [PATCH 2/2] drm/amd/pm: bump DRIVER_IF_VERSION for Sienna
> Cichlid
>
> To suppress the
[AMD Official Use Only]
Ping..
> -Original Message-
> From: Quan, Evan
> Sent: Friday, June 25, 2021 4:12 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Quan, Evan
>
> Subject: [PATCH 1/2] drm/amd/pm: update the gpu metrics data retrieving
> for Sienna Cichlid
>
>
[AMD Official Use Only]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Oak Zeng
Sent: Tuesday, June 29, 2021 7:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix ; Zhu, James ;
Koenig, Christian ; Zeng, Oak
Subject: [PATCH] drm/amdgpu: Set ttm caching
On 6/23/2021 9:05 PM, Felix Kuehling wrote:
On 2021-06-23 8:25 a.m., Nirmoy Das wrote:
VM code should not be responsible for freeing pasid as pasid
gets allocated outside of VM code, before initializing a vm.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c |
Replace idr with xarray as we actually need hash functionality.
Cleanup code related to vm pasid by adding helper function.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 136 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +-
2 files changed, 60
VM code should not be responsible for freeing pasid as pasid
gets allocated outside of VM code, before initializing a vm.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8
1 file changed, 8 insertions(+)
diff --git
VM code should not be responsible for freeing pasid as pasid
gets allocated outside of VM code, before initializing a vm.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 --
2 files changed, 8
[Public]
Acked-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Quan, Evan
Sent: Tuesday, June 29, 2021 3:44 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH 2/2] drm/amd/pm: bump DRIVER_IF_VERSION for Sienna Cichlid
[AMD
radeon_user_framebuffer_create() misses to call drm_gem_object_put() in
an error path. Add the missed function call to fix it.
Signed-off-by: Jing Xiangfeng
---
drivers/gpu/drm/radeon/radeon_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c
92 matches
Mail list logo
