Am 2021-11-11 um 8:43 a.m. schrieb Christian König:
> Am 11.11.21 um 13:13 schrieb Felix Kuehling:
>> Am 2021-11-11 um 2:00 a.m. schrieb Christian König:
>>> Am 11.11.21 um 00:36 schrieb Felix Kuehling:
On 2021-11-10 9:31 a.m., Christian König wrote:
[SNIP]
Aren't we processing
Am 2021-11-09 um 1:13 a.m. schrieb Ramesh Errabolu:
> Accounting system to track amount of available memory (system, TTM
> and VRAM of a device) relies on BO's domain. The change is to rely
> instead on allocation flag indicating BO type - VRAM, GTT, USERPTR,
> MMIO or DOORBELL
>
> Signed-off-by:
On 2021-11-10 8:24 a.m., Daniel Vetter wrote:
On Wed, Nov 10, 2021 at 11:09:50AM +0100, Christian König wrote:
Am 10.11.21 um 10:50 schrieb Daniel Vetter:
On Tue, Nov 09, 2021 at 08:17:01AM -0800, Rob Clark wrote:
On Tue, Nov 9, 2021 at 1:07 AM Daniel Vetter wrote:
On Mon, Nov 08, 2021 at
Am 11.11.21 um 13:13 schrieb Felix Kuehling:
Am 2021-11-11 um 2:00 a.m. schrieb Christian König:
Am 11.11.21 um 00:36 schrieb Felix Kuehling:
On 2021-11-10 9:31 a.m., Christian König wrote:
[SNIP]
Aren't we processing interrupts out-of-order in this case. We're
processing newer ones before
[AMD Official Use Only]
> >
> > Even if changing the heuristic for workload as Alex suggested?
> >
>
> Yes. I think this is meant to be BIOS driven for APU platforms and AMD
> APU + AMD dGPU with smartshift.
>
So then it sounds like if any - it would make sense only on dGPU that isn't
using
[AMD Official Use Only]
Agree with your comments. I will remove commenting the method
amdgpu_amdkfd_reserve_system_mem() in my updated patch.
-Original Message-
From: Kuehling, Felix
Sent: Thursday, November 11, 2021 2:54 PM
To: Errabolu, Ramesh ; amd-gfx@lists.freedesktop.org
[AMD Official Use Only]
Resp inline
Request clarification regarding - amdgpu_amdkfd_reserve_system_mem()
Will send out updated patch upon clarification
Regards,
Ramesh
-Original Message-
From: Kuehling, Felix
Sent: Thursday, November 11, 2021 7:44 AM
To:
Am 2021-11-11 um 3:45 p.m. schrieb Errabolu, Ramesh:
> [AMD Official Use Only]
>
> Resp inline
>
> Request clarification regarding - amdgpu_amdkfd_reserve_system_mem()
>
> Will send out updated patch upon clarification
>
> Regards,
> Ramesh
>
> -Original Message-
> From: Kuehling, Felix
On 2021-11-11 8:57 a.m., Felix Kuehling
wrote:
Am 2021-11-11 um 8:43 a.m. schrieb Christian König:
Am 11.11.21 um 13:13 schrieb Felix Kuehling:
Am 2021-11-11 um 2:00 a.m. schrieb Christian König:
Am
On 2021-11-09 10:26 p.m., Felix
Kuehling wrote:
On 2021-11-09 6:04 p.m., Philip Yang wrote:
If unmapping partial range, the parent
prange list op is update
notifier, child range list op is unmap range, need check
add sysfs knobs to enable modules' pr_debug()s ---> tracefs
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 8
drivers/gpu/drm/drm_print.c| 13 ++---
drivers/gpu/drm/i915/intel_gvt.c | 15 ---
3 files
Sean Paul proposed, in:
https://patchwork.freedesktop.org/series/78133/
drm/trace: Mirror DRM debug logs to tracefs
His patchset's objective is to be able to independently steer some of
the drm.debug stream to an alternate tracing destination, by splitting
drm_debug_enabled() into syslog & trace
drm's debug system writes 10 distinct categories of messages to syslog
using a small API[1]: drm_dbg*(10 names), DRM_DEV_DEBUG*(3 names),
DRM_DEBUG*(8 names). There are thousands of these callsites, each
categorized in this systematized way.
These callsites can be enabled at runtime by their
Hi Jason, Greg, DRM-everyone, everyone,
resend to add more people, after rebasing on master to pick up
306589856399 drm/print: Add deprecation notes to DRM_...() functions
This patchset has 3 separate but related parts:
1. DEFINE_DYNAMIC_DEBUG_BITGRPS macro [patch 1/10]
Declares DRM.debug
DEFINE_DYNAMIC_DEBUG_BITGRPS(fsname, var, bitmap_desc, bitmap)
allows users to create a drm.debug style (bitmap) sysfs interface,
mapping each bit to a group of pr_debugs, matching on their formats.
This works well when the formats systematically include a prefix
string such as ERR|WARN|INFO,
Taking embedded spaces out of existing prefixes makes them more easily
searchable; simplifying the extra quoting needed otherwise:
$> echo format "^gvt: core:" +p >control
Dropping the internal spaces means any trailing space in a query will
more clearly terminate the prefix being searched
The gvt component of this driver has ~120 pr_debugs with formats using
one of 9 fixed string prefixes, which are quite similar to those
enumerated in DRM debug categories. Following the interface model of
drm.debug, add a parameter to map bits to these format prefixes.
static struct
Duplicate drm_debug_enabled() code into both "basic" and "dyndbg"
ifdef branches. Then add a pr_debug("todo: ...") into the "dyndbg"
branch.
Then convert the "dyndbg" branch's code to a macro, so that the
pr_debug() get its callsite info from the invoking function, instead
of from
With the recent addition of pr_debug to tracefs via +T flag, we now
want to add drm.trace; like its model: drm.debug, it maps bits to
pr_debug categories, but this one enables/disables writing to tracefs
(iff CONFIG_TRACING).
Do this by:
1. add flags to dyndbg_bitmap_param, holds "p" or "T" to
allocates and initializes ...
Signed-off-by: Jim Cromie
---
include/drm/drm_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index 0cd95953cdf5..4b29261c4537 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@
logger_types.h defines many DC_LOG_*() categorized debug wrappers.
Most of these already use DRM debug API, so are controllable using
drm.debug, but others use a bare pr_debug("$prefix: .."), with 1 of 13
different class-prefixes matching [:uppercase:]
Use DEFINE_DYNAMIC_DEBUG_BITGRPS to create a
Accounting system to track amount of available memory (system, TTM
and VRAM of a device) relies on BO's domain. The change is to rely
instead on allocation flag indicating BO type - VRAM, GTT, USERPTR,
MMIO or DOORBELL
Signed-off-by: Ramesh Errabolu
---
MMIO/DOORBELL BOs encode control data and should be pinned in GTT
domain before enabling PCIe connected peer devices in accessing it
Signed-off-by: Ramesh Errabolu
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 69 +++
1 file changed, 69 insertions(+)
diff --git
From: Jun Lei
[why]
DML itself is SW only, putting the logic as part of resource makes it
hw dependent and thus impossible to compile separately from dc.
Separate compilation is critical for unit testing as well as bbox tool
development
[how]
create new dml wrapper.
Copy logic from the
From: "Xu, Jinze"
[Why]
In fast boot sequence, when change dispclk, otg is disabled but digfe
is enabled. This may cause dig fifo error.
[How]
Reset dig fifo after enable otg.
Reviewed-by: Jun Lei
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: JinZe.Xu
---
From: Mikita Lipski
[why]
- Adding a DM interface to enable DSC over eDP on Linux
- DSC over eDP will allow to power savings by reducing
the bandwidth required to support panel's modes
- Apply link optimization algorithm to reduce link bandwidth
when DSC is enabled
[how]
- Read eDP panel's DSC
From: Brandon Syu
[WHY]
With eDP DSC enabled and set 4K 60Hz, there would be screen
corruption when booting to OS or enabling the driver.
[HOW]
Avoid powering down VDD when we cannot apply eDP fast boot.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Brandon Syu
---
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Fix issue that secondary display goes blank on Non DCN31.
- Adjust flushing data in DMCUB
- Revert patches which cause regression in hadnling MPO/Link encoder assignment
- Correct the setting within MSA of DP2.0
From: Ahmad Othman
[Why]
Due to integration issues with branch merging,
a regression happened that prevented secondary
displays from lighting up or enabling certain features
[How]
Separated the new logic to be for DCN31 only and retained
pre DCN31 logic for all other ASICs
Reviewed-by: Wenjing
From: Nicholas Kazlauskas
[Why]
We're currently flushing commands that had been previously been
flushed or are currently being processed by the DMCUB when we don't
immediately wait for idle after command execution.
[How]
Avoiding reflushing the data by keeping track of the last wptr.
We'll
From: Angus Wang
[WHY]
The previous changes for fixing MPO underflow with multiple
display connected caused a regression where the machine runs
into a hang when doing multiple driver pnp with multiple displays
connected
[HOW]
Reverted offending change
Reviewed-by: Martin Leung
Acked-by: Wayne
From: Wenjing Liu
[why]
There is a bug in MSA programming sequence that mistakenly set
MSA vsp/hsp to 1 for positive polarity. This is incorrect.
Reviewed-by: Ariel Bernstein
Acked-by: Wayne Lin
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c| 4
From: Anthony Koo
- Fix ARR39-C issue with scaled integer addition in rb func
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
From: Yi-Ling Chen
[WHY]
After unloading driver, driver would not disable DSC function.
At next loading driver, driver would power all DSC engines off.
When driver powered the active DSC off, the screen would be gray
until reprograming DSC relatived register correcntly.
[HOW]
1. Remove DSC
From: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: hvanzyll
[What]
This change allows adjustment to the Visual Confirm
height border.
[Why]
Aids debugging and testing
[How]
Use the existing infrastructure to implement logic to
draw borders
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Harry VanZyllDeJong
---
From: Aric Cyr
This version brings along following fixes:
- Fix issue that secondary display goes blank on Non DCN31.
- Adjust flushing data in DMCUB
- Revert patches which cause regression in hadnling MPO/Link encoder assignment
- Correct the setting within MSA of DP2.0
- Adjustment for DML
From: Sung Joon Kim
[why]
Change causing issue. Need to revert the change.
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 2 --
1 file changed, 2 deletions(-)
diff --git
Just a ping to the amd-gfx list.
Trivial cleanup, can anybody give me an rb for that?
Thanks,
Christian.
Am 28.10.21 um 15:26 schrieb Christian König:
Just grab all fences for the display flip in one go.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
add support that allow the userspace tool like RGP to get the GFX clock
value at runtime, the fix follow the old way to show the min/current/max
clocks level for compatible consideration.
=== Test ===
$ cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 200Mhz *
1: 1100Mhz
2: 1600Mhz
then run stress
Am 11.11.21 um 10:58 schrieb Jiapeng Chong:
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2245
dp_dsc_slice_bpg_offset_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2044
Am 11.11.21 um 11:03 schrieb Jiapeng Chong:
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:622
dmub_srv_cmd_execute() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
Reviewed-by: Christian König
---
Am 2021-11-11 um 2:00 a.m. schrieb Christian König:
> Am 11.11.21 um 00:36 schrieb Felix Kuehling:
>> On 2021-11-10 9:31 a.m., Christian König wrote:
>>> Am 10.11.21 um 14:59 schrieb philip yang:
On 2021-11-10 5:15 a.m., Christian König wrote:
> [SNIP]
It is hard to
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