[AMD Official Use Only - General]
Series is acked-by: Evan Quan
> -Original Message-
> From: Powell, Darren
> Sent: Friday, May 13, 2022 11:15 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan ; Wang, Yang(Kevin)
> ; david.ni...@amd.com; Lazar, Lijo
> ; Feng, Kenneth ; Yu,
> Lang
On 5/11/2022 2:02 PM, Christian König wrote:
This is enough to get gputop working :)
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
Hey Christian,
On 5/11/2022 2:02 PM, Christian König wrote:
Convert fdinfo format to one documented in drm-usage-stats.rst.
It turned out that the existing implementation was actually completely
nonsense. The calculated percentages indeed represented the usage of the
engine, but with varying
/0day-ci/archive/20220513/202205131519.0pphvmxz-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
9519dacab7b8afd537811fc2abaceb4d14f4e16a)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
create smartshift sysfs attributes from dGPU device even
on smartshift 1.0 platform to be consistent. Do not populate
the attributes on platforms that have APU only but not dGPU
or vice versa.
V2:
avoid checking for the number of VGA/DISPLAY devices (Lijo)
move code to read from dGPU or APU
Well the best placement is guaranteed as long as the application doesn't
do any nonsense (e.g. trying to allocate a buffer larger than available
VRAM).
The VM_ALWAYS_VALID flag doesn't affect any of that handling.
Regards,
Christian.
Am 13.05.22 um 00:17 schrieb Marek Olšák:
Would it be
On 5/13/2022 3:29 PM, Sathishkumar S wrote:
create smartshift sysfs attributes from dGPU device even
on smartshift 1.0 platform to be consistent. Do not populate
the attributes on platforms that have APU only but not dGPU
or vice versa.
V2:
avoid checking for the number of VGA/DISPLAY
Am 13.05.22 um 10:18 schrieb Sharma, Shashank:
Hey Christian,
On 5/11/2022 2:02 PM, Christian König wrote:
[SNIP]
@@ -162,17 +162,49 @@ static unsigned int
amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip)
return hw_prio;
}
+/* Calculate the time spend on the hw */
+static
Exactly that's what we can't do.
See the kernel must always be able to move things to GTT or discard. So
when you want to guarantee that something is in VRAM you must at the
same time say you can discard it if it can't.
Christian.
Am 13.05.22 um 10:43 schrieb Pierre-Eric Pelloux-Prayer:
Hi
On 05/12, Sung Joon Kim wrote:
> According to the KMS man page, there is a
> "Coverage" alpha blend mode that assumes the
> pixel color values have NOT been pre-multiplied
> and will be done when the actual blending to
> the background color values happens.
>
> Previously, this mode hasn't been
[AMD Official Use Only - General]
-Original Message-
From: Kim, Sung joon
Sent: Friday, May 13, 2022 4:22 PM
To: Wentland, Harry ; Li, Sun peng (Leo)
; Siqueira, Rodrigo ; Deucher,
Alexander ; Koenig, Christian
Cc: amd-...@lists.freekdesktop.org; m...@igalia.com;
From: Lee Jones
commit 353f7f3a9dd5fd2833b6462bac89ec1654c9c3aa upstream.
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c: In function
‘dal_gpio_service_create’:
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:71:4:
From: Lee Jones
commit 353f7f3a9dd5fd2833b6462bac89ec1654c9c3aa upstream.
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c: In function
‘dal_gpio_service_create’:
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:71:4:
From: Lee Jones
commit 353f7f3a9dd5fd2833b6462bac89ec1654c9c3aa upstream.
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c: In function
‘dal_gpio_service_create’:
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:71:4:
Applied. Thanks!
Alex
On Thu, May 12, 2022 at 3:19 AM Jiapeng Chong
wrote:
>
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9687
> amdgpu_dm_atomic_commit_tail() warn: inconsistent indenting.
>
> Reported-by: Abaci Robot
> Signed-off-by:
On Fri, May 13, 2022 at 3:20 AM pengfuyuan wrote:
>
> [Why]
> The DC_DEFAULT_LOG_MASK macro has not been used for a long time, so remove it.
I'm sure there are lots of macros in the driver that are not used at
the moment. Any particular reason to remove it? DC_MIN_LOG_MASK
doesn't appear to be
On Thu, May 12, 2022 at 05:33:44PM -0500, Sierra Guiza, Alejandro (Alex) wrote:
>
> On 5/11/2022 1:50 PM, Jason Gunthorpe wrote:
> > On Thu, May 05, 2022 at 04:34:36PM -0500, Alex Sierra wrote:
> >
> > > diff --git a/mm/memory.c b/mm/memory.c
> > > index 76e3af9639d9..892c4cc54dc2 100644
> > >
[Why]
The DC_DEFAULT_LOG_MASK macro has not been used for a long time, so remove it.
Signed-off-by: pengfuyuan
---
.../drm/amd/display/include/logger_types.h| 33 ---
1 file changed, 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h
On 2022-05-12 09:15, Christian König wrote:
Am 12.05.22 um 15:07 schrieb Andrey Grodzovsky:
On 2022-05-12 02:06, Christian König wrote:
Am 11.05.22 um 22:27 schrieb Andrey Grodzovsky:
On 2022-05-11 11:39, Christian König wrote:
Am 11.05.22 um 17:35 schrieb Andrey Grodzovsky:
On
From: Derek Lai
[Why]
Second eDP can send display off notification through HPD
but DC isn't hooked up to handle. Some primary eDP panels
will toggle on/off incorrectly if it's enabled generically.
[How]
Extend the debug option to allow individually enabling hotplug
either the first eDP or the
From: Nicholas Kazlauskas
[Why]
A display clock change hang can occur when switching between DIO and HPO
enabled modes during the optimize_bandwidth in dc_commit_state_no_check
call.
This happens when going from 4k120 8bpc 420 to 4k144 10bpc 444.
Display clock in the DIO case is 1200MHz, but
From: Jasdeep Dhillon
[why & how]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN30 to DML, where all FPU code
should locate.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Jasdeep Dhillon
From: Michael Strauss
[WHY]
Regressions untentionally caused by change,
reverting until this can be resolved.
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Strauss
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 171 +++---
From: Paul Hsieh
[Why]
when driver and dmub request aux engine at the same time,
dmub grant the aux engine but driver fail. Then driver
release aux engine but doesn't clear the request bit.
Then aux engine will be occupied by driver forever.
[How]
When driver release aux engine, clear request
From: Aric Cyr
This version brings along the following:
- Improvements in link training fallback
- Adding individual edp hotplug support
- Fixes in DPIA HPD status, display clock change hang, etc.
- FPU isolation work for DCN30
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Improvements in link training fallback
* Adding individual edp hotplug support
* Fixes in DPIA HPD status, display clock change hang, etc.
* FPU isolation work for DCN30
---
Alvin Lee (1):
drm/amd/display:
From: Jimmy Kizito
[Why]
Driver needs up to date DPIA HPD status.
[How]
Use HPD query command to get DPIA HPD status.
Reviewed-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3
From: Jimmy Kizito
[Why]
Some displays may need several link training attempts before
link training succeeds.
[How]
If training succeeds after falling back to lower link bandwidth,
retry at original link bandwidth instead of abandoning link training
whenever link bandwidth is less than stream
From: David Galiffi
[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: David Galiffi
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 9 ++---
1 file changed, 6 insertions(+), 3
From: Alvin Lee
[Why & How]
Code clean up in dc.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 -
2 files changed, 9 insertions(+), 7
From: Bhawanpreet Lakha
[Why]
we save the prev_dppclk value using "dpp_inst" but
when reading this value we use the index "i". In
a case where a pipe is fused off we can end up reading
the incorrect instance because i != dpp_inst in this
case.
[How]
read the prev_dppclk using dpp_inst instead
From: Jimmy Kizito
[Why]
Driver needs up to date DPIA HPD status.
[How]
Use HPD query command to get DPIA HPD status.
Reviewed-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3
From: Bhawanpreet Lakha
[Why]
we save the prev_dppclk value using "dpp_inst" but
when reading this value we use the index "i". In
a case where a pipe is fused off we can end up reading
the incorrect instance because i != dpp_inst in this
case.
[How]
read the prev_dppclk using dpp_inst instead
From: Aric Cyr
This version brings along the following:
- Improvements in link training fallback
- Adding individual edp hotplug support
- Fixes in DPIA HPD status, display clock change hang, etc.
- FPU isolation work for DCN30
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
From: Jasdeep Dhillon
[why & how]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN30 to DML, where all FPU code
should locate.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Jasdeep Dhillon
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Improvements in link training fallback
* Adding individual edp hotplug support
* Fixes in DPIA HPD status, display clock change hang, etc.
* FPU isolation work for DCN30
---
Alvin Lee (1):
drm/amd/display:
From: Jimmy Kizito
[Why]
Some displays may need several link training attempts before
link training succeeds.
[How]
If training succeeds after falling back to lower link bandwidth,
retry at original link bandwidth instead of abandoning link training
whenever link bandwidth is less than stream
From: Alvin Lee
[Why & How]
Code clean up in dc.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 -
2 files changed, 9 insertions(+), 7
From: Paul Hsieh
[Why]
when driver and dmub request aux engine at the same time,
dmub grant the aux engine but driver fail. Then driver
release aux engine but doesn't clear the request bit.
Then aux engine will be occupied by driver forever.
[How]
When driver release aux engine, clear request
From: Nicholas Kazlauskas
[Why]
A display clock change hang can occur when switching between DIO and HPO
enabled modes during the optimize_bandwidth in dc_commit_state_no_check
call.
This happens when going from 4k120 8bpc 420 to 4k144 10bpc 444.
Display clock in the DIO case is 1200MHz, but
From: David Galiffi
[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: David Galiffi
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 9 ++---
1 file changed, 6 insertions(+), 3
From: Derek Lai
[Why]
Second eDP can send display off notification through HPD
but DC isn't hooked up to handle. Some primary eDP panels
will toggle on/off incorrectly if it's enabled generically.
[How]
Extend the debug option to allow individually enabling hotplug
either the first eDP or the
From: Michael Strauss
This reverts commit f07023c8bb2c596af97dea9995d9f5a0140cddd3.
[WHY]
Regressions untentionally caused by change,
reverting until this can be resolved.
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Strauss
---
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