This will remove some redundant codes.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index d6fc00d51c8c..03e07d1d1d1a
[Why]
Getting below build errors:
drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1419:3: error:
unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
default:
^
[Why]
Getting below errors:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5:
error: implicit conversion from enumeration type 'enum scan_direction_class'
to different enumeration type 'enum dm_rotation_angle'
[-Werror,-Wenum-conversion]
On 6/7/2022 2:08 PM, Evan Quan wrote:
Enable ASPM support for PCIE 7.4.0 and 7.6.0.
Signed-off-by: Evan Quan
Reviewed-by: Lijo Lazar
Thanks,
Lijo
Change-Id: Ib3b0e106ff43ad49f0f815e6eeb5c756b6bf4550
--
v1->v2:
- support LTR disabled scenario(Lijo)
---
Enable ASPM support for PCIE 7.4.0 and 7.6.0.
Signed-off-by: Evan Quan
Change-Id: Ib3b0e106ff43ad49f0f815e6eeb5c756b6bf4550
--
v1->v2:
- support LTR disabled scenario(Lijo)
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1, Move root BO kmapping to amdgpu_vm_make_compute.
2, Don't validate and kmap root BO intentional, it would be
validated and mapped by amdgpu_vm_validate_pt_bos if necessary.
3, Rename and expose vm_validate_pt_pd_bos, so that it
could be used by SVM.
Signed-off-by: Lang Yu
---
If a BO is pinned to VRAM and you try to validate it into GTT,
you will get an error.
Suggested-by: Christian König
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Add support for peer-to-peer communication among AMD GPUs over PCIe
bus. Support REQUIRES enablement of config HSA_AMD_P2P.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
[AMD Official Use Only - General]
Ping
-Original Message-
From: amd-gfx On Behalf Of Yifan Zhang
Sent: Monday, June 6, 2022 6:40 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Ray
Subject: [PATCH] drm/amdgpu/mes: only invalid/prime icache after
On Tue, Jun 7, 2022 at 4:27 AM Chandan Vurdigere Nataraj
wrote:
>
> [Why]
> Getting below build errors:
> drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1419:3: error:
> unannotated fall-through between switch labels
> [-Werror,-Wimplicit-fallthrough]
> default:
>
amdgpu_get_xgmi_hive() increases the kobject reference counter of the
hive it returned. The hive returned by amdgpu_get_xgmi_hive() should be
released with the help of amdgpu_put_xgmi_hive() to balance its kobject
reference counter properly. Forgetting the amdgpu_put_xgmi_hive()
operation will
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Joseph
Greathouse
Sent: Monday, June 6, 2022 7:04 PM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom ; Greathouse, Joseph
Subject: [PATCH] drm/amdgpu: Add MODE
[Public]
Acked-by: Alex Deucher
From: Zhang, Yifan
Sent: Tuesday, June 7, 2022 10:36 AM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Huang, Tim ; Du, Xiaojian
Subject: RE: [PATCH] drm/amdgpu/mes: only invalid/prime
Reviewed-by: Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Tuesday, June 7, 2022 10:37 PM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Huang, Tim ; Du, Xiaojian
Subject: RE: [PATCH] drm/amdgpu/mes: only invalid/prime icache after
On Sun, Jun 5, 2022 at 10:39 PM ZhenGuo Yin wrote:
>
> The scratch register should be accessed through MMIO instead of RLCG
> in SRIOV, since it being used in RLCG register access function.
>
> Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
> Signed-off-by: ZhenGuo Yin
On 2022-06-07 10:00, Alex Deucher wrote:
> On Tue, Jun 7, 2022 at 4:27 AM Chandan Vurdigere Nataraj
> wrote:
>>
>> [Why]
>> Getting below build errors:
>> drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1419:3: error:
>> unannotated fall-through between switch labels
>>
[AMD Official Use Only - General]
Does this need an update for GC 10.3.7 as well?
Alex
From: Zhang, Jesse(Jie)
Sent: Monday, June 6, 2022 11:20 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Limonciello, Mario
; Chang, David ; Kuehling,
Felix
On 6/6/22 13:57, Christian König wrote:
> Am 05.06.22 um 18:47 schrieb Daniel Vetter:
>> On Fri, 27 May 2022 at 01:55, Dmitry Osipenko
>> wrote:
>>> Introduce a common DRM SHMEM shrinker framework that allows to reduce
>>> code duplication among DRM drivers by replacing theirs custom shrinker
>>>
Similar to the handling of amdgpu_sa_bo_next_hole in commit 6a15f3ff19a8
("drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_hole"),
we thought a patch might be needed here as well.
The entries were only initialized once in radeon_sa_bo_new. If a fence
wasn't signalled yet in the
Similar to the handling of amdgpu_mode_dumb_create in commit 54ef0b5461c0
("drm/amdgpu: integer overflow in amdgpu_mode_dumb_create()"),
we thought a patch might be needed here as well.
args->size is a u64. arg->pitch and args->height are u32. The
multiplication will overflow instead of using
Am 2022-06-07 um 05:59 schrieb Lang Yu:
This will remove some redundant codes.
Signed-off-by: Lang Yu
The redundancy is quite small, and
amdgpu_amdkfd_gpuvm_validate_pt_pd_bos and amdgpu_amdkfd_bo_validate are
quite a bit more complex and handle more different cases. Someone
changing
On Tue, Jun 7, 2022 at 1:14 PM Tejun Heo wrote:
>
> On Sat, May 21, 2022 at 12:04:00AM -0400, Andrey Grodzovsky wrote:
> > From 78df30cc97f10c885f5159a293e6afe2348aa60c Mon Sep 17 00:00:00 2001
> > From: Andrey Grodzovsky
> > Date: Thu, 19 May 2022 09:47:28 -0400
> > Subject: Revert "workqueue:
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
From: David Galiffi
[ Upstream commit 49947b906a6bd9668eaf4f9cf691973c25c26955 ]
[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: David Galiffi
Tested-by: Daniel Wheeler
Signed-off-by: Alex
From: Gong Yuanjun
[ Upstream commit d2f4460a3d9502513419f06cc376c7ade49d5753 ]
gpu_metrics_table is allocated in yellow_carp_init_smc_tables() but
not freed in yellow_carp_fini_smc_tables().
Signed-off-by: Gong Yuanjun
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Lijo Lazar
[ Upstream commit b0f4d663fce6a4232d3c20ce820f919111b1c60b ]
On aldebaran, when thermal throttling happens due to excessive GPU
temperature, the reason for throttling event is missed in warning
message. This patch fixes it.
Signed-off-by: Lijo Lazar
Reviewed-by: Yang Wang
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
On Mon, Jun 6, 2022 at 5:04 PM Joseph Greathouse
wrote:
>
> The MODE register contains detailed per-wave information, but UMR
> skipped printing it. This patch adds the ability to print each wave's
> MODE register as part of the wave scan operation, and prints the MODE
> register's sub-fields as
Applied. Thanks!
Alex
On Tue, Jun 7, 2022 at 12:05 PM Xiaohui Zhang wrote:
>
> Similar to the handling of amdgpu_mode_dumb_create in commit 54ef0b5461c0
> ("drm/amdgpu: integer overflow in amdgpu_mode_dumb_create()"),
> we thought a patch might be needed here as well.
>
> args->size is a u64.
[Why]
0 was passed in place of a pointer which triggered null pointer
dereference.
[How]
Pass in a pointer that contains nullified parameters instead of null
pointer.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 ++---
1 file changed, 6
From: Nicholas Kazlauskas
[ Upstream commit 66a197203794339b028eedfa880bff9367fce783 ]
[Why]
A display clock change hang can occur when switching between DIO and HPO
enabled modes during the optimize_bandwidth in dc_commit_state_no_check
call.
This happens when going from 4k120 8bpc 420 to
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
From: Gong Yuanjun
[ Upstream commit d2f4460a3d9502513419f06cc376c7ade49d5753 ]
gpu_metrics_table is allocated in yellow_carp_init_smc_tables() but
not freed in yellow_carp_fini_smc_tables().
Signed-off-by: Gong Yuanjun
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: David Galiffi
[ Upstream commit 49947b906a6bd9668eaf4f9cf691973c25c26955 ]
[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: David Galiffi
Tested-by: Daniel Wheeler
Signed-off-by: Alex
From: Yury Norov
[ Upstream commit 525d6515604eb1373ce5e6372a6b6640953b2d6a ]
The smu_v1X_0_set_allowed_mask() uses bitmap_copy() to convert
bitmap to 32-bit array. This may be wrong due to endiannes issues.
Fix it by switching to bitmap_{from,to}_arr32.
CC: Alexander Gordeev
CC: Andy
From: Yury Norov
[ Upstream commit 525d6515604eb1373ce5e6372a6b6640953b2d6a ]
The smu_v1X_0_set_allowed_mask() uses bitmap_copy() to convert
bitmap to 32-bit array. This may be wrong due to endiannes issues.
Fix it by switching to bitmap_{from,to}_arr32.
CC: Alexander Gordeev
CC: Andy
TTM used to track the "acc_size" of all BOs internally. We needed to
keep track of it in our memory reservation to avoid TTM running out
of memory in its own accounting. However, that "acc_size" accounting
has since been removed from TTM. Therefore we don't really need to
track it any more.
[WHY]
Unified memory with xnack off should be tracked, as userptr mappings
and legacy allocations do. To avoid oversuscribe system memory when
xnack off.
[How]
Exposing functions reserve_mem_limit and unreserve_mem_limit to SVM
API and call them on every prange creation and free.
Signed-off-by:
On 2022-06-07 13:41, Alex Deucher wrote:
On Tue, Jun 7, 2022 at 1:40 PM Rodrigo Siqueira Jordao
wrote:
On 2022-06-07 13:06, Aurabindo Pillai wrote:
[Why]
0 was passed in place of a pointer which triggered null pointer
dereference.
[How]
Pass in a pointer that contains nullified
Applied. Thanks!
Alex
On Tue, Jun 7, 2022 at 12:04 PM Xiaohui Zhang wrote:
>
> Similar to the handling of amdgpu_sa_bo_next_hole in commit 6a15f3ff19a8
> ("drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_hole"),
> we thought a patch might be needed here as well.
>
> The
On 2022-06-07 05:40, Chandan Vurdigere Nataraj wrote:
> [Why]
> Getting below errors:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5:
> error: implicit conversion from enumeration type 'enum scan_direction_class'
> to different enumeration type 'enum
On Tue, Jun 7, 2022 at 1:40 PM Rodrigo Siqueira Jordao
wrote:
>
>
>
> On 2022-06-07 13:06, Aurabindo Pillai wrote:
> > [Why]
> > 0 was passed in place of a pointer which triggered null pointer
> > dereference.
> >
> > [How]
> > Pass in a pointer that contains nullified parameters instead of null
On 2022-06-07 11:34, Leo wrote:
On 2022-06-07 05:40, Chandan Vurdigere Nataraj wrote:
[Why]
Getting below errors:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5:
error: implicit conversion from enumeration type 'enum scan_direction_class'
to different
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
From: David Galiffi
[ Upstream commit 49947b906a6bd9668eaf4f9cf691973c25c26955 ]
[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: David Galiffi
Tested-by: Daniel Wheeler
Signed-off-by: Alex
From: Lijo Lazar
[ Upstream commit b0f4d663fce6a4232d3c20ce820f919111b1c60b ]
On aldebaran, when thermal throttling happens due to excessive GPU
temperature, the reason for throttling event is missed in warning
message. This patch fixes it.
Signed-off-by: Lijo Lazar
Reviewed-by: Yang Wang
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
Am 2022-06-07 um 04:23 schrieb Ramesh Errabolu:
Add support for peer-to-peer communication among AMD GPUs over PCIe
bus. Support REQUIRES enablement of config HSA_AMD_P2P.
Signed-off-by: Ramesh Errabolu
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h |
On Sat, May 21, 2022 at 12:04:00AM -0400, Andrey Grodzovsky wrote:
> From 78df30cc97f10c885f5159a293e6afe2348aa60c Mon Sep 17 00:00:00 2001
> From: Andrey Grodzovsky
> Date: Thu, 19 May 2022 09:47:28 -0400
> Subject: Revert "workqueue: remove unused cancel_work()"
>
> This reverts commit
On 2022-06-07 13:06, Aurabindo Pillai wrote:
[Why]
0 was passed in place of a pointer which triggered null pointer
dereference.
[How]
Pass in a pointer that contains nullified parameters instead of null
pointer.
Signed-off-by: Aurabindo Pillai
---
From: Evan Quan
[ Upstream commit 396beb91a9eb86cbfa404e4220cca8f3ada70777 ]
Correct the metrics version used for SMU 11.0.11/12/13.
Fixes misreported GPU metrics (e.g., fan speed, etc.) depending
on which version of SMU firmware is loaded.
Bug:
From: Lijo Lazar
[ Upstream commit b0f4d663fce6a4232d3c20ce820f919111b1c60b ]
On aldebaran, when thermal throttling happens due to excessive GPU
temperature, the reason for throttling event is missed in warning
message. This patch fixes it.
Signed-off-by: Lijo Lazar
Reviewed-by: Yang Wang
From: Yury Norov
[ Upstream commit 525d6515604eb1373ce5e6372a6b6640953b2d6a ]
The smu_v1X_0_set_allowed_mask() uses bitmap_copy() to convert
bitmap to 32-bit array. This may be wrong due to endiannes issues.
Fix it by switching to bitmap_{from,to}_arr32.
CC: Alexander Gordeev
CC: Andy
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
From: Gong Yuanjun
[ Upstream commit a2b28708b645c5632dc93669ab06e97874c8244f ]
In radeon_fp_native_mode(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference
on failure of drm_mode_duplicate(). Add a check to avoid npd.
The failure
- add unified queue headers
- add unified queue ib tests.
Signed-off-by: Ruijing Dong
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 102 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
2 files changed, 100 insertions(+), 3 deletions(-)
diff --git
- remove multiple queue support.
- add unified queue related functions.
Signed-off-by: Ruijing Dong
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 563 +++---
1 file changed, 140 insertions(+), 423 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
In retrospect, the name I chose for this originally is confusing, as
there's a lot more info in here then just the VCPI. This really should be
called a payload. Let's make it more obvious that this is meant to be
related to the atomic state and is about payloads by renaming it to
This function isn't too confusing if you see the comment around the
call-site for it, but if you don't then it's not at all obvious this is
meant to copy DRM's payload table over to DC's internal state structs.
Seeing this function before finding that comment definitely threw me into a
loop a few
Just to make this more clear to outside contributors that these are
DC-specific structs, as this also threw me into a loop a number of times
before I figured out the purpose of this.
Signed-off-by: Lyude Paul
Cc: Wayne Lin
Cc: Fangzhi Zuo
---
On Tue, Jun 07, 2022 at 01:39:01PM -0400, Alex Deucher wrote:
> On Tue, Jun 7, 2022 at 1:14 PM Tejun Heo wrote:
> >
> > On Sat, May 21, 2022 at 12:04:00AM -0400, Andrey Grodzovsky wrote:
> > > From 78df30cc97f10c885f5159a293e6afe2348aa60c Mon Sep 17 00:00:00 2001
> > > From: Andrey Grodzovsky
>
We already open-code this quite often, and will be iterating through
payloads even more once we've moved all of the payload tracking into the
atomic state. So, let's add a helper for doing this.
Signed-off-by: Lyude Paul
Cc: Wayne Lin
Cc: Ville Syrjälä
Cc: Fangzhi Zuo
Cc: Jani Nikula
Cc:
Right now, radeon is technically the only non-atomic driver still making
use of the MST helpers - and thus the final user of all of the legacy MST
helpers. Originally I was going to look into seeing if we could move legacy
MST into the radeon driver itself, however:
* SI and CIK both can use
In the past, we've ran into strange issues regarding errors in response to
trying to destroy payloads after a port has been unplugged. We fixed this
back in:
This is intended to replace the workaround that was added here:
commit 3769e4c0af5b ("drm/dp_mst: Avoid to mess up payload table by ports
I'm not sure why, but at the time I originally wrote the find/release time
slot helpers I thought we should avoid keeping modeset tracking out of the
MST helpers. In retrospect though there's no actual good reason to do
this, and the logic has ended up being identical across all the drivers
using
We want to start cutting down on all of the places that we use port
validation, so that ports may be removed from the topology as quickly as
possible to minimize the number of errors we run into as a result of being
out of sync with the current topology status. This isn't a very typical
scenario
Currently, we set drm_dp_atomic_payload->time_slots to 0 in order to
indicate that we're about to delete a payload in the current atomic state.
Since we're going to be dropping all of the legacy code for handling the
payload table however, we need to be able to ensure that we still keep
track of
[AMD Official Use Only - General]
I can see for VCN4, AV1 dec/enc also need to limit to the first instance.
Thanks,
Ruijing
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, June 3, 2022 10:12 AM
To: Christian König
Cc: Pelloux-Prayer, Pierre-Eric ; amd-gfx
VCPI is only sort of the correct term here, originally the majority of this
code simply referred to timeslots vaguely as "slots" - and since I started
working on it and adding atomic functionality, the name "VCPI slots" has
been used to represent time slots.
Now that we actually have consistent
Post-NV50, the only kind of encoder you'll find for DP connectors on Nvidia
GPUs are SORs (serial output resources). Because SORs have fixed
associations with their connectors, we can correctly assume that any DP
connector on a nvidia GPU will have exactly one SOR encoder routed to it
for
Since we're going to be relying on atomic locking for payloads now (and the
MST mgr needs to track CRTCs), pull in the topology state for all modesets
in nv50_msto_atomic_check().
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
1 file changed, 1 insertion(+), 1
Currently with the MST helpers we avoid releasing payloads _and_ avoid
pulling in the MST state if there aren't any actual payload changes. While
we want to keep the first step, we need to now make sure that we're always
pulling in the MST state on all modesets that can modify payloads - even if
Now that we've finally gotten rid of the non-atomic MST users leftover in
the kernel, we can finally get rid of all of the legacy payload code we
have and move as much as possible into the MST atomic state structs. The
main purpose of this is to make the MST code a lot less confusing to work
on,
For quite a while we've been carrying around a lot of legacy modesetting
code in the MST helpers that has been rather annoying to keep around,
and very often gets in the way of trying to implement additional
functionality in MST such as fallback link rate retraining, dynamic BPC
management and DSC
We already open-code this quite often, and will be iterating through
payloads even more once we've moved all of the payload tracking into the
atomic state. So, let's add a helper for doing this.
Signed-off-by: Lyude Paul
Cc: Wayne Lin
Cc: Ville Syrjälä
Cc: Fangzhi Zuo
Cc: Jani Nikula
Cc:
For some reason we mention returning 0 if "slots have been added back to
drm_dp_mst_topology_state->avail_slots". This is totally misleading,
avail_slots is simply for figuring out the total number of slots available
in total on the topology and has no relation to the current payload
allocations.
Since we're about to start adding some stuff here, we may as well fill in
any missing documentation that we forgot to write.
Signed-off-by: Lyude Paul
Cc: Wayne Lin
Cc: Ville Syrjälä
Cc: Fangzhi Zuo
Cc: Jani Nikula
Cc: Imre Deak
Cc: Daniel Vetter
Cc: Sean Paul
---
Since we're about to start adding some stuff here, we may as well fill in
any missing documentation that we forgot to write.
Signed-off-by: Lyude Paul
Cc: Wayne Lin
Cc: Ville Syrjälä
Cc: Fangzhi Zuo
Cc: Jani Nikula
Cc: Imre Deak
Cc: Daniel Vetter
Cc: Sean Paul
---
For some reason we mention returning 0 if "slots have been added back to
drm_dp_mst_topology_state->avail_slots". This is totally misleading,
avail_slots is simply for figuring out the total number of slots available
in total on the topology and has no relation to the current payload
allocations.
As Daniel Vetter pointed out, if we only use the atomic modesetting locks
with MST it's technically possible for a driver with non-blocking modesets
to race when it comes to MST displays - as we make the mistake of not doing
our own CRTC commit tracking in the topology_state object.
This could
This function isn't too confusing if you see the comment around the
call-site for it, but if you don't then it's not at all obvious this is
meant to copy DRM's payload table over to DC's internal state structs.
Seeing this function before finding that comment definitely threw me into a
loop a few
Am 2022-06-07 um 13:17 schrieb Alex Sierra:
[WHY]
Unified memory with xnack off should be tracked, as userptr mappings
and legacy allocations do. To avoid oversuscribe system memory when
xnack off.
[How]
Exposing functions reserve_mem_limit and unreserve_mem_limit to SVM
API and call them on
VCPI is only sort of the correct term here, originally the majority of this
code simply referred to timeslots vaguely as "slots" - and since I started
working on it and adding atomic functionality, the name "VCPI slots" has
been used to represent time slots.
Now that we actually have consistent
Ugh, thanks ./scripts/get_maintainers.pl for confusing and breaking
git-send email <<. Sorry for the resend everyone.
For quite a while we've been carrying around a lot of legacy modesetting
code in the MST helpers that has been rather annoying to keep around,
and very often gets in the way of
In retrospect, the name I chose for this originally is confusing, as
there's a lot more info in here then just the VCPI. This really should be
called a payload. Let's make it more obvious that this is meant to be
related to the atomic state and is about payloads by renaming it to
Just to make this more clear to outside contributors that these are
DC-specific structs, as this also threw me into a loop a number of times
before I figured out the purpose of this.
Signed-off-by: Lyude Paul
Cc: Wayne Lin
Cc: Fangzhi Zuo
---
There's another kind of situation where we could potentially race with
nonblocking modesets and MST, especially if we were to only use the locking
provided by atomic modesetting:
* Display 1 begins as enabled on DP-1 in SST mode
* Display 1 switches to MST mode, exposes one sink in MST mode
*
We'll need to implement the parse callbacks for vcn4 as well if we
haven't already.
Alex
On Tue, Jun 7, 2022 at 4:20 PM Dong, Ruijing wrote:
>
> [AMD Official Use Only - General]
>
> I can see for VCN4, AV1 dec/enc also need to limit to the first instance.
>
> Thanks,
> Ruijing
>
>
On Fri, Jun 3, 2022 at 9:05 AM Christian König
wrote:
>
> The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
> are set.
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
> 1 file changed, 5
On Tue, Jun 7, 2022 at 3:39 PM Lyude Paul wrote:
>
> Right now, radeon is technically the only non-atomic driver still making
> use of the MST helpers - and thus the final user of all of the legacy MST
> helpers. Originally I was going to look into seeing if we could move legacy
> MST into the
KUnit unifies the test structure and provides helper tools that simplify
the development. Basic use case allows running tests as regular
processes, which makes easier to run unit tests on a development machine
and to integrate the tests in a CI system.
This commit introduce a basic unit test to
From: Magali Lemes
The bw_fixed library performs a lot of the mathematical operations
involving fixed-point arithmetic and the conversion of integers to
fixed-point representation.
As fixed-point representation is the base foundation of the DML calcs
operations, this unit tests intend to assure
The macros defined at bw_fixed are important mathematical definitions,
specifying masks to get the fractional part and the maximum and minimum
values of I64. In order to enable unit tests for bw_fixed, it is
relevant to have access to those macros. This commit moves the macros to
the header file,
This RFC is a preview of the work being developed by Isabella Basso [1],
Maíra Canal [2], and Tales Lelo [3], as part of their Google Summer of Code
projects [4], and Magali Lemes [5], as part of her capstone project.
Our main goal is to bring unit testing to the AMDPGU driver; in particular,
Update MES API to support oversubscription without aggregated doorbell
for usermode queues.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
Store MES scheduler and MES KIQ version numbers in amdgpu_mes.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 +++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 12
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
Make MES/RS64 CP enablement and MES scheduler/MES KIQ versions available
through sysfs.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
Starting with GFX11, MES requires wptr BOs to be GTT allocated/mapped to
GART for usermode queues in order to support oversubscription. In the
case that work is submitted to an unmapped queue, MES must have a GART
wptr address to determine whether the queue should be mapped.
This change is
Add jpeg vmid update under IB submit
Signed-off-by: Mohammad Zafar Ziya
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git
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