Prepare DRM prime core to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Reviewed-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/drm_prime.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
The new common dma-buf locking convention will require buffer importers
to hold the reservation lock around mapping operations. Make DRM GEM core
to take the lock around the vmapping operations and update DRM drivers to
use the locked functions for the case where DRM core now holds the lock.
This
Move dma-buf attachment API functions to the dynamic locking specification
by taking the reservation lock around the mapping operations. The strict
locking convention prevents deadlock situations for dma-buf importers and
exporters.
Reviewed-by: Christian König
Signed-off-by: Dmitry Osipenko
Add unlocked variant of dma_buf_map/unmap_attachment() that will
be used by drivers that don't take the reservation lock explicitly.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 53 +++
include/linux/dma-buf.h |
Add unlocked variant of dma_buf_vmap/vunmap() that will be utilized
by drivers that don't take the reservation lock explicitly.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 38 ++
include/linux/dma-buf.h | 2 ++
From: Alvin Lee
[Why and How]
- Add a debug option for allocating extra way for cursor
- Remove usage of cache_cursor_addr since it's not gaurenteed
to be populated
- Include cursor size in MALL calculation if it exceeds the
DCN cursor buffer size (and don't need extra way for cursor)
From: Alvin Lee
[Why and How]
For SubVP pipe split case, pass in split index for
main and phantom pipes to ensure that the P-State
sequence will force P-State for all required pipes.
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
From: Wenjing Liu
[why]
When user unplugs mst hubs, the current code will forcefully zero
entire mst payload allocation table structure stored in link before we
deallocate actual payload when disabling stream.
During the first disable stream sequence, we will use current mst
payload allocation
From: Alvin Lee
[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.
Am 2022-09-12 um 08:36 schrieb Christian König:
Use DMA_RESV_USAGE_BOOKKEEP for VM page table updates and KFD preemption fence.
v2: actually update all usages for KFD
Signed-off-by: Christian König
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 26 ---
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 0caac1da994900d12a9be6106edb8e98696712a3 Add linux-next specific
files for 20220913
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209042337.fqi69rlv-...@intel.com
https
Hello,
This series moves all drivers to a dynamic dma-buf locking specification.
>From now on all dma-buf importers are made responsible for holding
dma-buf's reservation lock around all operations performed over dma-bufs
in accordance to the locking specification. This allows us to utilize
Move dma-buf attachment mapping functions to the dynamic locking
specification by asserting that the reservation lock is held.
Reviewed-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git
Prepare InfiniBand drivers to the common dynamic dma-buf locking
convention by starting to use the unlocked versions of dma-buf API
functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/infiniband/core/umem_dmabuf.c | 7 ---
1 file changed, 4 insertions(+), 3
Prepare Tegra DRM driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gem.c | 17 +
1 file changed, 9 insertions(+), 8
Prepare Tegra video decoder driver to the common dynamic dma-buf
locking convention by starting to use the unlocked versions of dma-buf
API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/media/platform/nvidia/tegra-vde/dmabuf-cache.c | 6 +++---
1 file changed,
Move dma_buf_vmap/vunmap_unlocked() functions to the dynamic locking
specification by asserting that the reservation lock is held.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/dma-buf/dma-buf.c | 4
1 file changed, 4 insertions(+)
diff --git
Prepare Etnaviv driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 2 +-
1 file changed, 1 insertion(+), 1
Prepare gntdev driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Juergen Gross
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/xen/gntdev-dmabuf.c | 8
1 file changed, 4
Prepare i915 driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions
and handling cases where importer now holds the reservation lock.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
Move dma_buf_mmap() function to the dynamic locking specification by
taking the reservation lock. Neither of the today's drivers take the
reservation lock within the mmap() callback, hence it's safe to enforce
the locking.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
Prepare Armada driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/armada/armada_gem.c | 8
1 file changed, 4 insertions(+), 4
Prepare V4L2 memory allocators to the common dynamic dma-buf locking
convention by starting to use the unlocked versions of dma-buf API
functions.
Acked-by: Tomasz Figa
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/media/common/videobuf2/videobuf2-dma-contig.c | 11
All drivers that use dma-bufs have been moved to the updated locking
specification and now dma-buf reservation is guaranteed to be locked
by importers during the mapping operations. There is no need to take
the internal dma-buf lock anymore. Remove locking from the videobuf2
memory allocators.
From: George Shen
[Why]
Current DCN3.2 logic for finding the dummy P-state index uses the
DCN3.0 DML validation function instead of DCN3.2 DML.
This can result in either unexpected DML VBA values, or unexpected
dummy P-state index to be used.
[How]
Update the dummy P-state logic to use DCN3.2
On 2022-09-12 18:02, Nathan Chancellor wrote:
Hi Rodrigo,
On Mon, Sep 12, 2022 at 05:50:31PM -0400, Rodrigo Siqueira Jordao wrote:
On 2022-08-30 16:34, Nathan Chancellor wrote:
Hi all,
This series aims to address the following warnings, which are visible
when building x86_64
From: Alvin Lee
[Why & How]
Uncomment SubVP pipe split assignment in driver since FW headers
are now promoted
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4
1 file changed, 4 deletions(-)
diff --git
From: George Shen
[Why]
The urgent latency override is useful when debugging issues
relating to underflow.
Current overridden variable is not correct and has no effect
on DCN3.2 and DCN3.21 DML calculations.
[How]
For DCN3.2 and DCN3.21, override the correct urgent latency
variable when
From: Charlene Liu
[why]
Expose few dchubbun functions in dcn31 and dcn32 to leverage.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 2 +-
.../drm/amd/display/dc/dcn31/dcn31_hubbub.h | 2 ++
From: Pavle Kotarac
[WHY]
New dcn301 has 2 less phys
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Sherry Wang
[Why]
Hostvm should be enabled/disabled accordding to
the status of riommu_active, but hostvm always
be disabled on DCN31 which causes underflow
[How]
Set correct hostvm flag on DCN31
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Sherry Wang
---
From: Pavle Kotarac
[WHY]
Adding new asic id for dcn301
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
From: Wenjing Liu
[why]
Original change 8da78e248069 "drm/amd/display: Add
interface to track PHY state" was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are
From: Michael Strauss
[WHY]
LTTPRs can in very rare instsances fail to increment DPCD LTTPR count.
This results in aux-i LTTPR requests to be sent to the wrong DPCD
address, which causes link training failure.
[HOW]
Override internal repeater count if fixed_vs flag is set for a given link
Given many entities competing for same run queue on
the same scheduler and unacceptably long wait time for some
jobs waiting stuck in the run queue before being picked up are
observed (seen using GPUVis).
The issue is due to the Round Robin policy used by schedulers
to pick up the next entity's
This patch updates the PTE flags when translate further (TF) is
enabled:
- With translate_further enabled, invalid PTEs can be 0. Reading
consecutive invalid PTEs as 0 is considered a fault. To prevent
this, ensure invalid PTEs have at least 1 bit set.
- The current invalid PTE flags settings
From: Ian Chen
[Why & How]
Move extra panel power sequencer settings into panel_cofig struct.
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Ian Chen
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 11 +++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +++---
From: Alvin Lee
[Why and How]
- Don't skip bottom and next odm pipe when calculating
num ways for subvp
- Don't need to double cache lines for DCC (divide by 256)
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource_helpers.c |
From: Anthony Koo
- Handle pipe split case for SubVP:
Pass in pipe split index for main and phantom pipes
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
From: Hugo Hu
[Why]
The desktop plane and full-screen game plane may have different
gamut remap coefficients, if switching between desktop and
full-screen game without updating the gamut remap will cause
incorrect color.
[How]
Update gamut remap if planes change.
Reviewed-by: Dmytro
From: zhikzhai
[why]
We have minimal pipe split transition method to avoid pipe
allocation outage.However, this method will invoke audio setup
which cause audio output stuck once pipe reallocate.
[how]
skip audio setup for pipelines which audio stream has been enabled
Reviewed-by: Charlene Liu
From: Alvin Lee
[Why and How]
- For driver disable cases in current implementation, if P-State
is unsupported or still supported by firmware, we force it
supported by DCN.
- SubVP now needs to be included in this case along with FPO.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
From: Aric Cyr
This version brings along following fixes:
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of memory channel count and width
- Fix SubVP and ODM relevant issues
- Fix pipe
Prepare fastrpc to the common dynamic dma-buf locking convention by
starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Acked-by: Srinivas Kandagatla
Signed-off-by: Dmitry Osipenko
---
drivers/misc/fastrpc.c | 6 +++---
1 file changed, 3 insertions(+), 3
Prepare OMAP DRM driver to the common dynamic dma-buf locking convention
by starting to use the unlocked versions of dma-buf API functions.
Acked-by: Christian König
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 4 ++--
1 file changed, 2 insertions(+), 2
The internal dma-buf lock isn't needed anymore because the updated
locking specification claims that dma-buf reservation must be locked
by importers, and thus, the internal data is already protected by the
reservation lock. Remove the obsoleted internal lock.
Acked-by: Christian König
Add documentation for the dynamic locking convention. The documentation
tells dma-buf API users when they should take the reservation lock and
when not.
Reviewed-by: Christian König
Signed-off-by: Dmitry Osipenko
---
Documentation/driver-api/dma-buf.rst | 6 +++
drivers/dma-buf/dma-buf.c
From: Alvin Lee
[Why & How]
- Pipe split prediction previously only took into
account MPC split. We must also consider when
ODM combine is required, and when we apply ODM
combine by policy.
- Also re-work DET allocation function as it wasn't
properly splitting the DET per stream, per plane.
From: Charlene Liu
[Why & How]
Support dramclk change latency change via debug option and add some
code isolation.
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 5 +
From: Leo Chen
[Why & How]
Added logs for panel delays, spread_spectrum_percentage,
and gpuclk_ss_percentage to facilitate debugging.
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Leo Chen
---
.../drm/amd/display/dc/bios/bios_parser2.c| 54 ++-
1 file
From: Dmytro Laktyushkin
[Why & How]
Correctly set ddr5 channel width to 8 bytes
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 3 +--
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 7
From: Aurabindo Pillai
[Why]
After reg offset initialization was switched to runtime rather than
compile time, some of the defintions are not needed anymore and can
be removed.
Acked-by: Wayne Lin
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 23
From: Chris Park
[Why]
420 modes are limited by FMT buffer width of 4096
which requires multi-pipe support in form of ODM
combine. If 420 modes have greater HActive than
4096, the DML logic should accomodate whether
it should be rejected, or ODM combine 2:1 or 4:1
is triggered accordingly.
From: Leo Li
[Why]
DC makes use of layer_index (zpos) when picking the HW plane to enable
HW cursor on. However, some compositors will not attach zpos information
to each DRM plane. Consequently, in amdgpu, we default layer_index to 0
and do not update it.
This causes said DC logic to enable
From: Alvin Lee
[Why and How]
- Only consider pixel rate div policy for DCN32+
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 16 ++--
.../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 --
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv
SDMA update page table may be called from unlocked context, this
generate below warning. Use unlocked iterator to handle this case.
WARNING: CPU: 0 PID: 1475 at
drivers/dma-buf/dma-resv.c:483 dma_resv_iter_next
Call Trace:
dma_resv_iter_first+0x43/0xa0
amdgpu_vm_sdma_update+0x69/0x2d0 [amdgpu]
Am 2022-09-13 um 09:19 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and
[AMD Official Use Only - General]
Thank Luben for the review. I replied inline and will update the patch.
Thanks,
Jiadong
-Original Message-
From: Tuikov, Luben
Sent: Tuesday, September 13, 2022 11:12 PM
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray
Subject: Re:
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
For DC version 3.2.203
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of memory channel count and width
- Fix
From: Alvin Lee
[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.
From: Alvin Lee
[Why & How]
Uncomment SubVP pipe split assignment in driver since FW headers
are now promoted
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4
1 file changed, 4 deletions(-)
diff --git
From: George Shen
[Why]
The urgent latency override is useful when debugging issues
relating to underflow.
Current overridden variable is not correct and has no effect
on DCN3.2 and DCN3.21 DML calculations.
[How]
For DCN3.2 and DCN3.21, override the correct urgent latency
variable when
From: zhikzhai
[why]
We have minimal pipe split transition method to avoid pipe
allocation outage.However, this method will invoke audio setup
which cause audio output stuck once pipe reallocate.
[how]
skip audio setup for pipelines which audio stream has been enabled
Reviewed-by: Charlene Liu
From: Sherry Wang
[Why]
Hostvm should be enabled/disabled accordding to
the status of riommu_active, but hostvm always
be disabled on DCN31 which causes underflow
[How]
Set correct hostvm flag on DCN31
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Sherry Wang
---
From: Pavle Kotarac
[WHY]
Adding new asic id for dcn301
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
From: Wenjing Liu
[Why]
There is a coding error when moving dp disable link phy to
hw sequencer, where the receiver power control is missed during
this refactor.
[how]
1. Add back missing receiver power control in disable link phy.
2. minor modifications to ensure there is no undesired sequence
From: Aric Cyr
This version brings along following fixes:
- Fix urgent latency override for DCN32/DCN321
- Correct hostvm flag in DCN31
- Added new Asic Id for DCN301
- Adjust to 2 phys in DCN301
- Update dummy P-state search to use DCN32 DML
- Increase dcn315 pstate change latency
- Disable OTG
From: Charlene Liu
[why]
update hw dccg based on HW delta, and reuse common src code
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 +
From: Charlene Liu
[why]
num_dsc is 3 for dcn314 based on HW capablity.
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Resend due to connection time out.
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
For DC version 3.2.203
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of
From: Wenjing Liu
[why]
When user unplugs mst hubs, the current code will forcefully zero
entire mst payload allocation table structure stored in link before we
deallocate actual payload when disabling stream.
During the first disable stream sequence, we will use current mst
payload allocation
From: Leo Chen
[Why & How]
Added logs for panel delays, spread_spectrum_percentage,
and gpuclk_ss_percentage to facilitate debugging.
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Leo Chen
---
.../drm/amd/display/dc/bios/bios_parser2.c| 54 ++-
1 file
From: Alvin Lee
[Why and How]
For SubVP pipe split case, pass in split index for
main and phantom pipes to ensure that the P-State
sequence will force P-State for all required pipes.
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
From: Alvin Lee
[Why and How]
- Add a debug option for allocating extra way for cursor
- Remove usage of cache_cursor_addr since it's not gaurenteed
to be populated
- Include cursor size in MALL calculation if it exceeds the
DCN cursor buffer size (and don't need extra way for cursor)
From: Alvin Lee
[Why and How]
- For driver disable cases in current implementation, if P-State
is unsupported or still supported by firmware, we force it
supported by DCN.
- SubVP now needs to be included in this case along with FPO.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
From: Aric Cyr
This version brings along following fixes:
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of memory channel count and width
- Fix SubVP and ODM relevant issues
- Fix pipe
From: Pavle Kotarac
[WHY]
New dcn301 has 2 less phys
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: George Shen
[Why]
Current DCN3.2 logic for finding the dummy P-state index uses the
DCN3.0 DML validation function instead of DCN3.2 DML.
This can result in either unexpected DML VBA values, or unexpected
dummy P-state index to be used.
[How]
Update the dummy P-state logic to use DCN3.2
From: Meenakshikumar Somasundaram
[Why]
During hot plug of specific 5K tiled display, sometimes both the tiles
are not synchronized resulting in distortion. The reason is that otgs of
both the tiles goes out of sync when otg workaround (dcnxxx_disable_otg_wa)
is applied for bandwidth
From: Charlene Liu
[why]
Expose few dchubbun functions in dcn31 and dcn32 to leverage.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 2 +-
.../drm/amd/display/dc/dcn31/dcn31_hubbub.h | 2 ++
On 2022-09-13 22:34, Zhu, Jiadong wrote:
>> +
>> + r_rptr = amdgpu_ring_get_rptr(mux->real_ring);
>> + r_wptr = amdgpu_ring_get_wptr(mux->real_ring);
>> These names are very much the same to a human. How about writep and readp?
> r_rptr for real ring's read ptr differed from sw_rptr.
From: Aurabindo Pillai
[Why and How]
Enable committing subvp config through DMCUB for DCN32
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 --
1 file changed, 2 deletions(-)
diff --git
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 2 +-
From: Jaehyun Chung
[Why]
v1_5 display object table has no way for connectors to
indicate which slot they are a part of, resulting in additional
empty slots to appear in EDID management UI.
[How]
Assume that all connectors belong to the same slot.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
From: Daniel Miess
[Why]
DP DSC compliance failing for dcn314 due to ICH_RESET_AT_END_OF_LINE
shift and mask being missing
[How]
Add in shift and mask for ICH_RESET_AT_END_OF_LINE
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Daniel Miess
---
From: muansari
[WHY]
The Vstartup position should be as late as possible to
maximize power saving with the current. Calculation of
Vstartup in DML does not take into account as SDP signal.
[HOW]
Made necessary changes to calculate the correct Vstartup
position in DML to account for AS SDP
*
From: Alvin Lee
[Why & How]
If we find that DML requires pipe split, run through
DML again because the DET allocation per pipe must
be re-assigned.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 26 +-
From: Josip Pavic
[Why & How]
Extend existing OTG state collection function to include the vertical
interrupt 1 state.
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 6 ++
From: Robin Chen
[Why]
The Sink device string ID1/ID2 use 5 bytes instead of 6 bytes,
so the driver should compare the first 5 bytes only.
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 7 ---
From: Nicholas Kazlauskas
[Why]
This shouldn't trigger during tiled display hotplug/unplug but it does
because one of the tiles can end up with a NULL plane state.
This also doesn't guard against the hang that it was originally trying
to resolve, and can instead cause DIO corruption due to OTG
From: Rodrigo Siqueira
[Why and How]
We are hitting k1/k2 assert when we are using a virtual signal in the
test; as a result, we are failing some automated tests with a false
positive. This commit addresses this issue by ignoring the assert
condition if we use SIGNAL_TYPE_VIRTUAL.
Reviewed-by:
From: Daniel Miess
[Why]
DP DSC compliance failing for dcn314 due to ICH_RESET_AT_END_OF_LINE
shift and mask being missing
[How]
Add in shift and mask for ICH_RESET_AT_END_OF_LINE
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Daniel Miess
---
From: muansari
[WHY]
The Vstartup position should be as late as possible to
maximize power saving with the current. Calculation of
Vstartup in DML does not take into account as SDP signal.
[HOW]
Made necessary changes to calculate the correct Vstartup
position in DML to account for AS SDP
*
From: Dmytro Laktyushkin
[Why & How]
Update after new measurment came in
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Dmytro Laktyushkin
---
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 22 ---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git
From: Cruise Hung
[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.
[How]
Updated verified_link_cap
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 2 +-
From: Aurabindo Pillai
[Why and How]
Enable committing subvp config through DMCUB for DCN32
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 --
1 file changed, 2 deletions(-)
diff --git
From: Nicholas Kazlauskas
[Why]
This shouldn't trigger during tiled display hotplug/unplug but it does
because one of the tiles can end up with a NULL plane state.
This also doesn't guard against the hang that it was originally trying
to resolve, and can instead cause DIO corruption due to OTG
From: Jaehyun Chung
[Why]
v1_5 display object table has no way for connectors to
indicate which slot they are a part of, resulting in additional
empty slots to appear in EDID management UI.
[How]
Assume that all connectors belong to the same slot.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
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