v1 - update the fw header for each vcn instance (Veera)
VCN1 has different FW binary in VCN v4_0_6.
Add changes to load the VCN1 fw binary
Signed-off-by: Saleemkhan Jamadar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 38 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2
Am 11.03.24 um 23:21 schrieb Philip Yang:
Otherwise amdgpu_ttm_backend_unbind will not clear the gart page table
and leave valid mapping entry to the stale system page.
Signed-off-by: Philip Yang
Good catch, that bug is probably in there for quite a while.
Reviewed-by: Christian König
[AMD Official Use Only - General]
Looks good to me.
Reviewed-by: Veerabadhran Gopalakrishnan
Regards,
Veera
-Original Message-
From: Jamadar, Saleemkhan
Sent: Tuesday, March 12, 2024 12:36 PM
To: amd-gfx@lists.freedesktop.org; Jamadar, Saleemkhan
; Liu, Leo ; Sundararaju,
Sometimes user may want to enable the od feature
by setting ppfeaturemask when loading amdgpu driver.
However,not all Asics support this feature.
So we need to restore the ppfeature value and print
a warning info.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15
From: Sherry Wang
[Why]
Hostvm should be enabled/disabled accordding to the status of
riommu_active, but hostvm always be disabled on DCN31 which causes
underflow
[How]
Set correct hostvm flag on DCN31
Acked-by: Wayne Lin
Signed-off-by: Sherry Wang
---
From: Rodrigo Siqueira
[Why & How]
This commit just drop some old comments and update a typo in another
one.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
From: Rodrigo Siqueira
[Why & How]
Registers and offset are missing. Add it back
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
.../include/asic_reg/dcn/dcn_3_2_1_offset.h | 37 ++-
.../include/asic_reg/dcn/dcn_3_2_1_sh_mask.h | 16
2 files changed, 52
From: Leo Ma
[Why]
When mode switching is triggered there is momentary noise visible on
some HDMI TV or displays.
[How]
Wait for 2 frames to make sure we have enough time to send out AV mute
and sink receives a full frame.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
From: Rodrigo Siqueira
[Why & How]
DCN3_16_MIN_COMPBUF_SIZE_KB is defined in the dcn316_resource.c file.
This header fit better in the dcn31_fpu.h together with similar defines.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
From: Rodrigo Siqueira
[Why & How]
If the driver has issues retrieving the MALL size for the specific
hardware, it might fail since the current value is set to zero. This
commit addresses this issue by adding a simple constant value to give
the drive a chance to start.
Acked-by: Wayne Lin
From: Rodrigo Siqueira
[Why & How]
Remove legacy code which is unnecessary.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
.../dc/resource/dcn314/dcn314_resource.c | 20 ---
1 file changed, 20 deletions(-)
diff --git
From: Rodrigo Siqueira
[Why & How]
Enable legacy fast update for DCN314
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Charlene Liu
[why]
APU has different refclk as dGPU which is used for AUX_DPHY setup
Reviewed-by: Chris Park
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 2 +-
From: Nicholas Kazlauskas
[Why]
Cursor update can be pre-empted by a request for setting target flip
submission.
This causes an issue where we're in the middle of the exit sequence
trying to log to DM, but the pre-emption starts another DMCUB
command submission that requires being out of idle.
From: Wenjing Liu
This reverts commit 6cf00f4c4d5c ("drm/amd/display: Remove pixle rate
limit for subvp")
[why]
The original commit causes a regression when subvp is applied
on ODM required 8k60hz timing. The display shows black screen
on boot. The issue can be recovered with hotplug. It also
From: Natanel Roizenman
Added debug prints for zstate_support and StutterPeriod in
dcn35_decide_zstate_support for testing.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Natanel Roizenman
---
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4
1 file
From: Chris Park
[Why]
Disabling stream encoder invokes a function that no longer exists
in bring-up.
[How]
Check if the function declaration is NULL in disable stream encoder.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
From: Dillon Varone
[WHY]
Even if memory lower power feature policy states that it is disabled,
VPG memory should still be poweerd on if it is currently disabled when
requested.
Reviewed-by: Chris Park
Acked-by: Wayne Lin
Signed-off-by: Dillon Varone
---
From: Charlene Liu
[why]
need to apply the debug key check for max displayclk.
Reviewed-by: Chris Park
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Natanel Roizenman
Increase Z8 watermark times from 210->250us and 320->350us.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Natanel Roizenman
---
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 ++--
Am 12.03.24 um 10:35 schrieb Sharma, Shashank:
On 12/03/2024 09:31, Christian König wrote:
Am 11.03.24 um 15:37 schrieb Sharma, Shashank:
On 07/03/2024 20:22, Philip Yang wrote:
On 2024-03-06 09:41, Shashank Sharma wrote:
From: Christian König
The problem is that when (for example) 4k
Hi,
On 2024/2/27 18:14, Thomas Zimmermann wrote:
Temporarily lock the fbdev buffer object during updates to prevent
memory managers from evicting/moving the buffer. Moving a buffer
object while update its content results in undefined behaviour.
Fbdev-generic updates its buffer object from a
On Mon, 26 Feb 2024 16:10:22 -0500
Harry Wentland wrote:
> v4:
> - Drop IOCTL docs since we dropped the IOCTLs (Pekka)
> - Clarify reading and setting of COLOR_PIPELINE prop (Pekka)
> - Add blurb about not requiring to reject a pipeline due to
>incompatible ops, as long as op can be
On Mon, 26 Feb 2024 16:10:20 -0500
Harry Wentland wrote:
> Debugging LUT math is much easier when we can unit test
> it. Add kunit functionality to VKMS and add tests for
> - get_lut_index
> - lerp_u16
>
> v4:
> - Test the critical points of the lerp function (Pekka)
>
> v3:
> - Use
On Mon, 26 Feb 2024 16:10:17 -0500
Harry Wentland wrote:
> A value of 0x8000 and higher should round up, and
> below should round down. VKMS Kunit tests for lerp_u16
> showed that this is not the case. Fix it.
>
> 1 << (DRM_FIXED_POINT_HALF - 1) =
> 1 << 15 = 0x8000
>
> This is not 0.5,
Hi,
On 2024/2/27 18:14, Thomas Zimmermann wrote:
Acquire the buffer object's reservation lock in drm_gem_pin() and
remove locking the drivers' GEM callbacks where necessary. Same for
unpin().
DRM drivers and memory managers modified by this patch will now have
correct dma-buf locking
On 11/03/2024 14:48, Tvrtko Ursulin wrote:
Hi Felix,
On 06/12/2023 21:23, Felix Kuehling wrote:
Executive Summary: We need to add CRIU support to DRM render nodes in
order to maintain CRIU support for ROCm application once they start
relying on render nodes for more GPU memory management.
From: Sung Joon Kim
[why & how]
To enable a new interface so alternate scrambling can be done via
security module.
Reviewed-by: Wenjing Liu
Acked-by: Wayne Lin
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/link/link_dpms.c
From: Nicholas Kazlauskas
[Why]
It was previously disabled for stability purposes, but command
submission causes residency issues in IPS video playback.
[How]
Enable the disallow/reallow pattern back. There's additional checks
now in DMCUB that should make this safer stability wise.
From: Wenjing Liu
[why]
During minimal transition commit, the base state could be freed if it is
current state.
This is because after committing minimal transition state, the current state
will be
swapped to the minimal transition state and the old current state will be
released.
the release
From: Xi Liu
[Why and how]
Bounding box clocks for DCN351 should be increased as per request
Reviewed-by: Swapnil Patel
Acked-by: Wayne Lin
Signed-off-by: Xi Liu
---
.../amd/display/dc/dml/dcn351/dcn351_fpu.c| 90 ---
1 file changed, 76 insertions(+), 14 deletions(-)
From: Nicholas Kazlauskas
[Why]
Cursor updates can be preempted by queued flips in some DMs.
The synchronization model causes this to occur within the same thread
at an intermediate level when we insert logs into the OS queue.
Since this occurs on the same thread and we're still holding the
From: Aric Cyr
This version brings along following fixes:
- Fix few problems for DCN35
- Fix a bug which dereferences freed memory
- Enable new interface design for alternate scrambling
- Enhance IPS handshake
- Increase Z8 watermark times
- Fix DML2 problem
- Revert patch which cause regression
From: Nicholas Kazlauskas
[Why]
To reduce the handshake overhead for static screen and video playback.
[How]
Flip the debug option to enable by default.
Reviewed-by: Duncan Ma
Acked-by: Wayne Lin
Signed-off-by: Nicholas Kazlauskas
---
From: Xi Liu
[Why]
The hard coded DPM states are only used to fix mismatch states numbers from FW.
[How]
Remove when not needed.
Reviewed-by: Sung joon Kim
Acked-by: Wayne Lin
Signed-off-by: Xi Liu
---
.../display/dc/dml2/dml2_translation_helper.c | 17 +++--
1 file
From: Nicholas Kazlauskas
[Why]
It's possible to skip parts of the eval and exit sequencing if we know
whether DCN is in IPS2 already or if it's committed to going to idle
and not in IPS2.
[How]
Skip IPS2 entry/exit if DMCUB is idle but the IPS2 commit is not set.
Skip the eval delay if DMCUB
From: Chaitanya Dhere
[Why & How]
For DML2 to decouple it from other DML versions.
Reviewed-by: Dillon Varone
Acked-by: Wayne Lin
Signed-off-by: Chaitanya Dhere
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 12/03/2024 09:31, Christian König wrote:
Am 11.03.24 um 15:37 schrieb Sharma, Shashank:
On 07/03/2024 20:22, Philip Yang wrote:
On 2024-03-06 09:41, Shashank Sharma wrote:
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need
Just another general comment on how to upstream patches.
When publishing a large set of patches it is usually good convention to
sort them:
1. Bug fixes which might even get backported
2. Comment and other non function cleanups
3. Functional cleanups
4. New features
One good reason for that
From: Dillon Varone
[WHY]
Stream clock source is a required parameter for DP DTO programming.
Reviewed-by: Chris Park
Acked-by: Wayne Lin
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Nicholas Kazlauskas
[Why]
Leave disabled by default due to sequencing issues around power states
where these flags aren't properly reset.
[How]
Allow re-enabling from DC debug option.
Reviewed-by: Gabe Teeger
Acked-by: Wayne Lin
Signed-off-by: Nicholas Kazlauskas
---
From: Zhongwei
[Why]
OLED panels show no display for large vtotal timings.
[How]
Check if spread spectrum is enabled and read from lut for spread spectrum
percentage. Adjust dprefclk as required.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Zhongwei
---
From: Gabe Teeger
This reverts commit 97c109f498da ("drm/amd/display: Add left edge pixel for
YCbCr422/420 + ODM pipe split")
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: George Shen
Reviewed-by: Charlene Liu
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
From: Ovidiu Bunea
This reverts commit 1b35616f8bdb ("drm/amd/display: Set the power_down_on_boot
function pointer to null")
[why & how]
This commit breaks S0i3 entry because DCN does not enter IPS2.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas
From: Dillon Varone
[WHY]
Pixel clock programming should be built per dcn revision, not hardcoded to use
dcn20.
Reviewed-by: Chris Park
Acked-by: Wayne Lin
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 7 ++-
1 file changed, 6
From: Samson Tam
[Why]
During init_pipes, otg master is not initialized. So mpc tree is
still configured even if mpc bottom is not active
[How]
For pipes that have tg enabled, check their mpc tree and clear
opp_list if mpc bottom is not active
Reviewed-by: George Shen
Acked-by: Wayne Lin
From: Wenjing Liu
[why]
In minial transitions state, ODM combine shouldn't be forced as it will
make transition non seamless. The force ODM debug option is to control
the end result not the intermediate transition. So we can temporarily
disable ODM forcing when committing minimal transition
From: Martin Leung
why and how:
causes black screen on PNP on DCN 3.5
This reverts commit 520b0596f978 ("drm/amd/display: Exit idle
optimizations before HDCP execution")
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
From: Nicholas Susanto
[Why]
Underflow occurs when running netflix in a 4k144 eDP + 4k60 setup.
Increasing DCFCLK or urgent latency watermark fixes the issue. Implementing
this workaround for now while we figure out why this is happenning in DCN.
[How]
Enable urgent latency adjustment and
From: Aric Cyr
This version brings along following fixes:
- Clear mpc_tree in init_pipes
- Program pixclk according to dcn revision
- Add stream clock source to DP DTO params
- Enabling urgent latency adjustment for DCN35
- To adjust dprefclk by down spread percentage
- Add debug option for idle
From: Anthony Koo
- Add a Replay residency mode which only calcuates the
entry time based on replay state 0/1 switch.
Acked-by: Wayne Lin
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
Am 11.03.24 um 15:37 schrieb Sharma, Shashank:
On 07/03/2024 20:22, Philip Yang wrote:
On 2024-03-06 09:41, Shashank Sharma wrote:
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Clear mpc_tree in init_pipes
- Program pixclk according to dcn revision
- Add stream clock source to DP DTO params
- Enabling urgent latency adjustment for DCN35
- To adjust dprefclk by down spread percentage
-
From: Alex Hung
[Why & How]
dcn32_smu_transfer_wm_table_dram_2_smu is defined twice so one is
removed. Also adjust prototype orders.
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
.../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 3 +--
1 file changed, 1 insertion(+), 2
From: Alex Hung
[Why & How]
This fixes indentations and adjust spaces for better readability and
code styles.
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/dc/bios/bios_parser.c | 1 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 15 ---
From: Rodrigo Siqueira
[Why & How]
Remove redundant code
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
From: Rodrigo Siqueira
In some of the merge conflict fixes, one '+' was accidentally left at
the beginning of the line. Fortunately, this did not cause any major
issues since it acted as a number signal. This commit addresses this
issue by removing the extra '+'.
Acked-by: Wayne Lin
From: Rodrigo Siqueira
[Why & How]
Enable 2to1 ODM policy for DCN35
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 3/12/2024 4:29 PM, Ma Jun wrote:
> Sometimes user may want to enable the od feature
> by setting ppfeaturemask when loading amdgpu driver.
> However,not all Asics support this feature.
> So we need to restore the ppfeature value and print
> a warning info.
>
> Signed-off-by: Ma Jun
> ---
>
We need the min/max vfreq on the amdgpu_dm_connector in order to
program VRR.
Fixes: db3e4f1cbb84 ("drm/amd/display: Use freesync when
`DRM_EDID_FEATURE_CONTINUOUS_FREQ` found")
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +--
1 file changed, 5
Add all the IP's information on a SOC to the
devcoredump.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
Add firmware version information of each
IP and each instance where applicable.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 122 ++
1 file changed, 122 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
On Tue, Mar 12, 2024 at 9:57 AM Harry Wentland wrote:
>
> We need the min/max vfreq on the amdgpu_dm_connector in order to
> program VRR.
>
> Fixes: db3e4f1cbb84 ("drm/amd/display: Use freesync when
> `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found")
> Signed-off-by: Harry Wentland
> ---
>
On Tuesday, March 12th, 2024 at 16:02, Pekka Paalanen
wrote:
> This list here is the list of all values the enum could take, right?
> Should it not be just the one value it's going to have? It'll never
> change, and it can never be changed.
Listing all possible values is how other properties
This causes flicker on a bunch of eDP panels. The info_packet code
also caused regressions on other OSes that we haven't' seen on Linux
yet, but that is likely due to the fact that we haven't had a chance
to test those environments on Linux.
We'll need to revisit this.
This reverts commit
On 2024-03-12 10:58, Alex Deucher wrote:
> On Tue, Mar 12, 2024 at 9:57 AM Harry Wentland wrote:
>>
>> We need the min/max vfreq on the amdgpu_dm_connector in order to
>> program VRR.
>>
>> Fixes: db3e4f1cbb84 ("drm/amd/display: Use freesync when
>> `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found")
On 2024-01-01 13:28, Joshua Ashton wrote:
> The check for sending the vsc infopacket to the display was gated behind
> PSR (Panel Self Refresh) being enabled.
>
> The vsc infopacket also contains the colorimetry (specifically the
> container color gamut) information for the stream on modern
This patch removes an unused input variable in the MES
doorbell function.
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git
On 3/13/2024 8:15 AM, Ma, Jun wrote:
>
>
> On 3/12/2024 8:57 PM, Lazar, Lijo wrote:
>>
>>
>> On 3/12/2024 4:29 PM, Ma Jun wrote:
>>> Sometimes user may want to enable the od feature
>>> by setting ppfeaturemask when loading amdgpu driver.
>>> However,not all Asics support this feature.
>>> So
On 3/12/2024 8:57 PM, Lazar, Lijo wrote:
>
>
> On 3/12/2024 4:29 PM, Ma Jun wrote:
>> Sometimes user may want to enable the od feature
>> by setting ppfeaturemask when loading amdgpu driver.
>> However,not all Asics support this feature.
>> So we need to restore the ppfeature value and print
From: Victor Skvortsov
Host will initiate an FLR in SDMA poison consumption scenario.
Guest should wait for FLR message to re-init data exchange.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On 2024-03-08 14:00, Ahmad Rehman wrote:
In passthrough environment, when amdgpu is reloaded after unload, mode-1
is triggered after initializing the necessary IPs, That init does not
include KFD, and KFD init waits until the reset is completed. KFD init
is called in the reset handler, but in
Use amdgpu_vram_mgr to reserve bad page ranges.
Reserved ranges will be freed by amdgpu_vram_mgr_fini()
Delete bo_create path as it is redundant.
Suggested-by: Christian König
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 55 ++--
On 02/26, Harry Wentland wrote:
> This aligns with most other DRM drivers and will allow
> us to add new VKMS config options without polluting
> the DRM Kconfig.
>
> v3:
> - Change SPDX to GPL-2.0-only to match DRM KConfig
>SPDX (Simon)
>
> Signed-off-by: Harry Wentland
> Reviewed-by:
On 02/26, Harry Wentland wrote:
> When the floor LUT index (drm_fixp2int(lut_index) is the last
> index of the array the ceil LUT index will point to an entry
> beyond the array. Make sure we guard against it and use the
> value of the floor LUT index.
>
> v3:
> - Drop bits from commit
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