[PATCH 2/2] drm/amdgpu/si/dpm: fix phase shedding setup

2016-09-27 Thread Alex Deucher 
Used the wrong index to setup the phase shedding mask.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/sislands_smc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 73ccf33..8bd0892 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4593,7 +4593,7 @@ static int si_populate_smc_voltage_tables(struct 
amdgpu_device *adev,
  
>pm.dpm.dyn_state.phase_shedding_limits_table)) {
si_populate_smc_voltage_table(adev, 
_pi->vddc_phase_shed_table, table);
 
-   
table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
+   
table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =

cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
 
si_write_smc_soft_register(adev, 
SI_SMC_SOFT_REGISTER_phase_shedding_delay,
diff --git a/drivers/gpu/drm/amd/amdgpu/sislands_smc.h 
b/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
index ee4b846..d2930ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
+++ b/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
@@ -194,6 +194,7 @@ typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
 #define SISLANDS_SMC_VOLTAGEMASK_VDDC  0
 #define SISLANDS_SMC_VOLTAGEMASK_MVDD  1
 #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
+#define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
 #define SISLANDS_SMC_VOLTAGEMASK_MAX   4
 
 struct SISLANDS_SMC_VOLTAGEMASKTABLE
-- 
2.5.5

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[pull] radeon and amdgpu drm-fixes-4.8

2016-09-27 Thread Alex Deucher 
Hi Dave,

Just a couple of small fixes for 4.8:
- dpm stability fix for some SI parts
- fix a regression in 4.8 on display tear down

The following changes since commit 47a66e45d7a7613322549c2475ea9d809baaf514:

  drm: Only use compat ioctl for addfb2 on X86/IA64 (2016-09-19 17:28:20 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.8

for you to fetch changes up to 670bb4fd21c966d0d2a59ad4a99bb4889f9a2987:

  drm/radeon/si/dpm: add workaround for for Jet parts (2016-09-27 12:22:29 
-0400)


Alex Deucher (1):
  drm/radeon/si/dpm: add workaround for for Jet parts

Grazvydas Ignotas (1):
  drm/amdgpu: disable CRTCs before teardown

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 drivers/gpu/drm/radeon/si_dpm.c| 6 ++
 2 files changed, 7 insertions(+), 1 deletion(-)
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[PATCH 2/2] drm/amdgpu/si/dpm: sync up quirks from radeon

2016-09-27 Thread Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index e2db4a7..73ccf33 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3023,9 +3023,12 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = {
/* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
{ PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 12 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 12 },
+   { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 12 },
{ PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 9 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 12 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 12 },
+   { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 12 },
+   { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 12 },
{ 0, 0, 0, 0 },
 };
 
@@ -3486,6 +3489,16 @@ static void si_apply_state_adjust_rules(struct 
amdgpu_device *adev,
}
++p;
}
+   /* limit mclk on all R7 370 parts for stability */
+   if (adev->pdev->device == 0x6811 &&
+   adev->pdev->revision == 0x81)
+   max_mclk = 12;
+   /* limit sclk/mclk on Jet parts for stability */
+   if (adev->pdev->device == 0x6665 &&
+   adev->pdev->revision == 0xc3) {
+   max_sclk = 75000;
+   max_mclk = 8;
+   }
 
if (rps->vce_active) {
rps->evclk = 
adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
-- 
2.5.5

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Re: [PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry' directly

2016-09-27 Thread Edward O'Callaghan 
Excellent point Christian, it did occur to me that endianness could be a
problem so will definitely fix this one up as Tom suggested.

Kind Regards,
Edward.

On 09/27/2016 11:02 PM, StDenis, Tom wrote:
> Better would be to add them to a bitmask header and then use
> REG_GET_FIELD() so it's nice and clean looking.
> 
> 
> Tom
> 
> 
> 
> 
> *From:* amd-gfx  on behalf of
> Christian König 
> *Sent:* Tuesday, September 27, 2016 08:52
> *To:* Edward O'Callaghan; amd-gfx@lists.freedesktop.org
> *Subject:* Re: [PATCH 2/2] drm/amdkfd: Decode bit fields in
> 'cik_ih_ring_entry' directly
>  
> NAK, don't use bitfields to decode hardware values. They aren't portable.
> 
> Regards,
> Christian.
> 
> Am 27.09.2016 um 14:47 schrieb Edward O'Callaghan:
>> Signed-off-by: Edward O'Callaghan 
>> ---
>>   drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 15 +--
>>   drivers/gpu/drm/amd/amdkfd/cik_int.h | 20 
>>   2 files changed, 21 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c 
>> b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> index 211fc48..1c47b9e 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> @@ -27,14 +27,12 @@
>>   static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>>const uint32_t *ih_ring_entry)
>>   {
>> - unsigned int pasid;
>>const struct cik_ih_ring_entry *ihre =
>>(const struct cik_ih_ring_entry *)ih_ring_entry;
>>   
>> - pasid = (ihre->ring_id & 0x) >> 16;
>>   
>>/* Do not process in ISR, just request it to be forwarded to WQ. */
>> - return (pasid != 0) &&
>> + return (ihre->pasid != 0) &&
>>(ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE ||
>>ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG ||
>>ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE);
>> @@ -43,21 +41,18 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>>   static void cik_event_interrupt_wq(struct kfd_dev *dev,
>>const uint32_t *ih_ring_entry)
>>   {
>> - unsigned int pasid;
>>const struct cik_ih_ring_entry *ihre =
>>(const struct cik_ih_ring_entry *)ih_ring_entry;
>>   
>> - pasid = (ihre->ring_id & 0x) >> 16;
>> -
>> - if (pasid == 0)
>> + if (ihre->pasid == 0)
>>return;
>>   
>>if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE)
>> - kfd_signal_event_interrupt(pasid, 0, 0);
>> + kfd_signal_event_interrupt(ihre->pasid, 0, 0);
>>else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG)
>> - kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8);
>> + kfd_signal_event_interrupt(ihre->pasid, ihre->data & 0xFF, 8);
>>else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE)
>> - kfd_signal_hw_exception_event(pasid);
>> + kfd_signal_hw_exception_event(ihre->pasid);
>>   }
>>   
>>   const struct kfd_event_interrupt_class event_interrupt_class_cik = {
>> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h 
>> b/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> index 79a16d2..27d1ede 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> +++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> @@ -26,10 +26,22 @@
>>   #include 
>>   
>>   struct cik_ih_ring_entry {
>> - uint32_t source_id;
>> - uint32_t data;
>> - uint32_t ring_id;
>> - uint32_t reserved;
>> + uint32_t source_id:8;
>> + uint32_t reserved1:8;
>> + uint32_t reserved2:16;
>> +
>> + uint32_t data:28;
>> + uint32_t reserved3:4;
>> +
>> + /* pipeid, meid and unused3 are officially called RINGID,
>> +  * but for our purposes, they always decode into pipe and ME. */
>> + uint32_t pipeid:2;
>> + uint32_t meid:2;
>> + uint32_t reserved4:4;
>> + uint32_t vmid:8;
>> + uint32_t pasid:16;
>> +
>> + uint32_t reserved5;
>>   };
>>   
>>   #define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6
> 
> 
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Re: [PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry' directly

2016-09-27 Thread StDenis, Tom 
Better would be to add them to a bitmask header and then use REG_GET_FIELD() so 
it's nice and clean looking.


Tom



From: amd-gfx  on behalf of Christian 
König 
Sent: Tuesday, September 27, 2016 08:52
To: Edward O'Callaghan; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry' 
directly

NAK, don't use bitfields to decode hardware values. They aren't portable.

Regards,
Christian.

Am 27.09.2016 um 14:47 schrieb Edward O'Callaghan:
> Signed-off-by: Edward O'Callaghan 
> ---
>   drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 15 +--
>   drivers/gpu/drm/amd/amdkfd/cik_int.h | 20 
>   2 files changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c 
> b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> index 211fc48..1c47b9e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> @@ -27,14 +27,12 @@
>   static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>const uint32_t *ih_ring_entry)
>   {
> - unsigned int pasid;
>const struct cik_ih_ring_entry *ihre =
>(const struct cik_ih_ring_entry *)ih_ring_entry;
>
> - pasid = (ihre->ring_id & 0x) >> 16;
>
>/* Do not process in ISR, just request it to be forwarded to WQ. */
> - return (pasid != 0) &&
> + return (ihre->pasid != 0) &&
>(ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE ||
>ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG ||
>ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE);
> @@ -43,21 +41,18 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>   static void cik_event_interrupt_wq(struct kfd_dev *dev,
>const uint32_t *ih_ring_entry)
>   {
> - unsigned int pasid;
>const struct cik_ih_ring_entry *ihre =
>(const struct cik_ih_ring_entry *)ih_ring_entry;
>
> - pasid = (ihre->ring_id & 0x) >> 16;
> -
> - if (pasid == 0)
> + if (ihre->pasid == 0)
>return;
>
>if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE)
> - kfd_signal_event_interrupt(pasid, 0, 0);
> + kfd_signal_event_interrupt(ihre->pasid, 0, 0);
>else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG)
> - kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8);
> + kfd_signal_event_interrupt(ihre->pasid, ihre->data & 0xFF, 8);
>else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE)
> - kfd_signal_hw_exception_event(pasid);
> + kfd_signal_hw_exception_event(ihre->pasid);
>   }
>
>   const struct kfd_event_interrupt_class event_interrupt_class_cik = {
> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h 
> b/drivers/gpu/drm/amd/amdkfd/cik_int.h
> index 79a16d2..27d1ede 100644
> --- a/drivers/gpu/drm/amd/amdkfd/cik_int.h
> +++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h
> @@ -26,10 +26,22 @@
>   #include 
>
>   struct cik_ih_ring_entry {
> - uint32_t source_id;
> - uint32_t data;
> - uint32_t ring_id;
> - uint32_t reserved;
> + uint32_t source_id:8;
> + uint32_t reserved1:8;
> + uint32_t reserved2:16;
> +
> + uint32_t data:28;
> + uint32_t reserved3:4;
> +
> + /* pipeid, meid and unused3 are officially called RINGID,
> +  * but for our purposes, they always decode into pipe and ME. */
> + uint32_t pipeid:2;
> + uint32_t meid:2;
> + uint32_t reserved4:4;
> + uint32_t vmid:8;
> + uint32_t pasid:16;
> +
> + uint32_t reserved5;
>   };
>
>   #define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6


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Re: [PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry' directly

2016-09-27 Thread Oded Gabbay 
Christian is correct. That is not portable to other architectures

Oded

On Tue, Sep 27, 2016 at 3:52 PM, Christian König
 wrote:
> NAK, don't use bitfields to decode hardware values. They aren't portable.
>
> Regards,
> Christian.
>
>
> Am 27.09.2016 um 14:47 schrieb Edward O'Callaghan:
>>
>> Signed-off-by: Edward O'Callaghan 
>> ---
>>   drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 15 +--
>>   drivers/gpu/drm/amd/amdkfd/cik_int.h | 20
>> 
>>   2 files changed, 21 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> index 211fc48..1c47b9e 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> @@ -27,14 +27,12 @@
>>   static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>> const uint32_t *ih_ring_entry)
>>   {
>> -   unsigned int pasid;
>> const struct cik_ih_ring_entry *ihre =
>> (const struct cik_ih_ring_entry *)ih_ring_entry;
>>   - pasid = (ihre->ring_id & 0x) >> 16;
>> /* Do not process in ISR, just request it to be forwarded to WQ.
>> */
>> -   return (pasid != 0) &&
>> +   return (ihre->pasid != 0) &&
>> (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE ||
>> ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG ||
>> ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE);
>> @@ -43,21 +41,18 @@ static bool cik_event_interrupt_isr(struct kfd_dev
>> *dev,
>>   static void cik_event_interrupt_wq(struct kfd_dev *dev,
>> const uint32_t *ih_ring_entry)
>>   {
>> -   unsigned int pasid;
>> const struct cik_ih_ring_entry *ihre =
>> (const struct cik_ih_ring_entry *)ih_ring_entry;
>>   - pasid = (ihre->ring_id & 0x) >> 16;
>> -
>> -   if (pasid == 0)
>> +   if (ihre->pasid == 0)
>> return;
>> if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE)
>> -   kfd_signal_event_interrupt(pasid, 0, 0);
>> +   kfd_signal_event_interrupt(ihre->pasid, 0, 0);
>> else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG)
>> -   kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8);
>> +   kfd_signal_event_interrupt(ihre->pasid, ihre->data & 0xFF,
>> 8);
>> else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE)
>> -   kfd_signal_hw_exception_event(pasid);
>> +   kfd_signal_hw_exception_event(ihre->pasid);
>>   }
>> const struct kfd_event_interrupt_class event_interrupt_class_cik = {
>> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> b/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> index 79a16d2..27d1ede 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> +++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> @@ -26,10 +26,22 @@
>>   #include 
>> struct cik_ih_ring_entry {
>> -   uint32_t source_id;
>> -   uint32_t data;
>> -   uint32_t ring_id;
>> -   uint32_t reserved;
>> +   uint32_t source_id:8;
>> +   uint32_t reserved1:8;
>> +   uint32_t reserved2:16;
>> +
>> +   uint32_t data:28;
>> +   uint32_t reserved3:4;
>> +
>> +   /* pipeid, meid and unused3 are officially called RINGID,
>> +* but for our purposes, they always decode into pipe and ME. */
>> +   uint32_t pipeid:2;
>> +   uint32_t meid:2;
>> +   uint32_t reserved4:4;
>> +   uint32_t vmid:8;
>> +   uint32_t pasid:16;
>> +
>> +   uint32_t reserved5;
>>   };
>> #define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6
>
>
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Additional amdkfd cleanups for 4.9

2016-09-27 Thread Edward O'Callaghan 
These additional minor changes apply on top of my previous set. Nothing
too interesting here just yet more clean ups to make way for future changes.

Please review,
Kind Regards,

Edward O'Callaghan (2):
 [PATCH 1/2] drm/amdkfd: Use kfd_vm_info struct to carry consts state
 [PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry'
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[PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry' directly

2016-09-27 Thread Edward O'Callaghan 
Signed-off-by: Edward O'Callaghan 
---
 drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 15 +--
 drivers/gpu/drm/amd/amdkfd/cik_int.h | 20 
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c 
b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
index 211fc48..1c47b9e 100644
--- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
@@ -27,14 +27,12 @@
 static bool cik_event_interrupt_isr(struct kfd_dev *dev,
const uint32_t *ih_ring_entry)
 {
-   unsigned int pasid;
const struct cik_ih_ring_entry *ihre =
(const struct cik_ih_ring_entry *)ih_ring_entry;
 
-   pasid = (ihre->ring_id & 0x) >> 16;
 
/* Do not process in ISR, just request it to be forwarded to WQ. */
-   return (pasid != 0) &&
+   return (ihre->pasid != 0) &&
(ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE ||
ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG ||
ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE);
@@ -43,21 +41,18 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
 static void cik_event_interrupt_wq(struct kfd_dev *dev,
const uint32_t *ih_ring_entry)
 {
-   unsigned int pasid;
const struct cik_ih_ring_entry *ihre =
(const struct cik_ih_ring_entry *)ih_ring_entry;
 
-   pasid = (ihre->ring_id & 0x) >> 16;
-
-   if (pasid == 0)
+   if (ihre->pasid == 0)
return;
 
if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE)
-   kfd_signal_event_interrupt(pasid, 0, 0);
+   kfd_signal_event_interrupt(ihre->pasid, 0, 0);
else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG)
-   kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8);
+   kfd_signal_event_interrupt(ihre->pasid, ihre->data & 0xFF, 8);
else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE)
-   kfd_signal_hw_exception_event(pasid);
+   kfd_signal_hw_exception_event(ihre->pasid);
 }
 
 const struct kfd_event_interrupt_class event_interrupt_class_cik = {
diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h 
b/drivers/gpu/drm/amd/amdkfd/cik_int.h
index 79a16d2..27d1ede 100644
--- a/drivers/gpu/drm/amd/amdkfd/cik_int.h
+++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h
@@ -26,10 +26,22 @@
 #include 
 
 struct cik_ih_ring_entry {
-   uint32_t source_id;
-   uint32_t data;
-   uint32_t ring_id;
-   uint32_t reserved;
+   uint32_t source_id:8;
+   uint32_t reserved1:8;
+   uint32_t reserved2:16;
+
+   uint32_t data:28;
+   uint32_t reserved3:4;
+
+   /* pipeid, meid and unused3 are officially called RINGID,
+* but for our purposes, they always decode into pipe and ME. */
+   uint32_t pipeid:2;
+   uint32_t meid:2;
+   uint32_t reserved4:4;
+   uint32_t vmid:8;
+   uint32_t pasid:16;
+
+   uint32_t reserved5;
 };
 
 #define CIK_INTSRC_DEQUEUE_COMPLETE0xC6
-- 
2.7.4

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[PATCH 1/2] drm/amdkfd: Use kfd_vm_info struct to carry consts state

2016-09-27 Thread Edward O'Callaghan 
Use a struct to carry the calculated const state inside the
main kfd_dev state to use where we need it. Minor cleanups
while we are here.

Signed-off-by: Edward O'Callaghan 
---
 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c|  9 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c|  7 +++
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 13 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  3 ---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  7 +++
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  2 +-
 6 files changed, 23 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
index d5e19b5..2114c66 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
@@ -800,13 +800,8 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, 
struct kfd_process *p)
union GRBM_GFX_INDEX_BITS reg_gfx_index;
struct kfd_process_device *pdd;
struct dbg_wave_control_info wac_info;
-   int temp;
-   int first_vmid_to_scan = 8;
-   int last_vmid_to_scan = 15;
-
-   first_vmid_to_scan = ffs(dev->shared_resources.compute_vmid_bitmap) - 1;
-   temp = dev->shared_resources.compute_vmid_bitmap >> first_vmid_to_scan;
-   last_vmid_to_scan = first_vmid_to_scan + ffz(temp);
+   int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
+   int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
 
reg_sq_cmd.u32All = 0;
status = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 3f95f7c..2417b44 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -223,9 +223,16 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 const struct kgd2kfd_shared_resources *gpu_resources)
 {
unsigned int size;
+   unsigned int vmid_bitmap_kfd;
 
kfd->shared_resources = *gpu_resources;
 
+   vmid_bitmap_kfd = kfd->shared_resources.compute_vmid_bitmap;
+   kfd->vm_info.first_vmid_kfd = ffs(vmid_bitmap_kfd) - 1;
+   kfd->vm_info.last_vmid_kfd = fls(vmid_bitmap_kfd) - 1;
+   kfd->vm_info.vmid_num_kfd = 1 + kfd->vm_info.last_vmid_kfd
+   - kfd->vm_info.first_vmid_kfd;
+
/* calculate max size of mqds needed for queues */
size = max_num_of_queues_per_device *
kfd->device_info->mqd_size_aligned;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index f49c551..f13058c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -100,11 +100,11 @@ static int allocate_vmid(struct device_queue_manager *dqm,
if (dqm->vmid_bitmap == 0)
return -ENOMEM;
 
-   bit = find_first_bit((unsigned long *)>vmid_bitmap, CIK_VMID_NUM);
+   bit = find_first_bit((unsigned long *)>vmid_bitmap,
+   dqm->dev->vm_info.vmid_num_kfd);
clear_bit(bit, (unsigned long *)>vmid_bitmap);
 
-   /* Kaveri kfd vmid's starts from vmid 8 */
-   allocated_vmid = bit + KFD_VMID_START_OFFSET;
+   allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
pr_debug("kfd: vmid allocation %d\n", allocated_vmid);
qpd->vmid = allocated_vmid;
q->properties.vmid = allocated_vmid;
@@ -119,7 +119,7 @@ static void deallocate_vmid(struct device_queue_manager 
*dqm,
struct qcm_process_device *qpd,
struct queue *q)
 {
-   int bit = qpd->vmid - KFD_VMID_START_OFFSET;
+   int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
 
/* Release the vmid mapping */
set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
@@ -570,7 +570,7 @@ static int initialize_nocpsch(struct device_queue_manager 
*dqm)
for (i = 0; i < get_pipes_num(dqm); i++)
dqm->allocated_queues[i] = (1 << QUEUES_PER_PIPE) - 1;
 
-   dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1;
+   dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
 
init_scheduler(dqm);
@@ -684,8 +684,7 @@ static int set_sched_resources(struct device_queue_manager 
*dqm)
 
queue_num = get_pipes_num_cpsch() * QUEUES_PER_PIPE;
queue_mask = (1 << queue_num) - 1;
-   res.vmid_mask = (1 << VMID_PER_DEVICE) - 1;
-   res.vmid_mask <<= KFD_VMID_START_OFFSET;
+   res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
res.queue_mask = queue_mask << (get_first_pipe(dqm) * QUEUES_PER_PIPE);
res.gws_mask = res.oac_mask = res.gds_heap_base =
res.gds_heap_size = 0;
diff

Re: VRAM manager

2016-09-27 Thread Edward O'Callaghan 
This series is, to the best of my ability,
Reviewed-by: Edward O'Callaghan 

On 09/27/2016 07:49 PM, Christian König wrote:
> Hi guys,
> 
> after fixing all those nasty little bugs this seems to be stable now.
> 
> Anybody brave enough to give it an review?
> 
> Cheers,
> Christian.
> 
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> 



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Re: VRAM manager

2016-09-27 Thread Mike Lothian 
Hi Christian

It's working for me on my Tonga now, thanks for fixing those bugs

Feel free to add a testing by

Cheers

Mike

On 27 September 2016 at 10:49, Christian König  wrote:
> Hi guys,
>
> after fixing all those nasty little bugs this seems to be stable now.
>
> Anybody brave enough to give it an review?
>
> Cheers,
> Christian.
>
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Re: [PATCH 6/6] drm/amdgpu: add VRAM manager v2

2016-09-27 Thread zhoucm1 



On 2016年09月27日 17:49, Christian König wrote:

From: Christian König 

Split VRAM allocations into 4MB blocks.

v2: fix typo in comment, some suggested cleanups
v3: document how to disable the feature, fix rebase issue

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/Makefile  |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   7 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |   4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |   1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 222 +++
  7 files changed, 237 insertions(+), 2 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 786b28a..2874bfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -30,7 +30,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
-   amdgpu_gtt_mgr.o
+   amdgpu_gtt_mgr.o amdgpu_vram_mgr.o
  
  # add asic specific block

  amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 73c9a2d..2a95827 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -99,6 +99,7 @@ extern char *amdgpu_disable_cu;
  extern int amdgpu_sclk_deep_sleep_en;
  extern char *amdgpu_virtual_display;
  extern unsigned amdgpu_pp_feature_mask;
+extern int amdgpu_vram_page_split;
  
  #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	3000

  #define AMDGPU_MAX_USEC_TIMEOUT   10  /* 100 ms */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5ca6a38..d66a8df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1053,6 +1053,13 @@ static void amdgpu_check_arguments(struct amdgpu_device 
*adev)
 amdgpu_vm_block_size);
amdgpu_vm_block_size = 9;
}
+
+   if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) ||
+   !amdgpu_check_pot_argument(amdgpu_vram_page_split)) {
+   dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
+amdgpu_vram_page_split);
+   amdgpu_vram_page_split = 1024;
+   }
  }
  
  /**

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 08ba441..538d3a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -84,6 +84,7 @@ int amdgpu_vm_size = 64;
  int amdgpu_vm_block_size = -1;
  int amdgpu_vm_fault_stop = 0;
  int amdgpu_vm_debug = 0;
+int amdgpu_vram_page_split = 1024;
  int amdgpu_exp_hw_support = 0;
  int amdgpu_dal = -1;
  int amdgpu_sched_jobs = 32;
@@ -165,6 +166,9 @@ module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, 
int, 0444);
  MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = 
enabled)");
  module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
  
+MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)");

+module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
+
  MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable 
(default))");
  module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index bd377d8..588e242 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -168,7 +168,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, 
uint32_t type,
break;
case TTM_PL_VRAM:
/* "On-card" video ram */
-   man->func = _bo_manager_func;
+   man->func = _vram_mgr_func;
man->gpu_offset = adev->mc.vram_start;
man->flags = TTM_MEMTYPE_FLAG_FIXED |
 TTM_MEMTYPE_FLAG_MAPPABLE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 9812c80..d1c00c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -66,6 +66,7 @@ struct amdgpu_mman {
  };
  
  extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;

+extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
  
  int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,

VRAM manager

2016-09-27 Thread Christian König 
Hi guys,

after fixing all those nasty little bugs this seems to be stable now.

Anybody brave enough to give it an review?

Cheers,
Christian.

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[PATCH 5/6] drm/amdgpu: enable amdgpu_move_blit to handle multiple MM nodes v2

2016-09-27 Thread Christian König 
From: Christian König 

This allows us to move scattered buffers around.

v2: fix a couple of typos, handle scattered to scattered moves as well.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 118 +++-
 1 file changed, 85 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 06ab624..bd377d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -259,64 +259,116 @@ static void amdgpu_move_null(struct ttm_buffer_object 
*bo,
new_mem->mm_node = NULL;
 }
 
-static int amdgpu_move_blit(struct ttm_buffer_object *bo,
-   bool evict, bool no_wait_gpu,
-   struct ttm_mem_reg *new_mem,
-   struct ttm_mem_reg *old_mem)
+static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
+  struct drm_mm_node *mm_node,
+  struct ttm_mem_reg *mem,
+  uint64_t *addr)
 {
-   struct amdgpu_device *adev;
-   struct amdgpu_ring *ring;
-   uint64_t old_start, new_start;
-   struct fence *fence;
int r;
 
-   adev = amdgpu_get_adev(bo->bdev);
-   ring = adev->mman.buffer_funcs_ring;
-
-   switch (old_mem->mem_type) {
+   switch (mem->mem_type) {
case TTM_PL_TT:
-   r = amdgpu_ttm_bind(bo, old_mem);
+   r = amdgpu_ttm_bind(bo, mem);
if (r)
return r;
 
case TTM_PL_VRAM:
-   old_start = (u64)old_mem->start << PAGE_SHIFT;
-   old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
+   *addr = mm_node->start << PAGE_SHIFT;
+   *addr += bo->bdev->man[mem->mem_type].gpu_offset;
break;
default:
-   DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
+   DRM_ERROR("Unknown placement %d\n", mem->mem_type);
return -EINVAL;
}
-   switch (new_mem->mem_type) {
-   case TTM_PL_TT:
-   r = amdgpu_ttm_bind(bo, new_mem);
-   if (r)
-   return r;
 
-   case TTM_PL_VRAM:
-   new_start = (u64)new_mem->start << PAGE_SHIFT;
-   new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
-   break;
-   default:
-   DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
-   return -EINVAL;
-   }
+   return 0;
+}
+
+static int amdgpu_move_blit(struct ttm_buffer_object *bo,
+   bool evict, bool no_wait_gpu,
+   struct ttm_mem_reg *new_mem,
+   struct ttm_mem_reg *old_mem)
+{
+   struct amdgpu_device *adev = amdgpu_get_adev(bo->bdev);
+   struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+
+   struct drm_mm_node *old_mm, *new_mm;
+   uint64_t old_start, old_size, new_start, new_size;
+   unsigned long num_pages;
+   struct fence *fence = NULL;
+   int r;
+
+   BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
+
if (!ring->ready) {
DRM_ERROR("Trying to move memory with ring turned off.\n");
return -EINVAL;
}
 
-   BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
+   old_mm = old_mem->mm_node;
+   r = amdgpu_mm_node_addr(bo, old_mm, old_mem, _start);
+   if (r)
+   return r;
+   old_size = old_mm->size;
+
 
-   r = amdgpu_copy_buffer(ring, old_start, new_start,
-  new_mem->num_pages * PAGE_SIZE, /* bytes */
-  bo->resv, , false);
+   new_mm = new_mem->mm_node;
+   r = amdgpu_mm_node_addr(bo, new_mm, new_mem, _start);
if (r)
return r;
+   new_size = new_mm->size;
+
+   num_pages = new_mem->num_pages;
+   while (num_pages) {
+   unsigned long cur_pages = min(old_size, new_size);
+   struct fence *next;
+
+   r = amdgpu_copy_buffer(ring, old_start, new_start,
+  cur_pages * PAGE_SIZE,
+  bo->resv, , false);
+   if (r)
+   goto error;
+
+   fence_put(fence);
+   fence = next;
+
+   num_pages -= cur_pages;
+   if (!num_pages)
+   break;
+
+   old_size -= cur_pages;
+   if (!old_size) {
+   r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
+   _start);
+   if (r)
+   goto error;
+   old_size = old_mm->size;
+   } else {
+

[PATCH 3/6] drm/amdgpu: set at least the node size in the gtt manager

2016-09-27 Thread Christian König 
From: Christian König 

Otherwise the new VM code becomes confused.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index f86c844..3c634f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -168,6 +168,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager 
*man,
return -ENOMEM;
 
node->start = AMDGPU_BO_INVALID_OFFSET;
+   node->size = mem->num_pages;
mem->mm_node = node;
 
if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
-- 
2.5.0

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[PATCH 4/6] drm/amdgpu: handle multiple MM nodes in the VMs v2

2016-09-27 Thread Christian König 
From: Christian König 

This allows us to map scattered VRAM BOs to the VMs.

v2: fix offset handling, use pfn instead of offset,
fix PAGE_SIZE != AMDGPU_GPU_PAGE_SIZE case

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 81 +++---
 1 file changed, 46 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 2379eb1..6ed11cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1069,8 +1069,8 @@ error_free:
  * @pages_addr: DMA addresses to use for mapping
  * @vm: requested vm
  * @mapping: mapped range and flags to use for the update
- * @addr: addr to set the area to
  * @flags: HW flags for the mapping
+ * @nodes: array of drm_mm_nodes with the MC addresses
  * @fence: optional resulting fence
  *
  * Split the mapping into smaller chunks so that each update fits
@@ -1083,12 +1083,11 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
  dma_addr_t *pages_addr,
  struct amdgpu_vm *vm,
  struct amdgpu_bo_va_mapping *mapping,
- uint32_t flags, uint64_t addr,
+ uint32_t flags,
+ struct drm_mm_node *nodes,
  struct fence **fence)
 {
-   const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / 
AMDGPU_GPU_PAGE_SIZE;
-
-   uint64_t src = 0, start = mapping->it.start;
+   uint64_t pfn, src = 0, start = mapping->it.start;
int r;
 
/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go 
here
@@ -1101,23 +1100,40 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
 
trace_amdgpu_vm_bo_update(mapping);
 
-   if (pages_addr) {
-   if (flags == gtt_flags)
-   src = adev->gart.table_addr + (addr >> 12) * 8;
-   addr = 0;
+   pfn = mapping->offset >> PAGE_SHIFT;
+   if (nodes) {
+   while (pfn >= nodes->size) {
+   pfn -= nodes->size;
+   ++nodes;
+   }
}
-   addr += mapping->offset;
 
-   if (!pages_addr || src)
-   return amdgpu_vm_bo_update_mapping(adev, exclusive,
-  src, pages_addr, vm,
-  start, mapping->it.last,
-  flags, addr, fence);
+   do {
+   uint64_t max_entries;
+   uint64_t addr, last;
 
-   while (start != mapping->it.last + 1) {
-   uint64_t last;
+   if (nodes) {
+   addr = nodes->start << PAGE_SHIFT;
+   max_entries = (nodes->size - pfn) *
+   (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
+   } else {
+   addr = 0;
+   max_entries = S64_MAX;
+   }
 
-   last = min((uint64_t)mapping->it.last, start + max_size - 1);
+   if (pages_addr) {
+   if (flags == gtt_flags)
+   src = adev->gart.table_addr +
+   (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
+   else
+   max_entries = min(max_entries, 16ull * 1024ull);
+   addr = 0;
+   } else if (flags & AMDGPU_PTE_VALID) {
+   addr += adev->vm_manager.vram_base_offset;
+   }
+   addr += pfn << PAGE_SHIFT;
+
+   last = min((uint64_t)mapping->it.last, start + max_entries - 1);
r = amdgpu_vm_bo_update_mapping(adev, exclusive,
src, pages_addr, vm,
start, last, flags, addr,
@@ -1125,9 +1141,14 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
if (r)
return r;
 
+   pfn += last - start + 1;
+   if (nodes && nodes->size == pfn) {
+   pfn = 0;
+   ++nodes;
+   }
start = last + 1;
-   addr += max_size * AMDGPU_GPU_PAGE_SIZE;
-   }
+
+   } while (unlikely(start != mapping->it.last + 1));
 
return 0;
 }
@@ -1151,34 +1172,24 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
dma_addr_t *pages_addr = NULL;
uint32_t gtt_flags, flags;
struct ttm_mem_reg *mem;
+   struct drm_mm_node *nodes;
struct fence *exclusive;
-   uint64_t addr;
int r;
 
if (clear) {
mem =

[PATCH 1/6] drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag v3

2016-09-27 Thread Christian König 
From: Christian König 

Add a flag noting that a BO must be created using linear VRAM
and set this flag on all in kernel users where appropriate.

Hopefully I haven't missed anything.

v2: add it in a few more places, fix CPU mapping.
v3: rename to VRAM_CONTIGUOUS, fix typo in CS code.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c|  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  9 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  6 --
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |  9 ++---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  6 --
 include/uapi/drm/amdgpu_drm.h  |  2 ++
 13 files changed, 53 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 7a8bfa3..a61f418 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -146,7 +146,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device 
*cgs_device,
switch(type) {
case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
case CGS_GPU_MEM_TYPE__VISIBLE_FB:
-   flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
if (max_offset > adev->mc.real_vram_size)
return -EINVAL;
@@ -157,7 +158,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device 
*cgs_device,
break;
case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
-   flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+   flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
place.fpfn =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b0f6e69..187c366 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1195,6 +1195,15 @@ int amdgpu_cs_sysvm_access_required(struct 
amdgpu_cs_parser *parser)
r = amdgpu_ttm_bind(>tbo, >tbo.mem);
if (unlikely(r))
return r;
+
+   if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
+   continue;
+
+   bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+   amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
+   r = ttm_bo_validate(>tbo, >placement, false, false);
+   if (unlikely(r))
+   return r;
}
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c626434..5ca6a38 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -265,7 +265,8 @@ static int amdgpu_vram_scratch_init(struct amdgpu_device 
*adev)
if (adev->vram_scratch.robj == NULL) {
r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
-AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 NULL, NULL, >vram_scratch.robj);
if (r) {
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 034e945..f491092 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -148,7 +148,8 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
aligned_size = ALIGN(size, PAGE_SIZE);
ret = amdgpu_gem_object_create(adev, aligned_size, 0,
   AMDGPU_GEM_DOMAIN_VRAM,
-  AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+  AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
   true, );
if (ret) {
printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
diff

[PATCH 2/6] drm/amdgpu: use explicit limit for VRAM_CONTIGUOUS

2016-09-27 Thread Christian König 
From: Christian König 

Split VRAM won't have a valid offset, so just set an explicit limit
when the flag is given to trigger reallocation if necessary.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index ba41807..c6754e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -121,12 +121,17 @@ static void amdgpu_ttm_placement_init(struct 
amdgpu_device *adev,
 
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
+   unsigned lpfn = 0;
+
+   /* This forces a reallocation if the flag wasn't set before */
+   if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
+   lpfn = adev->mc.real_vram_size >> PAGE_SHIFT;
 
if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
adev->mc.visible_vram_size < adev->mc.real_vram_size) {
places[c].fpfn = visible_pfn;
-   places[c].lpfn = 0;
+   places[c].lpfn = lpfn;
places[c].flags = TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM |
TTM_PL_FLAG_TOPDOWN;
@@ -134,7 +139,7 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device 
*adev,
}
 
places[c].fpfn = 0;
-   places[c].lpfn = 0;
+   places[c].lpfn = lpfn;
places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
TTM_PL_FLAG_VRAM;
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
-- 
2.5.0

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Re: [PATCH] drm/amdgpu: add version bump for raster config programming

2016-09-27 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Mon, Sep 26, 2016 at 10:46 PM, Alex Deucher  wrote:
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 2be20b4..28c6ea8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -57,9 +57,10 @@
>   * - 3.5.0 - Add support for new UVD_NO_OP register.
>   * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
>   * - 3.7.0 - Add support for VCE clock list packet
> + * - 3.8.0 - Add support raster config init in the kernel
>   */
>  #define KMS_DRIVER_MAJOR   3
> -#define KMS_DRIVER_MINOR   7
> +#define KMS_DRIVER_MINOR   8
>  #define KMS_DRIVER_PATCHLEVEL  0
>
>  int amdgpu_vram_limit = 0;
> --
> 2.5.5
>
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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

2016-09-27 Thread Christian König 

Am 27.09.2016 um 01:13 schrieb Marek Olšák:

On Mon, Sep 26, 2016 at 10:42 PM, Deucher, Alexander
 wrote:

-Original Message-
From: Marek Olšák [mailto:mar...@gmail.com]
Sent: Monday, September 26, 2016 4:39 PM
To: Huang, Ray
Cc: amd-gfx mailing list; Deucher, Alexander; Wang, Ken; Huan, Alvin
Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

The series is missing a DRM version bump, so Mesa can't really use it
even if it wanted.


We bumped it already this cycle for several other things, but I can add a 
specific bump for this as well if that is preferred.

Oh, that's not necessary. One bump per cycle is OK.


As I wrote in the other thread as well, bumping once per cycle sucks 
when you want to bisect something.


We are also not short on numbers, so I suggest that we establish that we 
always bump when we add a new interface to the kernel IOCTL.


Christian.



Marek
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Re: [PATCH] drm/amdgpu: add version bump for raster config programming

2016-09-27 Thread Christian König 

Am 26.09.2016 um 22:46 schrieb Alex Deucher:

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König .

BTW: I've never been a fan of bumping only once per cycle. We are not 
short on numbers and it really sucks to bump only once when you want to 
bisect something.


Regards,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 2be20b4..28c6ea8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -57,9 +57,10 @@
   * - 3.5.0 - Add support for new UVD_NO_OP register.
   * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
   * - 3.7.0 - Add support for VCE clock list packet
+ * - 3.8.0 - Add support raster config init in the kernel
   */
  #define KMS_DRIVER_MAJOR  3
-#define KMS_DRIVER_MINOR   7
+#define KMS_DRIVER_MINOR   8
  #define KMS_DRIVER_PATCHLEVEL 0
  
  int amdgpu_vram_limit = 0;



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Re: [PATCH] drm/amdgpu/vce: take all rings into account for idle checks

2016-09-27 Thread Christian König 

Am 26.09.2016 um 21:21 schrieb Alex Deucher:

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 121bd6e..3b03558 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -305,9 +305,12 @@ static void amdgpu_vce_idle_work_handler(struct 
work_struct *work)
  {
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, vce.idle_work.work);
+   unsigned i, count = 0;
  
-	if ((amdgpu_fence_count_emitted(>vce.ring[0]) == 0) &&

-   (amdgpu_fence_count_emitted(>vce.ring[1]) == 0)) {
+   for (i = 0; i < adev->vce.num_rings; i++)
+   count += amdgpu_fence_count_emitted(>vce.ring[i]);
+
+   if (count == 0) {
if (adev->pm.dpm_enabled) {
amdgpu_dpm_enable_vce(adev, false);
} else {



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