答复: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox

2017-01-24 Thread Liu, Monk 
please ignore those patches and we will give a formal patch serial later when 
confirm good working


BR Monk


?件人: amd-gfx  代表 Felix Kuehling 

?送??: 2017年1月25日 3:04:48
收件人: amd-gfx@lists.freedesktop.org
主?: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and server by 
mailbox

On 17-01-24 10:05 AM, Xue, Ken wrote:
>> From: Christian Konig [mailto:deathsim...@vodafone.de]
>> Sent: Tuesday, January 24, 2017 10:09 PM
>> To: Xue, Ken; amd-gfx mailing list
>> Cc: dl.SRDC_SW_GPUVirtualization
>> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and
>> server by mailbox
>>
>> Am 24.01.2017 um 13:55 schrieb Xue, Ken:
>>> Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
>>> message and after ACK server.
>>>
>>> Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
>>> Signed-off-by: Ken Xue 
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 
>>>   1 file changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> index d2622b6..b2c46db 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
>> amdgpu_device *adev)
>>>   static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
>>>   {
>>>  u32 reg;
>>> +   int timeout = VI_MAILBOX_TIMEDOUT;
>>> +   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
>>>
>>>  reg = RREG32(mmMAILBOX_CONTROL);
>>>  reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
>>>  WREG32(mmMAILBOX_CONTROL, reg);
>>> +
>>> +   /*Wait for RCV_MSG_VALID to be 0*/
>>> +   reg = RREG32(mmMAILBOX_CONTROL);
>>> +   while (reg & mask) {
>>> +   if (timeout <= 0) {
>>> +   pr_err("RCV_MSG_VALID is not cleared\n");
>>> +   break;
>>> +   }
>>> +   msleep(1);
>> Are you sure that you want to use msleep() here instead of mdelay() ?
>>
>> msleep() is horrible inaccurate, e.g. depending on the definition of HZ you 
>> can
>> sleep for 10ms instead of 1ms IIRC.
>>
>> mdelay() is a busy wait, so the CPU can't do anything else useful while 
>> waiting
>> but I don't think that this will hurt us here.
> Thanks for your suggestion.
> Currently, msleep may be a correct choice.
> 1)accuracy is not necessary here
> 2)the VI_MAILBOX_TIMEDOUT is 5000. if there is an issue from server side, 
> driver may be delayed 5 seconds
> 3)I followed the same style like other codes in the same file.

If msleep sleeps for 10ms instead of 1ms, then your loop may end up
waiting for 50s instead of 5s.

If you want the total timeout to be more predictable, it may be better
to compare jiffies rather than count loop iterations.

Regards,
  Felix

>
>
> Regards,
> Ken
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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[PATCH] drm/radeon: drop pitcairn dpm quirks

2017-01-24 Thread Alex Deucher 
No longer necessary with the new 58 mc ucode.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=76490

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/si_dpm.c | 47 +
 1 file changed, 1 insertion(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 2944916..d12b897 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2912,29 +2912,6 @@ static int si_init_smc_spll_table(struct radeon_device 
*rdev)
return ret;
 }
 
-struct si_dpm_quirk {
-   u32 chip_vendor;
-   u32 chip_device;
-   u32 subsys_vendor;
-   u32 subsys_device;
-   u32 max_sclk;
-   u32 max_mclk;
-};
-
-/* cards with dpm stability problems */
-static struct si_dpm_quirk si_dpm_quirk_list[] = {
-   /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 9 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 12 },
-   { 0, 0, 0, 0 },
-};
-
 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
   u16 vce_voltage)
 {
@@ -2997,18 +2974,8 @@ static void si_apply_state_adjust_rules(struct 
radeon_device *rdev,
u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
u32 max_sclk = 0, max_mclk = 0;
int i;
-   struct si_dpm_quirk *p = si_dpm_quirk_list;
 
-   /* limit all SI kickers */
-   if (rdev->family == CHIP_PITCAIRN) {
-   if ((rdev->pdev->revision == 0x81) ||
-   (rdev->pdev->device == 0x6810) ||
-   (rdev->pdev->device == 0x6811) ||
-   (rdev->pdev->device == 0x6816) ||
-   (rdev->pdev->device == 0x6817) ||
-   (rdev->pdev->device == 0x6806))
-   max_mclk = 12;
-   } else if (rdev->family == CHIP_HAINAN) {
+   if (rdev->family == CHIP_HAINAN) {
if ((rdev->pdev->revision == 0x81) ||
(rdev->pdev->revision == 0x83) ||
(rdev->pdev->revision == 0xC3) ||
@@ -3018,18 +2985,6 @@ static void si_apply_state_adjust_rules(struct 
radeon_device *rdev,
max_sclk = 75000;
}
}
-   /* Apply dpm quirks */
-   while (p && p->chip_device != 0) {
-   if (rdev->pdev->vendor == p->chip_vendor &&
-   rdev->pdev->device == p->chip_device &&
-   rdev->pdev->subsystem_vendor == p->subsys_vendor &&
-   rdev->pdev->subsystem_device == p->subsys_device) {
-   max_sclk = p->max_sclk;
-   max_mclk = p->max_mclk;
-   break;
-   }
-   ++p;
-   }
 
if (rps->vce_active) {
rps->evclk = 
rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
-- 
2.5.5

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[PATCH] drm/amdgpu: drop pitcairn dpm quirks

2017-01-24 Thread Alex Deucher 
No longer necessary with the new 58 mc ucode.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 47 +
 1 file changed, 1 insertion(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 4f12da1..ab2dd59 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3009,29 +3009,6 @@ static int si_init_smc_spll_table(struct amdgpu_device 
*adev)
return ret;
 }
 
-struct si_dpm_quirk {
-   u32 chip_vendor;
-   u32 chip_device;
-   u32 subsys_vendor;
-   u32 subsys_device;
-   u32 max_sclk;
-   u32 max_mclk;
-};
-
-/* cards with dpm stability problems */
-static struct si_dpm_quirk si_dpm_quirk_list[] = {
-   /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 9 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 12 },
-   { 0, 0, 0, 0 },
-};
-
 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
   u16 vce_voltage)
 {
@@ -3477,18 +3454,8 @@ static void si_apply_state_adjust_rules(struct 
amdgpu_device *adev,
u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
u32 max_sclk = 0, max_mclk = 0;
int i;
-   struct si_dpm_quirk *p = si_dpm_quirk_list;
 
-   /* limit all SI kickers */
-   if (adev->asic_type == CHIP_PITCAIRN) {
-   if ((adev->pdev->revision == 0x81) ||
-   (adev->pdev->device == 0x6810) ||
-   (adev->pdev->device == 0x6811) ||
-   (adev->pdev->device == 0x6816) ||
-   (adev->pdev->device == 0x6817) ||
-   (adev->pdev->device == 0x6806))
-   max_mclk = 12;
-   } else if (adev->asic_type == CHIP_HAINAN) {
+   if (adev->asic_type == CHIP_HAINAN) {
if ((adev->pdev->revision == 0x81) ||
(adev->pdev->revision == 0x83) ||
(adev->pdev->revision == 0xC3) ||
@@ -3498,18 +3465,6 @@ static void si_apply_state_adjust_rules(struct 
amdgpu_device *adev,
max_sclk = 75000;
}
}
-   /* Apply dpm quirks */
-   while (p && p->chip_device != 0) {
-   if (adev->pdev->vendor == p->chip_vendor &&
-   adev->pdev->device == p->chip_device &&
-   adev->pdev->subsystem_vendor == p->subsys_vendor &&
-   adev->pdev->subsystem_device == p->subsys_device) {
-   max_sclk = p->max_sclk;
-   max_mclk = p->max_mclk;
-   break;
-   }
-   ++p;
-   }
 
if (rps->vce_active) {
rps->evclk = 
adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
-- 
2.5.5

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[PATCH 1/2] drm/amdgpu: remove unused header si_reg.h

2017-01-24 Thread Alex Deucher 
All of these are available elsewhere.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h | 105 ---
 1 file changed, 105 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h 
b/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h
deleted file mode 100644
index 895c8e2..000
--- a/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-#ifndef __SI_REG_H__
-#define __SI_REG_H__
-
-/* SI */
-#define SI_DC_GPIO_HPD_MASK  0x196c
-#define SI_DC_GPIO_HPD_A 0x196d
-#define SI_DC_GPIO_HPD_EN0x196e
-#define SI_DC_GPIO_HPD_Y 0x196f
-
-#define SI_GRPH_CONTROL  0x1a01
-#   define SI_GRPH_DEPTH(x)  (((x) & 0x3) << 0)
-#   define SI_GRPH_DEPTH_8BPP0
-#   define SI_GRPH_DEPTH_16BPP   1
-#   define SI_GRPH_DEPTH_32BPP   2
-#   define SI_GRPH_NUM_BANKS(x)  (((x) & 0x3) << 2)
-#   define SI_ADDR_SURF_2_BANK   0
-#   define SI_ADDR_SURF_4_BANK   1
-#   define SI_ADDR_SURF_8_BANK   2
-#   define SI_ADDR_SURF_16_BANK  3
-#   define SI_GRPH_Z(x)  (((x) & 0x3) << 4)
-#   define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
-#   define SI_ADDR_SURF_BANK_WIDTH_1 0
-#   define SI_ADDR_SURF_BANK_WIDTH_2 1
-#   define SI_ADDR_SURF_BANK_WIDTH_4 2
-#   define SI_ADDR_SURF_BANK_WIDTH_8 3
-#   define SI_GRPH_FORMAT(x) (((x) & 0x7) << 8)
-/* 8 BPP */
-#   define SI_GRPH_FORMAT_INDEXED0
-/* 16 BPP */
-#   define SI_GRPH_FORMAT_ARGB1555   0
-#   define SI_GRPH_FORMAT_ARGB5651
-#   define SI_GRPH_FORMAT_ARGB   2
-#   define SI_GRPH_FORMAT_AI88   3
-#   define SI_GRPH_FORMAT_MONO16 4
-#   define SI_GRPH_FORMAT_BGRA5551   5
-/* 32 BPP */
-#   define SI_GRPH_FORMAT_ARGB   0
-#   define SI_GRPH_FORMAT_ARGB21010101
-#   define SI_GRPH_FORMAT_32BPP_DIG  2
-#   define SI_GRPH_FORMAT_8B_ARGB2101010 3
-#   define SI_GRPH_FORMAT_BGRA10101024
-#   define SI_GRPH_FORMAT_8B_BGRA1010102 5
-#   define SI_GRPH_FORMAT_RGB10  6
-#   define SI_GRPH_FORMAT_BGR10  7
-#   define SI_GRPH_BANK_HEIGHT(x)(((x) & 0x3) << 11)
-#   define SI_ADDR_SURF_BANK_HEIGHT_10
-#   define SI_ADDR_SURF_BANK_HEIGHT_21
-#   define SI_ADDR_SURF_BANK_HEIGHT_42
-#   define SI_ADDR_SURF_BANK_HEIGHT_83
-#   define SI_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
-#   define SI_ADDR_SURF_TILE_SPLIT_64B   0
-#   define SI_ADDR_SURF_TILE_SPLIT_128B  1
-#   define SI_ADDR_SURF_TILE_SPLIT_256B  2
-#   define SI_ADDR_SURF_TILE_SPLIT_512B  3
-#   define SI_ADDR_SURF_TILE_SPLIT_1KB   4
-#   define SI_ADDR_SURF_TILE_SPLIT_2KB   5
-#   define SI_ADDR_SURF_TILE_SPLIT_4KB   6
-#   define SI_GRPH_MACRO_TILE_ASPECT(x)  (((x) & 0x3) << 18)
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_1  0
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_2  1
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_4  2
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_8  3
-#   define SI_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
-#   define SI_GRPH_ARRAY_LINEAR_GENERAL  0
-#   define SI_GRPH_ARRAY_LINEAR_ALIGNED  1
-#   define

RE: [PATCH libdrm 3/3] amdgpu: A new option to run tests on render node

2017-01-24 Thread Xie, AlexBin 
Hi Emil,

Point 1 will be left for future patch.

Current error message is following.
Error: Permission denied. Hint:Try to run this test program as root.

I am thinking change it. Error message will be:
Error: Permission denied. Hint:Try to run this test program as root or in TTY.

Thanks,
Alex Bin Xie

-Original Message-
From: Emil Velikov [mailto:emil.l.veli...@gmail.com] 
Sent: Friday, January 20, 2017 8:31 AM
To: Xie, AlexBin 
Cc: amd-gfx mailing list 
Subject: Re: [PATCH libdrm 3/3] amdgpu: A new option to run tests on render node

HI Alex,

A couple of small idea(s) for future work (?).

On 19 January 2017 at 22:53, Alex Xie  wrote:
> Tested:
> 1. As root, tests passed on primary.
Add auth mechanism and request run outside of X environment (switching
to TTY should work).
Then adjust the suggestion s/run as root/run in TTY/ ?

> 2. As root, BO export/import failed on render node as expected.
Afaict those can never succeed, so might as well change the test to
expect failure [when using the render node], or at least print a
message "the following failure is expected" ?

Thanks the series !
Emil
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[PATCH libdrm 3/3] amdgpu: A new option to run tests on render node

2017-01-24 Thread Alex Xie 
Tested:
1. As root, tests passed on primary.
2. As root, tests passed on render node.
   BO export/import test was skipped
3. As non-privileged user, tests failed on primary as expected.
4. As non-privileged user, tests passed on render node.
   BO export/import test was skipped

Signed-off-by: Alex Xie 
---
 tests/amdgpu/amdgpu_test.c | 13 ++---
 tests/amdgpu/amdgpu_test.h |  3 +++
 tests/amdgpu/bo_tests.c|  5 +
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index c01ee54..3fd6820 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -56,6 +56,9 @@
  */
 int drm_amdgpu[MAX_CARDS_SUPPORTED];
 
+/** Open render node to test */
+int open_render_node = 0;  /* By default run most tests on primary node */
+
 /** The table of all known test suites to run */
 static CU_SuiteInfo suites[] = {
{
@@ -109,16 +112,17 @@ static void display_test_suites(void)
 
 /** Help string for command line parameters */
 static const char usage[] =
-   "Usage: %s [-hlp] [<-s > [-t ]] "
+   "Usage: %s [-hlpr] [<-s > [-t ]] "
"[-b  [-d ]]\n"
"where:\n"
"   l - Display all suites and their tests\n"
+   "   r - Run the tests on render node\n"
"   b - Specify device's PCI bus id to run tests\n"
"   d - Specify device's PCI device id to run tests (optional)\n"
"   p - Display information of AMDGPU devices in system\n"
"   h - Display this help\n";
 /** Specified options strings for getopt */
-static const char options[]   = "hlps:t:b:d:";
+static const char options[]   = "hlrps:t:b:d:";
 
 /* Open AMD devices.
  * Return the number of AMD device openned.
@@ -326,6 +330,9 @@ int main(int argc, char **argv)
case 'p':
display_devices = 1;
break;
+   case 'r':
+   open_render_node = 1;
+   break;
case '?':
case 'h':
fprintf(stderr, usage, argv[0]);
@@ -336,7 +343,7 @@ int main(int argc, char **argv)
}
}
 
-   if (amdgpu_open_devices(0) <= 0) {
+   if (amdgpu_open_devices(open_render_node) <= 0) {
perror("Cannot open AMDGPU device");
exit(EXIT_FAILURE);
}
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index fca92ad..e30e231 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -35,6 +35,9 @@
 /* Forward reference for array to keep "drm" handles */
 extern int drm_amdgpu[MAX_CARDS_SUPPORTED];
 
+/* Global variables */
+extern int open_render_node;
+
 /*  Basic test suite /
 
 /*
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 25df767..74b5e77 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -152,6 +152,11 @@ static void amdgpu_bo_export_import_do_type(enum 
amdgpu_bo_handle_type type)
 
 static void amdgpu_bo_export_import(void)
 {
+   if (open_render_node) {
+   printf("(DRM render node is used. Skip export/Import test) ");
+   return;
+   }
+
amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_gem_flink_name);
amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_dma_buf_fd);
 }
-- 
2.7.4

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[PATCH libdrm 2/3] amdgpu: A new option to choose which device to run most tests

2017-01-24 Thread Alex Xie 
This can be used to test multiple GPUs

v2: Use PCI bus ID and optional PCI device ID to choose device
Add an option to display information of AMDGPU devices

Tested:
   ./amdgpu_test -p
   ./amdgpu_test
   ./amdgpu_test -b 1 #fail as expected
   ./amdgpu_test -b 6 #pass
   ./amdgpu_test -b -d 1 #fail as expected
   ./amdgpu_test -b -d 0 #pass

Signed-off-by: Alex Xie 
---
 tests/amdgpu/amdgpu_test.c | 133 +++--
 1 file changed, 116 insertions(+), 17 deletions(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index d2b00d4..c01ee54 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -108,12 +108,17 @@ static void display_test_suites(void)
 
 
 /** Help string for command line parameters */
-static const char usage[] = "Usage: %s [-hl] [<-s > [-t ]]\n"
-   "where:\n"
-   "   l - Display all suites and their 
tests\n"
-   "   h - Display this help\n";
+static const char usage[] =
+   "Usage: %s [-hlp] [<-s > [-t ]] "
+   "[-b  [-d ]]\n"
+   "where:\n"
+   "   l - Display all suites and their tests\n"
+   "   b - Specify device's PCI bus id to run tests\n"
+   "   d - Specify device's PCI device id to run tests (optional)\n"
+   "   p - Display information of AMDGPU devices in system\n"
+   "   h - Display this help\n";
 /** Specified options strings for getopt */
-static const char options[]   = "hls:t:";
+static const char options[]   = "hlps:t:b:d:";
 
 /* Open AMD devices.
  * Return the number of AMD device openned.
@@ -203,21 +208,79 @@ static void amdgpu_close_devices()
 static void amdgpu_print_devices()
 {
int i;
-   for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
-   if (drm_amdgpu[i] >=0) {
-   /** Display version of DRM driver */
-   drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]);
+   drmDevicePtr device;
+
+   /* Open the first AMD devcie to print driver information. */
+   if (drm_amdgpu[0] >=0) {
+   /* Display AMD driver version information.*/
+   drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]);
+
+   if (retval == NULL) {
+   perror("Cannot get version for AMDGPU device");
+   return;
+   }
 
-   if (retval == NULL) {
-   perror("Cannot get version for AMDGPU device");
-   exit(EXIT_FAILURE);
+   printf("Driver name: %s, Date: %s, Description: %s.\n",
+   retval->name, retval->date, retval->desc);
+   drmFreeVersion(retval);
+   }
+
+   /* Display information of AMD devices */
+   printf("Devices:\n");
+   for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++)
+   if (drmGetDevice2(drm_amdgpu[i],
+   DRM_DEVICE_GET_PCI_REVISION,
+   ) == 0) {
+   if (device->bustype == DRM_BUS_PCI) {
+   printf("PCI ");
+   printf(" domain:%04x",
+   device->businfo.pci->domain);
+   printf(" bus:%02x",
+   device->businfo.pci->bus);
+   printf(" device:%02x",
+   device->businfo.pci->dev);
+   printf(" function:%01x",
+   device->businfo.pci->func);
+   printf(" vendor_id:%04x",
+   device->deviceinfo.pci->vendor_id);
+   printf(" device_id:%04x",
+   device->deviceinfo.pci->device_id);
+   printf(" subvendor_id:%04x",
+   device->deviceinfo.pci->subvendor_id);
+   printf(" subdevice_id:%04x",
+   device->deviceinfo.pci->subdevice_id);
+   printf(" revision_id:%02x",
+   device->deviceinfo.pci->revision_id);
+   printf("\n");
}
+   drmFreeDevice();
+   }
+}
+
+/* Find a match AMD device in PCI bus
+ * Return the index of the device or -1 if not found
+ */
+static int amdgpu_find_device(uint8_t bus, uint8_t dev)
+{
+   int i;
+   drmDevicePtr device;
+
+   for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++)
+   if (drmGetDevice2(drm_amdgpu[i],
+   DRM_DEVICE_GET_PCI_REVISION,
+   ) == 0) {
+   if (device->bustype

[PATCH libdrm 1/3] amdgpu: verify the tested device

2017-01-24 Thread Alex Xie 
Verify the vender ID and driver name.
Open all AMDGPU devices.
Provide an option to open render node.

Tested as root: PASS
Tested as non-privileged user:
All tests failed as expected

v2: Return value in the ene of function amdgpu_open_devices.
Check the return value of amdgpu_open_devices.
amdgpu_test is not for USB device for the time being.
Get the name of node from function drmGetDevices2.
Drop the legacy drmAvailable() from the test.

Signed-off-by: Alex Xie 
---
 tests/amdgpu/amdgpu_test.c | 145 +++--
 1 file changed, 115 insertions(+), 30 deletions(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 71f357c..d2b00d4 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -115,6 +115,111 @@ static const char usage[] = "Usage: %s [-hl] [<-s > [-t ]]\n"
 /** Specified options strings for getopt */
 static const char options[]   = "hls:t:";
 
+/* Open AMD devices.
+ * Return the number of AMD device openned.
+ */
+static int amdgpu_open_devices(int open_render_node)
+{
+   drmDevicePtr devices[MAX_CARDS_SUPPORTED];
+   int ret;
+   int i;
+   int drm_node;
+   int amd_index = 0;
+   int drm_count;
+   int fd;
+   drmVersionPtr version;
+
+   drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
+
+   if (drm_count < 0) {
+   fprintf(stderr,
+   "drmGetDevices2() returned an error %d\n",
+   drm_count);
+   return 0;
+   }
+
+   for (i = 0; i < drm_count; i++) {
+   /* If this is not PCI device, skip*/
+   if (devices[i]->bustype != DRM_BUS_PCI)
+   continue;
+
+   /* If this is not AMD GPU vender ID, skip*/
+   if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
+   continue;
+
+   if (open_render_node)
+   drm_node = DRM_NODE_RENDER;
+   else
+   drm_node = DRM_NODE_PRIMARY;
+
+   fd = -1;
+   if (devices[i]->available_nodes & 1 << drm_node)
+   fd = open(
+   devices[i]->nodes[drm_node],
+   O_RDWR | O_CLOEXEC);
+
+   /* This node is not available. */
+   if (fd < 0) continue;
+
+   version = drmGetVersion(fd);
+   if (!version) {
+   fprintf(stderr,
+   "Warning: Cannot get version for %s."
+   "Error is %s\n",
+   devices[i]->nodes[drm_node],
+   strerror(errno));
+   close(fd);
+   continue;
+   }
+
+   if (strcmp(version->name, "amdgpu")) {
+   /* This is not AMDGPU driver, skip.*/
+   drmFreeVersion(version);
+   close(fd);
+   continue;
+   }
+
+   drmFreeVersion(version);
+
+   drm_amdgpu[amd_index] = fd;
+   amd_index++;
+   }
+
+   drmFreeDevices(devices, drm_count);
+   return amd_index;
+}
+
+/* Close AMD devices.
+ */
+static void amdgpu_close_devices()
+{
+   int i;
+   for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
+   if (drm_amdgpu[i] >=0)
+   close(drm_amdgpu[i]);
+}
+
+/* Print AMD devices information */
+static void amdgpu_print_devices()
+{
+   int i;
+   for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
+   if (drm_amdgpu[i] >=0) {
+   /** Display version of DRM driver */
+   drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]);
+
+   if (retval == NULL) {
+   perror("Cannot get version for AMDGPU device");
+   exit(EXIT_FAILURE);
+   }
+
+   printf("AMDGPU device #%d: "
+   "Name: [%s] : Date [%s] : Description [%s]\n",
+   i, retval->name, retval->date, retval->desc);
+   drmFreeVersion(retval);
+   }
+}
+
 /* The main() function for setting up and running the tests.
  * Returns a CUE_SUCCESS on successful running, another
  * CUnit error code on failure.
@@ -128,14 +233,6 @@ int main(int argc, char **argv)
CU_pSuite pSuite = NULL;
CU_pTest  pTest  = NULL;
 
-   int aval = drmAvailable();
-
-   if (aval == 0) {
-   fprintf(stderr, "DRM driver is not available\n");
-   exit(EXIT_FAILURE);
-   }
-
-
for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
drm_amdgpu[i] = -1;
 
@@ -163,35 +260,23 @@ int main(int argc, char **argv)
}
}
 
-   /*

Re: [PATCH 6/6] drm/ttm: revert "add optional LRU removal callback v2"

2017-01-24 Thread Sinclair Yeh 
Pathces 1, 2, 5, 6:
Reviewed-by: Sinclair Yeh 

On Fri, Jan 13, 2017 at 10:51:11AM +0100, Christian König wrote:
> From: Christian König 
> 
> Without the custom LRU management the callback is not used any more.
> 
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/ttm/ttm_bo.c| 12 +---
>  include/drm/ttm/ttm_bo_driver.h |  6 --
>  2 files changed, 5 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> index 59fac2f..dfaeac4 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -186,12 +186,8 @@ EXPORT_SYMBOL(ttm_bo_add_to_lru);
>  
>  int ttm_bo_del_from_lru(struct ttm_buffer_object *bo)
>  {
> - struct ttm_bo_device *bdev = bo->bdev;
>   int put_count = 0;
>  
> - if (bdev->driver->lru_removal)
> - bdev->driver->lru_removal(bo);
> -
>   if (!list_empty(>swap)) {
>   list_del_init(>swap);
>   ++put_count;
> @@ -201,6 +197,11 @@ int ttm_bo_del_from_lru(struct ttm_buffer_object *bo)
>   ++put_count;
>   }
>  
> + /*
> +  * TODO: Add a driver hook to delete from
> +  * driver-specific LRU's here.
> +  */
> +
>   return put_count;
>  }
>  
> @@ -234,9 +235,6 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo)
>  
>   lockdep_assert_held(>resv->lock.base);
>  
> - if (bdev->driver->lru_removal)
> - bdev->driver->lru_removal(bo);
> -
>   put_count = ttm_bo_del_from_lru(bo);
>   ttm_bo_list_ref_sub(bo, put_count, true);
>   ttm_bo_add_to_lru(bo);
> diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
> index a1235fa..4395db1 100644
> --- a/include/drm/ttm/ttm_bo_driver.h
> +++ b/include/drm/ttm/ttm_bo_driver.h
> @@ -462,12 +462,6 @@ struct ttm_bo_driver {
> struct ttm_mem_reg *mem);
>   void (*io_mem_free)(struct ttm_bo_device *bdev,
>   struct ttm_mem_reg *mem);
> -
> - /**
> -  * Optional driver callback for when BO is removed from the LRU.
> -  * Called with LRU lock held immediately before the removal.
> -  */
> - void (*lru_removal)(struct ttm_buffer_object *bo);
>  };
>  
>  /**
> -- 
> 2.7.4
> 
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox

2017-01-24 Thread Felix Kuehling 
On 17-01-24 10:05 AM, Xue, Ken wrote:
>> From: Christian König [mailto:deathsim...@vodafone.de]
>> Sent: Tuesday, January 24, 2017 10:09 PM
>> To: Xue, Ken; amd-gfx mailing list
>> Cc: dl.SRDC_SW_GPUVirtualization
>> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and
>> server by mailbox
>>
>> Am 24.01.2017 um 13:55 schrieb Xue, Ken:
>>> Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
>>> message and after ACK server.
>>>
>>> Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
>>> Signed-off-by: Ken Xue 
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 
>>>   1 file changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> index d2622b6..b2c46db 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
>> amdgpu_device *adev)
>>>   static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
>>>   {
>>> u32 reg;
>>> +   int timeout = VI_MAILBOX_TIMEDOUT;
>>> +   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
>>>
>>> reg = RREG32(mmMAILBOX_CONTROL);
>>> reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
>>> WREG32(mmMAILBOX_CONTROL, reg);
>>> +
>>> +   /*Wait for RCV_MSG_VALID to be 0*/
>>> +   reg = RREG32(mmMAILBOX_CONTROL);
>>> +   while (reg & mask) {
>>> +   if (timeout <= 0) {
>>> +   pr_err("RCV_MSG_VALID is not cleared\n");
>>> +   break;
>>> +   }
>>> +   msleep(1);
>> Are you sure that you want to use msleep() here instead of mdelay() ?
>>
>> msleep() is horrible inaccurate, e.g. depending on the definition of HZ you 
>> can
>> sleep for 10ms instead of 1ms IIRC.
>>
>> mdelay() is a busy wait, so the CPU can't do anything else useful while 
>> waiting
>> but I don't think that this will hurt us here.
> Thanks for your suggestion.
> Currently, msleep may be a correct choice.
> 1)accuracy is not necessary here
> 2)the VI_MAILBOX_TIMEDOUT is 5000. if there is an issue from server side, 
> driver may be delayed 5 seconds
> 3)I followed the same style like other codes in the same file.

If msleep sleeps for 10ms instead of 1ms, then your loop may end up
waiting for 50s instead of 5s.

If you want the total timeout to be more predictable, it may be better
to compare jiffies rather than count loop iterations.

Regards,
  Felix

>
>
> Regards,
> Ken
> ___
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Re: [PATCH 5/6] drm/ttm: revert "implement LRU add callbacks v2"

2017-01-24 Thread Sinclair Yeh 
Minor typo

On Fri, Jan 13, 2017 at 10:51:10AM +0100, Christian König wrote:
> From: Christian König 
> 
> The additional housekeeping had to much CPU overhead,
   ^


> let's use the BO priorities instead.
> 
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 --
>  drivers/gpu/drm/ast/ast_ttm.c   |  2 --
>  drivers/gpu/drm/bochs/bochs_mm.c|  2 --
>  drivers/gpu/drm/cirrus/cirrus_ttm.c |  2 --
>  drivers/gpu/drm/mgag200/mgag200_ttm.c   |  2 --
>  drivers/gpu/drm/nouveau/nouveau_bo.c|  2 --
>  drivers/gpu/drm/qxl/qxl_ttm.c   |  2 --
>  drivers/gpu/drm/radeon/radeon_ttm.c |  2 --
>  drivers/gpu/drm/ttm/ttm_bo.c| 19 +--
>  drivers/gpu/drm/virtio/virtgpu_ttm.c|  2 --
>  drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c  |  2 --
>  include/drm/ttm/ttm_bo_driver.h |  9 -
>  12 files changed, 5 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index dd086d8..0402a11 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1086,8 +1086,6 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
>   .fault_reserve_notify = _bo_fault_reserve_notify,
>   .io_mem_reserve = _ttm_io_mem_reserve,
>   .io_mem_free = _ttm_io_mem_free,
> - .lru_tail = _bo_default_lru_tail,
> - .swap_lru_tail = _bo_default_swap_lru_tail,
>  };
>  
>  int amdgpu_ttm_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/ast/ast_ttm.c b/drivers/gpu/drm/ast/ast_ttm.c
> index 2a1368f..50c910e 100644
> --- a/drivers/gpu/drm/ast/ast_ttm.c
> +++ b/drivers/gpu/drm/ast/ast_ttm.c
> @@ -236,8 +236,6 @@ struct ttm_bo_driver ast_bo_driver = {
>   .verify_access = ast_bo_verify_access,
>   .io_mem_reserve = _ttm_io_mem_reserve,
>   .io_mem_free = _ttm_io_mem_free,
> - .lru_tail = _bo_default_lru_tail,
> - .swap_lru_tail = _bo_default_swap_lru_tail,
>  };
>  
>  int ast_mm_init(struct ast_private *ast)
> diff --git a/drivers/gpu/drm/bochs/bochs_mm.c 
> b/drivers/gpu/drm/bochs/bochs_mm.c
> index 099a3c6..e4c1125 100644
> --- a/drivers/gpu/drm/bochs/bochs_mm.c
> +++ b/drivers/gpu/drm/bochs/bochs_mm.c
> @@ -205,8 +205,6 @@ struct ttm_bo_driver bochs_bo_driver = {
>   .verify_access = bochs_bo_verify_access,
>   .io_mem_reserve = _ttm_io_mem_reserve,
>   .io_mem_free = _ttm_io_mem_free,
> - .lru_tail = _bo_default_lru_tail,
> - .swap_lru_tail = _bo_default_swap_lru_tail,
>  };
>  
>  int bochs_mm_init(struct bochs_device *bochs)
> diff --git a/drivers/gpu/drm/cirrus/cirrus_ttm.c 
> b/drivers/gpu/drm/cirrus/cirrus_ttm.c
> index d6da848..f53aa8f 100644
> --- a/drivers/gpu/drm/cirrus/cirrus_ttm.c
> +++ b/drivers/gpu/drm/cirrus/cirrus_ttm.c
> @@ -236,8 +236,6 @@ struct ttm_bo_driver cirrus_bo_driver = {
>   .verify_access = cirrus_bo_verify_access,
>   .io_mem_reserve = _ttm_io_mem_reserve,
>   .io_mem_free = _ttm_io_mem_free,
> - .lru_tail = _bo_default_lru_tail,
> - .swap_lru_tail = _bo_default_swap_lru_tail,
>  };
>  
>  int cirrus_mm_init(struct cirrus_device *cirrus)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_ttm.c 
> b/drivers/gpu/drm/mgag200/mgag200_ttm.c
> index 5e20220..657598b 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_ttm.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_ttm.c
> @@ -236,8 +236,6 @@ struct ttm_bo_driver mgag200_bo_driver = {
>   .verify_access = mgag200_bo_verify_access,
>   .io_mem_reserve = _ttm_io_mem_reserve,
>   .io_mem_free = _ttm_io_mem_free,
> - .lru_tail = _bo_default_lru_tail,
> - .swap_lru_tail = _bo_default_swap_lru_tail,
>  };
>  
>  int mgag200_mm_init(struct mga_device *mdev)
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
> b/drivers/gpu/drm/nouveau/nouveau_bo.c
> index 5b0a28b..3949a74 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> @@ -1570,8 +1570,6 @@ struct ttm_bo_driver nouveau_bo_driver = {
>   .fault_reserve_notify = _ttm_fault_reserve_notify,
>   .io_mem_reserve = _ttm_io_mem_reserve,
>   .io_mem_free = _ttm_io_mem_free,
> - .lru_tail = _bo_default_lru_tail,
> - .swap_lru_tail = _bo_default_swap_lru_tail,
>  };
>  
>  struct nvkm_vma *
> diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
> index f3939a9..2955f91 100644
> --- a/drivers/gpu/drm/qxl/qxl_ttm.c
> +++ b/drivers/gpu/drm/qxl/qxl_ttm.c
> @@ -395,8 +395,6 @@ static struct ttm_bo_driver qxl_bo_driver = {
>   .io_mem_reserve = _ttm_io_mem_reserve,
>   .io_mem_free = _ttm_io_mem_free,
>   .move_notify = _bo_move_notify,
> - .lru_tail = _bo_default_lru_tail,
> - .swap_lru_tail = _bo_default_swap_lru_tail,
>  };
>  
>  int qxl_ttm_init(struct qxl_device *qdev)
> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
>

RE: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox

2017-01-24 Thread Xue, Ken 
> From: Christian König [mailto:deathsim...@vodafone.de]
> Sent: Tuesday, January 24, 2017 10:09 PM
> To: Xue, Ken; amd-gfx mailing list
> Cc: dl.SRDC_SW_GPUVirtualization
> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and
> server by mailbox
> 
> Am 24.01.2017 um 13:55 schrieb Xue, Ken:
> > Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
> > message and after ACK server.
> >
> > Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
> > Signed-off-by: Ken Xue 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 
> >   1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > index d2622b6..b2c46db 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
> amdgpu_device *adev)
> >   static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
> >   {
> > u32 reg;
> > +   int timeout = VI_MAILBOX_TIMEDOUT;
> > +   u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
> >
> > reg = RREG32(mmMAILBOX_CONTROL);
> > reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
> > WREG32(mmMAILBOX_CONTROL, reg);
> > +
> > +   /*Wait for RCV_MSG_VALID to be 0*/
> > +   reg = RREG32(mmMAILBOX_CONTROL);
> > +   while (reg & mask) {
> > +   if (timeout <= 0) {
> > +   pr_err("RCV_MSG_VALID is not cleared\n");
> > +   break;
> > +   }
> > +   msleep(1);
> 
> Are you sure that you want to use msleep() here instead of mdelay() ?
> 
> msleep() is horrible inaccurate, e.g. depending on the definition of HZ you 
> can
> sleep for 10ms instead of 1ms IIRC.
> 
> mdelay() is a busy wait, so the CPU can't do anything else useful while 
> waiting
> but I don't think that this will hurt us here.

Thanks for your suggestion.
Currently, msleep may be a correct choice.
1)accuracy is not necessary here
2)the VI_MAILBOX_TIMEDOUT is 5000. if there is an issue from server side, 
driver may be delayed 5 seconds
3)I followed the same style like other codes in the same file.


Regards,
Ken
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Re: [PATCH 1/2] drm/amdgpu: fix 64bit shift for KV/KB

2017-01-24 Thread Felix Kuehling 
Series reviewed by me as well:

Reviewed-by: Felix Kuehling 


On 17-01-24 10:48 AM, Deucher, Alexander wrote:
>> -Original Message-
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Christian König
>> Sent: Tuesday, January 24, 2017 9:10 AM
>> To: amd-gfx@lists.freedesktop.org
>> Subject: [PATCH 1/2] drm/amdgpu: fix 64bit shift for KV/KB
>>
>> From: Christian König 
>>
>> Fixes "access stolen VRAM directly on KV/KB" otherwise that won't
>> work as expected with more than 4GB RAM.
>>
>> Signed-off-by: Christian König 
> Series is:
> Reviewed-by: Alex Deucher 
>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index ccce04d..8d05e0c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -378,7 +378,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device
>> *adev)
>>
>>  #ifdef CONFIG_X86_64
>>  if (adev->flags & AMD_IS_APU) {
>> -adev->mc.aper_base = RREG32(mmMC_VM_FB_OFFSET) <<
>> 22ULL;
>> +adev->mc.aper_base =
>> ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
>>  adev->mc.aper_size = adev->mc.real_vram_size;
>>  }
>>  #endif
>> --
>> 2.5.0
>>
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RE: [PATCH 1/2] drm/amdgpu: fix 64bit shift for KV/KB

2017-01-24 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, January 24, 2017 9:10 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 1/2] drm/amdgpu: fix 64bit shift for KV/KB
> 
> From: Christian König 
> 
> Fixes "access stolen VRAM directly on KV/KB" otherwise that won't
> work as expected with more than 4GB RAM.
> 
> Signed-off-by: Christian König 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index ccce04d..8d05e0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -378,7 +378,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device
> *adev)
> 
>  #ifdef CONFIG_X86_64
>   if (adev->flags & AMD_IS_APU) {
> - adev->mc.aper_base = RREG32(mmMC_VM_FB_OFFSET) <<
> 22ULL;
> + adev->mc.aper_base =
> ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
>   adev->mc.aper_size = adev->mc.real_vram_size;
>   }
>  #endif
> --
> 2.5.0
> 
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RE: [PATCH] drm/amd/powerplay: fix regresstion issue can't set manual dpm mode.

2017-01-24 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, January 24, 2017 4:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amd/powerplay: fix regresstion issue can't set manual
> dpm mode.
> 
> Change-Id: I0816a51efe696edfc2a37b17eaacb94660511038
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 6c661bb..0a6c833 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2625,6 +2625,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr
> *hwmgr,
>   smu7_force_clock_level(hwmgr, PP_MCLK, 1<   smu7_force_clock_level(hwmgr, PP_PCIE, 1<   break;
> + case AMD_DPM_FORCED_LEVEL_MANUAL:
> + hwmgr->dpm_level = level;
> + break;
>   case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
>   default:
>   break;
> --
> 1.9.1
> 
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Re: [PATCH 2/2] drm/amdgpu: fix 64bit shift for CZ

2017-01-24 Thread StDenis, Tom 
Works on my CZ system:


Ack-by: Tom St Denis 



From: amd-gfx  on behalf of Christian 
König 
Sent: Tuesday, January 24, 2017 09:09
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] drm/amdgpu: fix 64bit shift for CZ

From: Christian König 

Fixes "access stolen VRAM directly on CZ", otherwise that won't
work as expected with more than 4GB RAM.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index a564e89..7669b32 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -470,7 +470,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)

 #ifdef CONFIG_X86_64
 if (adev->flags & AMD_IS_APU) {
-   adev->mc.aper_base = RREG32(mmMC_VM_FB_OFFSET) << 22ULL;
+   adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 adev->mc.aper_size = adev->mc.real_vram_size;
 }
 #endif
--
2.5.0

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[PATCH 08/11] drm/amd/display: refactor dc_update_surfaces_for_stream

2017-01-24 Thread Harry Wentland 
From: Tony Cheng 

- reuse existing helper functions
- helper function to make it more obvious which cases we can do optimize 
programming

Change-Id: I5dbc2a9f896528a23364f76a4390c0847f260fd0
Signed-off-by: Tony Cheng 
Reviewed-by: Yongqiang Sun 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 367 ++-
 1 file changed, 212 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index de6ef8713ea8..170936bb378a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1007,7 +1007,7 @@ bool dc_commit_streams(
struct dc_bios *dcb = core_dc->ctx->dc_bios;
enum dc_status result = DC_ERROR_UNEXPECTED;
struct validate_context *context;
-   struct dc_validation_set set[MAX_STREAMS] = { 0 };
+   struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
int i, j, k;
 
if (false == streams_changed(core_dc, streams, stream_count))
@@ -1321,80 +1321,167 @@ bool dc_commit_surfaces_to_stream(
return dc_post_update_surfaces_to_stream(dc);
 }
 
-void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update 
*updates,
-   int surface_count, const struct dc_stream *dc_stream)
+static bool is_surface_in_context(
+   const struct validate_context *context,
+   const struct dc_surface *surface)
 {
-   struct core_dc *core_dc = DC_TO_CORE(dc);
-   struct validate_context *context = core_dc->temp_flip_context;
-   int i, j;
-   bool is_new_pipe_surface[MAX_PIPES];
-   const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 };
-   bool need_apply_clk_constraints = false;
-   bool can_skip_context_building = true;
+   int j;
 
-   update_surface_trace(dc, updates, surface_count);
+   for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
+   const struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
 
-   *context = *core_dc->current_context;
+   if (surface == _ctx->surface->public) {
+   return true;
+   }
+   }
 
-   for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
-   struct pipe_ctx *cur_pipe = >res_ctx.pipe_ctx[i];
+   return false;
+}
 
-   if (cur_pipe->top_pipe)
-   cur_pipe->top_pipe =
-   
>res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
+enum surface_update_type {
+   UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
+   UPDATE_TYPE_MED,  /* a lot of programming needed.  may need to alloc */
+   UPDATE_TYPE_FULL, /* may need to shuffle resources */
+};
 
-   if (cur_pipe->bottom_pipe)
-   cur_pipe->bottom_pipe =
-   
>res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
-   }
+static enum surface_update_type det_surface_update(
+   const struct core_dc *dc,
+   const struct dc_surface_update *u)
+{
+   const struct validate_context *context = dc->current_context;
 
-   for (j = 0; j < MAX_PIPES; j++)
-   is_new_pipe_surface[j] = true;
+   if (u->scaling_info || u->plane_info)
+   /* todo: not all scale and plane_info update need full update
+* ie. check if following is the same
+* scale ratio, view port, surface bpp etc
+*/
+   return UPDATE_TYPE_FULL; /* may need bandwidth update */
 
-   for (i = 0 ; i < surface_count; i++) {
-   struct core_surface *surface = 
DC_SURFACE_TO_CORE(updates[i].surface);
-   bool existing_surface = false;
+   if (!is_surface_in_context(context, u->surface))
+   return UPDATE_TYPE_FULL;
 
-   new_surfaces[i] = updates[i].surface;
+   if (u->in_transfer_func ||
+   u->out_transfer_func ||
+   u->hdr_static_metadata)
+   return UPDATE_TYPE_MED;
 
-   for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
-   struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[j];
+   return UPDATE_TYPE_FAST;
+}
 
-   if (surface == pipe_ctx->surface) {
-   existing_surface = true;
-   is_new_pipe_surface[j] = false;
-   }
-   }
+static enum surface_update_type check_update_surfaces_for_stream(
+   struct core_dc *dc,
+   struct dc_surface_update *updates,
+   int surface_count,
+   const struct dc_stream_status *stream_status)
+{
+   int i;
+   enum surface_update_type overall_type = UPDATE_TYPE_FAST;
 
-   if (updates[i].plane_info ||
-

RE: [radeon-alex:drm-next-4.11-wip 131/131] drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:380:48: error: expected ')' before ';' token

2017-01-24 Thread Deucher, Alexander 
> -Original Message-
> From: Nils Holland [mailto:nholl...@tisys.org]
> Sent: Monday, January 23, 2017 7:31 PM
> To: kbuild test robot
> Cc: kbuild-...@01.org; amd-gfx@lists.freedesktop.org; Deucher, Alexander;
> Daenzer, Michel; Koenig, Christian
> Subject: Re: [radeon-alex:drm-next-4.11-wip 131/131]
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:380:48: error: expected ')'
> before ';' token
> 
> On Tue, Jan 24, 2017 at 06:37:58AM +0800, kbuild test robot wrote:
> >
> >drivers/gpu/drm/amd/amdgpu/amdgpu_object.c: In function
> 'amdgpu_bo_create_restricted':
> > >> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:377:2: warning:
> #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better
> performance thanks to write-combining [-Wcpp]
> > #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better
> performance \
> >  ^~~
> > >> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:380:48: error:
> expected ')' before ';' token
> >  if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;)
> >^
> >
> > vim +380 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> >
> >371  #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
> >372  /* Don't try to enable write-combining when it can't 
> > work, or
> things
> >373   * may be slow
> >374   * See 
> > https://bugs.freedesktop.org/show_bug.cgi?id=88758
> >375   */
> >376
> >  > 377  #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for
> better performance \
> >378   thanks to write-combining
> >379
> >  > 380  if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;)
> >381  DRM_INFO_ONCE("Please enable CONFIG_MTRR
> and CONFIG_X86_PAT for "
> >382"better performance thanks to 
> > write-
> combining\n");
> >383  bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> 
> Whoops, the robot is certainly right, there's a ; that doesn't belong
> in line 380. Shame on me! :-(
> 
> Michel, now that you've already commited this patch, what do I do?
> Should I submit another patch that just fixes this one issue, or
> should I re-submit the whole patch, in fixed state, as a v2?
> 
> Sorry for the hassle! :-/

I fixed this up locally when I committed it.  It's already taken care of.

Alex

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[PATCH 00/11] DC Patches Jan 24, 2017

2017-01-24 Thread Harry Wentland 
* Mostly bug fixes here this time

Dmytro Laktyushkin (1):
  drm/amd/display: prevent setting cursor position with no surface

Harry Wentland (2):
  drm/amd/display: Don't reserve pipe for underlay on ASIC without
underlay
  drm/amd/display: Remove power gating debug flags

Hersen Wu (1):
  drm/amd/display: Check we got a stream in update_info_frame

Joshua Aberback (1):
  drm/amd/display: Proper de-allocation of OPP

Leon Elazar (1):
  drm/amd/display: check surface size is at least as large as stream

Tony Cheng (3):
  drm/amd/display: improve debug-ability
  drm/amd/display: refactor dc_update_surfaces_for_stream
  drm/amd/display: clean up redundant logic

Yongqiang Sun (2):
  drm/amd/display: Change update surface condition, fix surface
transition corruption.
  drm/amd/display: Fixed 4K black issue by refactor update surface.

 drivers/gpu/drm/amd/display/dc/core/dc.c   | 370 -
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc_surface.c   |  23 +-
 drivers/gpu/drm/amd/display/dc/dc.h|   3 -
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c   |  10 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h   |  35 --
 .../drm/amd/display/dc/dce100/dce100_resource.c|  30 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|   5 +
 .../drm/amd/display/dc/dce110/dce110_resource.c|   4 +-
 .../drm/amd/display/dc/dce112/dce112_resource.c|  32 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/inc/core_status.h   |  26 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   2 +
 13 files changed, 259 insertions(+), 287 deletions(-)

-- 
2.9.3

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[PATCH 10/11] drm/amd/display: Check we got a stream in update_info_frame

2017-01-24 Thread Harry Wentland 
From: Hersen Wu 

Change-Id: I649fd0d9a986a2a7474dafd262fa1b5282666ada
Signed-off-by: Hersen Wu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 6dbfc570b8c6..ce56f23806bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -837,6 +837,11 @@ static enum dc_status bios_parser_crtc_source_select(
 
 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 {
+   ASSERT(pipe_ctx->stream);
+
+   if (pipe_ctx->stream_enc == NULL)
+   return;  /* this is not root pipe */
+
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_enc->funcs->update_hdmi_info_packets(
pipe_ctx->stream_enc,
-- 
2.9.3

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[PATCH 04/11] drm/amd/display: Proper de-allocation of OPP

2017-01-24 Thread Harry Wentland 
From: Joshua Aberback 

- refactor opp_destroy functions to dce common file
  - fixes memory leak, dce specific variations didn't free regamma_params
- remove unused dce110_regamma structure

Change-Id: I30b8540c0367001e69b9571819f93866a1d59cb2
Signed-off-by: Joshua Aberback 
Reviewed-by: Jun Lei 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c   | 10 ---
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h   | 35 --
 .../drm/amd/display/dc/dce100/dce100_resource.c| 26 +---
 .../drm/amd/display/dc/dce112/dce112_resource.c| 26 +---
 4 files changed, 8 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 061de9e8249d..62f01911639f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -986,10 +986,12 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
 
 void dce110_opp_destroy(struct output_pixel_processor **opp)
 {
-   dm_free((*opp)->regamma_params);
-   (*opp)->regamma_params = NULL;
-
-   dm_free(FROM_DCE11_OPP(*opp));
+   if (*opp) {
+   if ((*opp)->regamma_params)
+   dm_free((*opp)->regamma_params);
+   (*opp)->regamma_params = NULL;
+   dm_free(FROM_DCE11_OPP(*opp));
+   }
*opp = NULL;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index f2828f044b96..a5afc0298d6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -312,40 +312,6 @@ struct dce_opp_registers {
uint32_t FMT_CLAMP_COMPONENT_B;
 };
 
-struct dce110_regamma {
-   struct gamma_curve arr_curve_points[16];
-   struct curve_points arr_points[3];
-   uint32_t hw_points_num;
-   struct hw_x_point *coordinates_x;
-   struct pwl_result_data *rgb_resulted;
-
-   /* re-gamma curve */
-   struct pwl_float_data_ex *rgb_regamma;
-   /* coeff used to map user evenly distributed points
-* to our hardware points (predefined) for gamma 256 */
-   struct pixel_gamma_point *coeff128;
-   struct pixel_gamma_point *coeff128_oem;
-   /* coeff used to map user evenly distributed points
-* to our hardware points (predefined) for gamma 1025 */
-   struct pixel_gamma_point *coeff128_dx;
-   /* evenly distributed points, gamma 256 software points 0-255 */
-   struct gamma_pixel *axis_x_256;
-   /* evenly distributed points, gamma 1025 software points 0-1025 */
-   struct gamma_pixel *axis_x_1025;
-   /* OEM supplied gamma for regamma LUT */
-   struct pwl_float_data *rgb_oem;
-   /* user supplied gamma */
-   struct pwl_float_data *rgb_user;
-   uint32_t extra_points;
-   bool use_half_points;
-   struct fixed31_32 x_max1;
-   struct fixed31_32 x_max2;
-   struct fixed31_32 x_min;
-   struct fixed31_32 divider1;
-   struct fixed31_32 divider2;
-   struct fixed31_32 divider3;
-};
-
 /* OPP RELATED */
 #define TO_DCE110_OPP(opp)\
container_of(opp, struct dce110_opp, base)
@@ -355,7 +321,6 @@ struct dce110_opp {
const struct dce_opp_registers *regs;
const struct dce_opp_shift *opp_shift;
const struct dce_opp_mask *opp_mask;
-   struct dce110_regamma regamma;
 };
 
 bool dce110_opp_construct(struct dce110_opp *opp110,
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index dc4f270ae44a..6ae334b42fbf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -633,30 +633,6 @@ struct output_pixel_processor *dce100_opp_create(
return NULL;
 }
 
-void dce100_opp_destroy(struct output_pixel_processor **opp)
-{
-   struct dce110_opp *dce110_opp;
-
-   if (!opp || !*opp)
-   return;
-
-   dce110_opp = FROM_DCE11_OPP(*opp);
-
-   dm_free(dce110_opp->regamma.coeff128_dx);
-   dm_free(dce110_opp->regamma.coeff128_oem);
-   dm_free(dce110_opp->regamma.coeff128);
-   dm_free(dce110_opp->regamma.axis_x_1025);
-   dm_free(dce110_opp->regamma.axis_x_256);
-   dm_free(dce110_opp->regamma.coordinates_x);
-   dm_free(dce110_opp->regamma.rgb_regamma);
-   dm_free(dce110_opp->regamma.rgb_resulted);
-   dm_free(dce110_opp->regamma.rgb_oem);
-   dm_free(dce110_opp->regamma.rgb_user);
-   dm_free(dce110_opp);
-
-   *opp = NULL;
-}
-
 struct clock_source *dce100_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
@@ -692,7 +668,7 @@ static void destruct(struct dce110_resource_pool *pool)
 
for (i = 0; i < pool->base.pipe_count;

[PATCH 02/11] drm/amd/display: Remove power gating debug flags

2017-01-24 Thread Harry Wentland 
They're not used anywhere

Change-Id: I607045a32ec1af4bb802a90b26301e328ef7f306
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index e0143f9f0421..332ecf8b1157 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -145,8 +145,6 @@ struct dc_debug {
bool disable_stutter;
bool disable_dcc;
bool disable_dfs_bypass;
-   bool disable_dpp_power_gate;
-   bool disable_hubp_power_gate;
bool disable_clock_gate;
bool disable_dmcu;
bool disable_color_module;
-- 
2.9.3

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[PATCH 06/11] drm/amd/display: prevent setting cursor position with no surface

2017-01-24 Thread Harry Wentland 
From: Dmytro Laktyushkin 

Change-Id: I98ac559661295af4c2d4d151c4dd6029e27349c1
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 47816c5ee0e0..e1f579bcd789 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -232,8 +232,8 @@ bool dc_stream_set_cursor_position(
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = _ctx->pipe_ctx[i];
 
-   if ((pipe_ctx->stream == stream) &&
-   (pipe_ctx->ipp != NULL)) {
+   if (pipe_ctx->stream == stream &&
+   pipe_ctx->ipp && pipe_ctx->surface) {
struct input_pixel_processor *ipp = pipe_ctx->ipp;
struct dc_cursor_mi_param param = {
.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
-- 
2.9.3

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[PATCH 01/11] drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay

2017-01-24 Thread Harry Wentland 
Change-Id: I961ed1bf9cb255cddf05b24c9915c830df492f89
Signed-off-by: Harry Wentland 
Acked-by: Jordan Lazare 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 2 +-
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 ++
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f9b7fc85d71a..270f8c5cfeda 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -621,7 +621,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
core_dc->hwss.init_hw(core_dc);
 
full_pipe_count = core_dc->res_pool->pipe_count;
-   if (core_dc->res_pool->underlay_pipe_index >= 0)
+   if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
full_pipe_count--;
core_dc->public.caps.max_streams = min(
full_pipe_count,
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index ae0e7eac2c9d..dc4f270ae44a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -934,7 +934,7 @@ static bool construct(
 
pool->base.res_cap = _cap;
pool->base.funcs = _res_pool_funcs;
-   pool->base.underlay_pipe_index = -1;
+   pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 
bp = ctx->dc_bios;
 
@@ -1004,7 +1004,7 @@ static bool construct(
/*
*  Resource + asic cap harcoding*
*/
-   pool->base.underlay_pipe_index = -1;
+   pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 64fae91dd5eb..fa8699d3b9ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1243,7 +1243,7 @@ static bool construct(
/*
 *  Resource + asic cap harcoding*
 */
-   pool->base.underlay_pipe_index = -1;
+   pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 100;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index bee3a41ffe9f..fea60aa5d297 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -931,7 +931,7 @@ static bool construct(
/*
 *  Resource + asic cap harcoding*
 */
-   pool->base.underlay_pipe_index = -1;
+   pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 66bfcdb57c4c..b349b5768b6e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -230,6 +230,8 @@ struct audio_support{
bool hdmi_audio_native;
 };
 
+#define NO_UNDERLAY_PIPE -1
+
 struct resource_pool {
struct mem_input *mis[MAX_PIPES];
struct input_pixel_processor *ipps[MAX_PIPES];
-- 
2.9.3

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[PATCH 05/11] drm/amd/display: Change update surface condition, fix surface transition corruption.

2017-01-24 Thread Harry Wentland 
From: Yongqiang Sun 

Change-Id: I637bab884686aa244d9d896dbc4facd10bafe66b
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +++
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 270f8c5cfeda..de6ef8713ea8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1497,7 +1497,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct 
dc_surface_update *upda
 
for (i = 0; i < surface_count; i++) {
struct core_surface *surface = 
DC_SURFACE_TO_CORE(updates[i].surface);
-   bool apply_ctx = false;
 
for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[j];
@@ -1505,13 +1504,9 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct 
dc_surface_update *upda
if (pipe_ctx->surface != surface)
continue;
 
-   if (updates[i].flip_addr) {
+   if (updates[i].flip_addr && can_skip_context_building) {
core_dc->hwss.update_plane_addr(core_dc, 
pipe_ctx);
-   }
-
-   if (updates[i].plane_info || updates[i].scaling_info
-   || is_new_pipe_surface[j]) {
-   apply_ctx = true;
+   } else {
 
if 
(!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
@@ -1546,7 +1541,7 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct 
dc_surface_update *upda
}
 
}
-   if (apply_ctx) {
+   if (!can_skip_context_building) {
core_dc->hwss.apply_ctx_for_surface(core_dc, surface, 
context);
context_timing_trace(dc, >res_ctx);
}
-- 
2.9.3

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[PATCH 11/11] drm/amd/display: Fixed 4K black issue by refactor update surface.

2017-01-24 Thread Harry Wentland 
From: Yongqiang Sun 

Change-Id: Ibff4c15aeddf0a013a9c2edca9b82219818cfccb
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 28 
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 170936bb378a..01d614781def 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1482,17 +1482,19 @@ void dc_update_surfaces_for_stream(struct dc *dc,
}
 
/* not sure if we still need this */
-   for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
-   struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[j];
-   struct core_stream *stream = pipe_ctx->stream;
+   if (update_type == UPDATE_TYPE_FULL) {
+   for (j = 0; j < context->res_ctx.pool->pipe_count; j++) 
{
+   struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[j];
+   struct core_stream *stream = pipe_ctx->stream;
 
-   if (pipe_ctx->surface != surface)
-   continue;
+   if (pipe_ctx->surface != surface)
+   continue;
 
-   resource_build_scaling_params(updates[i].surface, 
pipe_ctx);
-   if (dc->debug.surface_visual_confirm) {
-   pipe_ctx->scl_data.recout.height -= 2;
-   pipe_ctx->scl_data.recout.width -= 2;
+   
resource_build_scaling_params(updates[i].surface, pipe_ctx);
+   if (dc->debug.surface_visual_confirm) {
+   pipe_ctx->scl_data.recout.height -= 2;
+   pipe_ctx->scl_data.recout.width -= 2;
+   }
}
}
 
@@ -1563,10 +1565,12 @@ void dc_update_surfaces_for_stream(struct dc *dc,
}
 
if (update_type == UPDATE_TYPE_FULL) {
-   core_dc->hwss.apply_ctx_for_surface(core_dc, 
surface, context);
-   } else if (updates[i].flip_addr) {
+   /* only apply for top pipe */
+   if (!pipe_ctx->top_pipe)
+   
core_dc->hwss.apply_ctx_for_surface(core_dc,
+surface, context);
+   } else if (updates[i].flip_addr)
core_dc->hwss.update_plane_addr(core_dc, 
pipe_ctx);
-   }
 
if (update_type == UPDATE_TYPE_FAST)
continue;
-- 
2.9.3

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[PATCH 07/11] drm/amd/display: improve debug-ability

2017-01-24 Thread Harry Wentland 
From: Tony Cheng 

- make failure status obvious

Change-Id: If8106b3ac98433817b1fdd414c0776f983b616a9
Signed-off-by: Tony Cheng 
Reviewed-by: Yongqiang Sun 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/inc/core_status.h | 26 
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 147eb7cac701..23d52aea55dd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -29,19 +29,19 @@
 enum dc_status {
DC_OK = 1,
 
-   DC_NO_CONTROLLER_RESOURCE,
-   DC_NO_STREAM_ENG_RESOURCE,
-   DC_NO_CLOCK_SOURCE_RESOURCE,
-   DC_FAIL_CONTROLLER_VALIDATE,
-   DC_FAIL_ENC_VALIDATE,
-   DC_FAIL_ATTACH_SURFACES,
-   DC_FAIL_SURFACE_VALIDATE,
-   DC_NO_DP_LINK_BANDWIDTH,
-   DC_EXCEED_DONGLE_MAX_CLK,
-   DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED,
-   DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */
-   DC_FAIL_SCALING,
-   DC_FAIL_CLK_CONSTRAINT,
+   DC_NO_CONTROLLER_RESOURCE = 2,
+   DC_NO_STREAM_ENG_RESOURCE = 3,
+   DC_NO_CLOCK_SOURCE_RESOURCE = 4,
+   DC_FAIL_CONTROLLER_VALIDATE = 5,
+   DC_FAIL_ENC_VALIDATE = 6,
+   DC_FAIL_ATTACH_SURFACES = 7,
+   DC_FAIL_SURFACE_VALIDATE = 8,
+   DC_NO_DP_LINK_BANDWIDTH = 9,
+   DC_EXCEED_DONGLE_MAX_CLK = 10,
+   DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11,
+   DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */
+   DC_FAIL_SCALING = 13,
+   DC_FAIL_CLK_CONSTRAINT = 14,
 
DC_ERROR_UNEXPECTED = -1
 };
-- 
2.9.3

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[PATCH 2/2] drm/amdgpu: fix 64bit shift for CZ

2017-01-24 Thread Christian König 
From: Christian König 

Fixes "access stolen VRAM directly on CZ", otherwise that won't
work as expected with more than 4GB RAM.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index a564e89..7669b32 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -470,7 +470,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 
 #ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
-   adev->mc.aper_base = RREG32(mmMC_VM_FB_OFFSET) << 22ULL;
+   adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
adev->mc.aper_size = adev->mc.real_vram_size;
}
 #endif
-- 
2.5.0

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[PATCH 1/2] drm/amdgpu: fix 64bit shift for KV/KB

2017-01-24 Thread Christian König 
From: Christian König 

Fixes "access stolen VRAM directly on KV/KB" otherwise that won't
work as expected with more than 4GB RAM.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index ccce04d..8d05e0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -378,7 +378,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 
 #ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
-   adev->mc.aper_base = RREG32(mmMC_VM_FB_OFFSET) << 22ULL;
+   adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
adev->mc.aper_size = adev->mc.real_vram_size;
}
 #endif
-- 
2.5.0

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Re: amdgpu: fix performance drop

2017-01-24 Thread Christian König 

Hi Sinclair,

you probably have missed this set of patches I've send to the dri-devel 
mailing list a while ago.


It basically replaces some work for TTM I've did back in April last year 
and you reviewed with a different implementation.


The original callback design turned out to have to much overhead which 
made this change necessary. Could you take a look at the new 
implementation as well?


Thanks in advance,
Christian.
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[PATCH] drm/amd/powerplay: fix regresstion issue can't set manual dpm mode.

2017-01-24 Thread Rex Zhu 
Change-Id: I0816a51efe696edfc2a37b17eaacb94660511038
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6c661bb..0a6c833 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2625,6 +2625,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
smu7_force_clock_level(hwmgr, PP_MCLK, 1<dpm_level = level;
+   break;
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
default:
break;
-- 
1.9.1

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RE: [virtual display] code review

2017-01-24 Thread Tao, Yintian 
Hi  Christian

Thanks for your guidance. I will follow it next time.


Best Regards
Yintian Tao

-Original Message-
From: Koenig, Christian 
Sent: Tuesday, January 24, 2017 5:31 PM
To: Tao, Yintian ; Deucher, Alexander 

Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [virtual display] code review

For public mailing lists please use text format only, not HTML mail.

Apart from that the patch looks good to me and is Reviewed-by: Christian König 
.

Regards,
Christian.

Am 24.01.2017 um 10:19 schrieb Tao, Yintian:
>
> Hi  Christian
>
> Please help to review this patch. The whole story is as follows：
>
> For pass-through case, amdgpu module driver may be included into one 
> image with specified BDF parameter,
>
> which will cause the failure of virtual display creation when the slot 
> where GPU is put into is modified.
>
> Therefore adding the new parameter “all” for virtual display enable 
> will fix this issue. Thanks a lot.
>
> Best Regards
>
> Yintian Tao
>

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[virtual display] code review

2017-01-24 Thread Tao, Yintian 
Hi  Christian


Please help to review this patch. The whole story is as follows：

For pass-through case, amdgpu module driver may be included into one image with 
specified BDF parameter,

which will cause the failure of virtual display creation when the slot where 
GPU is put into is modified.

Therefore adding the new parameter “all” for virtual display enable will fix 
this issue. Thanks a lot.


Best Regards
Yintian Tao



0001-drm-amdgpu-add-new-virtual-display-ID.patch
Description: 0001-drm-amdgpu-add-new-virtual-display-ID.patch
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