Re: [PATCH 2/4] PCI: add functionality for resizing resources v2

On Mon, Mar 13, 2017 at 01:41:34PM +0100, Christian König wrote: > From: Christian König > > This allows device drivers to request resizing their BARs. > > The function only tries to reprogram the windows of the bridge directly above > the requesting device and only

Re: [PATCH 3/3] drm/amdgpu/soc15: return cached values for some registers

We're reporting gb_addr_config to user mode in our KFD tiling info API. If this is no longer needed by user mode for soc15, we could just put in a dummy value. However, I haven't been told that it can be removed for older ASICs. Regards, Felix On 17-03-24 03:48 PM, Alex Deucher wrote: > On

Re: Plan: BO move throttling for visible VRAM evictions

On 03/24/2017 05:33 PM, Marek Olšák wrote: Hi, I'm sharing this idea here, because it's something that has been decreasing our performance a lot recently, for example: http://openbenchmarking.org/prospect/1703011-RI-RADEONDIR06/7b7668cfc109d1c3dc27e871c8aea71ca13f23fa I think the problem

Re: [PATCH 3/3] drm/amdgpu/soc15: return cached values for some registers

Am 24.03.2017 um 20:13 schrieb Alex Deucher: Required for SR-IOV and saves MMIO transactions. Signed-off-by: Alex Deucher As far as I can see they are not used any more by userspace and the same info is available in enabled_rb_pipes_mask. So why do you want to

[PATCH 2/3] drm/amdgpu/gfx9: cache RB harvest registers

So we don't have to look this up via MMIO when users request the value via ioctl. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

[PATCH 3/3] drm/amdgpu/soc15: return cached values for some registers

Required for SR-IOV and saves MMIO transactions. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 40 ++ 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 1/3] drm/amdgpu/gfx9: use hweight for calculating num_rbs

Match what we do for other asics. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index

Re: [PATCH] Revert "drm/radeon: Try evicting from CPU accessible to inaccessible VRAM first"

Hi Michel, No this change does not help on the other issue (hard lockup). I have no tried it in combination with the 0 -> i change. Thx anyway. Julien On 24 March 2017 at 10:03, Michel Dänzer wrote: > On 24/03/17 12:31 AM, Zachary Michaels wrote: > > > > I should also

Re: [PATCH 2/2] drm/amdgpu: sanitize soc15_allowed_read_registers

Am 24.03.2017 um 19:38 schrieb Alex Deucher: On Fri, Mar 24, 2017 at 11:09 AM, Christian König wrote: From: Christian König Disallow mmCC_RB_BACKEND_DISABLE, reading it can cause GRBM problems and the same info is available cached as

Re: [PATCH] Revert "drm/radeon: Try evicting from CPU accessible to inaccessible VRAM first"

Hi Michel, I double checked and you are right, the change 0 -> i works. Cheers Julien On 24 March 2017 at 09:59, Michel Dänzer wrote: > On 24/03/17 06:50 PM, Julien Isorce wrote: > > Hi Michel, > > > > (Just for other readers my reply has been delayed on the mailing lists

Re: [PATCH 2/2] drm/amdgpu: sanitize soc15_allowed_read_registers

On Fri, Mar 24, 2017 at 11:09 AM, Christian König wrote: > From: Christian König > > Disallow mmCC_RB_BACKEND_DISABLE, reading it can cause GRBM problems and the > same info is available cached as enabled_rb_pipes_mask. NACK. We need to

Re: [PATCH 1/2] drm/amdgpu: drop GB_GPU_ID from the golden settings

On Fri, Mar 24, 2017 at 11:09 AM, Christian König wrote: > From: Christian König > > That register is marked deprecated, reading it results in a bus error. > > Signed-off-by: Christian König Might want to compare with

RE: Plan: BO move throttling for visible VRAM evictions

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Marek Olšák > Sent: Friday, March 24, 2017 12:34 PM > To: amd-gfx mailing list > Subject: Plan: BO move throttling for visible VRAM evictions > > Hi, > > I'm sharing this idea here, because

Re: Plan: BO move throttling for visible VRAM evictions

On Fri, Mar 24, 2017 at 5:45 PM, Christian König wrote: > Am 24.03.2017 um 17:33 schrieb Marek Olšák: >> >> Hi, >> >> I'm sharing this idea here, because it's something that has been >> decreasing our performance a lot recently, for example: >> >>

Re: Plan: BO move throttling for visible VRAM evictions

Am 24.03.2017 um 17:33 schrieb Marek Olšák: Hi, I'm sharing this idea here, because it's something that has been decreasing our performance a lot recently, for example: http://openbenchmarking.org/prospect/1703011-RI-RADEONDIR06/7b7668cfc109d1c3dc27e871c8aea71ca13f23fa I think the problem

Re: [PATCH 1/4] PCI: add resizeable BAR infrastructure v3

On Mon, Mar 13, 2017 at 01:41:33PM +0100, Christian König wrote: > From: Christian König > > Just the defines and helper functions to read the possible sizes of a BAR and > update it's size. s/it's/its/ > See >

Plan: BO move throttling for visible VRAM evictions

Hi, I'm sharing this idea here, because it's something that has been decreasing our performance a lot recently, for example: http://openbenchmarking.org/prospect/1703011-RI-RADEONDIR06/7b7668cfc109d1c3dc27e871c8aea71ca13f23fa I think the problem there is that Mesa git started uploading

RE: [PATCH 09/13] drm/amdgpu:fix gmc_v9 vm fault process for SRIOV

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 09/13] drm/amdgpu:fix gmc_v9 vm fault process for SRIOV > > for SRIOV we

[PATCH 1/2] drm/amdgpu: drop GB_GPU_ID from the golden settings

From: Christian König That register is marked deprecated, reading it results in a bus error. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 - 1 file changed, 1 deletion(-) diff --git

[PATCH 2/2] drm/amdgpu: sanitize soc15_allowed_read_registers

From: Christian König Disallow mmCC_RB_BACKEND_DISABLE, reading it can cause GRBM problems and the same info is available cached as enabled_rb_pipes_mask. Also remove duplicate mmCP_CPF_BUSY_STAT. Signed-off-by: Christian König ---

RE: [PATCH umr] Add new AI CG bits to umr_print_config()

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Friday, March 24, 2017 9:49 AM > To: amd-gfx@lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH umr] Add new AI CG bits to umr_print_config() > > Signed-off-by:

RE: [PATCH 11/13] drm/amdgpu:fix missing programing critical registers

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:39 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 11/13] drm/amdgpu:fix missing programing critical registers > > those

RE: [PATCH 08/13] drm/amdgpu:no cg for soc15 of SRIOV

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 08/13] drm/amdgpu:no cg for soc15 of SRIOV > > no CG for SRIOV on SOC15

RE: [PATCH 06/13] drm/amdgpu:change sequence of SDMA v4 init

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 06/13] drm/amdgpu:change sequence of SDMA v4 init > > must set

RE: [PATCH 07/13] drm/amdgpu:two fixings for sdma v4 for SRIOV

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 07/13] drm/amdgpu:two fixings for sdma v4 for SRIOV > > no hw_fini for

RE: [PATCH 04/13] drm/amdgpu:virt_init_setting invoke is missed!

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 04/13] drm/amdgpu:virt_init_setting invoke is missed! > > this must be

RE: [PATCH 02/13] drm/amdgpu:enable mcbp for gfx9

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 02/13] drm/amdgpu:enable mcbp for gfx9 > > set bit 21 of IB.control

RE: [PATCH 01/13] drm/amdgpu:imple cond_exec for gfx8

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx@lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 01/13] drm/amdgpu:imple cond_exec for gfx8 > > when MCBP enalbed for

RE: [PATCH 6/6] drm/amdgpu: fix to remove HDP MGCG on soc15

> -Original Message- > From: Huang Rui [mailto:ray.hu...@amd.com] > Sent: Friday, March 24, 2017 1:48 AM > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander > Cc: Huan, Alvin; Huang, Ray > Subject: [PATCH 6/6] drm/amdgpu: fix to remove HDP MGCG on soc15 > > SOC15 doesn't enable HDP

[PATCH umr] Add family text for family 141

Signed-off-by: Tom St Denis --- src/app/print_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/app/print_config.c b/src/app/print_config.c index 6dbe0d42b8dc..e295302ab7a3 100644 --- a/src/app/print_config.c +++ b/src/app/print_config.c @@ -91,6 +91,7 @@

[PATCH umr] Add new AI CG bits to umr_print_config()

Signed-off-by: Tom St Denis --- src/app/print_config.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/app/print_config.c b/src/app/print_config.c index 6a4bf5dd594a..6dbe0d42b8dc 100644 --- a/src/app/print_config.c +++ b/src/app/print_config.c @@ -54,6 +54,12

Re: [PATCH umr] Add program memory dump to wave status.

Reviewed-by: Edward O'Callaghan On 03/22/2017 01:11 AM, Tom St Denis wrote: > It will display the leading 4 words up to > the current PC value and then 4 words after. > > Signed-off-by: Tom St Denis > --- > src/app/print_waves.c | 44

Re: [PATCH 0/6] drm/amdgpu: add get clockgating functions for new asic

This series is, Reviewed-by: Edward O'Callaghan On 03/24/2017 04:47 PM, Huang Rui wrote: > Hi all, > > This patch set adds get_clockgating functions, after that, we can use > debugfs pm to check the dynamic clockgating status. > > Thanks, > Rui > > Huang Rui (6):

Re: [PATCH 3/6] drm/amdgpu: add get_clockgating callback for soc15

On 03/24/17 00:47, Huang Rui wrote: > Signed-off-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 +++ > drivers/gpu/drm/amd/amdgpu/soc15.c | 34 > ++ > 2 files changed, 37 insertions(+) > > diff --git

RE: [PATCH 00/13] *** VEGA10 SRIOV PATCHES ***

Reviewed-by: Xiangliang Yu for the series. Thanks! Xiangliang Yu > -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 PM > To: amd-gfx@lists.freedesktop.org > Cc: Liu,

[PATCH 10/13] drm/amdgpu:fix ring_write_multiple

ring_write_multiple should use buf_mask instead of ptr_mask Change-Id: Ia249b6a1a990a6c3cba5c4048de6d604bb91d0ef Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 12/13] drm/amdgpu:changes in gfx DMAframe scheme

1) Adapt to vulkan: Now use double SWITCH BUFFER to replace the 128 nops w/a, because when vulkan introduced, umd can insert 7 ~ 16 IBs per submit which makes 256 DW size cannot hold the whole DMAframe (if we still insert those 128 nops), CP team suggests use double SWITCH_BUFFERs, instead of

[PATCH 05/13] drm/amdgpu:fix ring init sequence

ring->buf_mask need be set prior to ring_clear_ring invoke and fix ring_clear_ring as well which should use buf_mask instead of ptr_mask Change-Id: I7778a7afe27ac2bdedcaba1b0146582100602f9d Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 6 +++---

[PATCH 00/13] *** VEGA10 SRIOV PATCHES ***

patch 1 is a fix for VI patch 2 to patch 11 are bug fixings for vega10 for SRIOV patch 12/13 is the DMAframe scheme change to fix CE VM fault after world switch. Monk Liu (13): drm/amdgpu:imple cond_exec for gfx8 drm/amdgpu:enable mcbp for gfx9 drm/amdgpu:add KIQ interrupt id

[PATCH 04/13] drm/amdgpu:virt_init_setting invoke is missed!

this must be invoked during early init Change-Id: I68726dd36825259913b47493ba1e9c467b368d0c Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 06/13] drm/amdgpu:change sequence of SDMA v4 init

must set minor_update.enable before write smaller value to wptr/doorbell, so for sriov we need set that register bit in hw_init period. this could fix the SDMA ring test fail after guest reboot Change-Id: Id863396788cc5b35550cdcac405131d41690e77a Signed-off-by: Monk Liu ---

[PATCH 13/13] drm/amdgpu:change emit_frame_size of gfx8

and no need to insert 128 nops after gfx8 vm flush anymore because there was double SWITCH_BUFFER append to vm flush Change-Id: I6ecec95236bd1745f2beaa1b34a075748813f131 Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 29 ++--- 1

[PATCH 11/13] drm/amdgpu:fix missing programing critical registers

those MC_VM registers won't be programed by VBIOS in VF so driver is responsible to programe them. Change-Id: I817371346d86bd5668ac80a486dadc1605d0b6ca Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

[PATCH 07/13] drm/amdgpu:two fixings for sdma v4 for SRIOV

no hw_fini for SRIOV, otherwise other VF will be affected no CG for SRIOV Change-Id: I1b0525eb8d08754b4bd1a6ee6798bf5e41c6bc6b Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCH 02/13] drm/amdgpu:enable mcbp for gfx9

set bit 21 of IB.control filed to actually enable MCBP for SRIOV Change-Id: Ie5126d5be95e037087cf7167c28c61975f40d784 Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Re: [PATCH] Revert "drm/radeon: Try evicting from CPU accessible to inaccessible VRAM first"

On 24/03/17 06:50 PM, Julien Isorce wrote: > Hi Michel, > > (Just for other readers my reply has been delayed on the mailing lists > and should have been on second position) It is on https://patchwork.freedesktop.org/patch/145731/ , did you mean something else? The delay was because you weren't

Re: [PATCH] Revert "drm/radeon: Try evicting from CPU accessible to inaccessible VRAM first"

Hi Michel, (Just for other readers my reply has been delayed on the mailing lists and should have been on second position) We have actually spotted this /0/i/ but somehow I convinced myself it was intentional. The reason I found was that you wanted to set the fpfn only if there is 2 placements,

Re: [PATCH 00/18] *** multiple level VMPT enablement ***

Patches #11 and #18 are Reviewed-by: Christian König . Patch #12 is a NAK, that will also increase the VM space for pre gfx9 and we already found that this isn't a good idea. We should change how that value is evaluated in the different GMC handling code instead.

Re: [PATCH v2 1/2] drm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freed

Am 23.03.2017 um 20:27 schrieb Nicolai Hähnle: From: Nicolai Hähnle We will add the fence to freed buffer objects in a later commit, to ensure that the underlying memory can only be re-used after all references in page tables have been cleared. Signed-off-by: Nicolai

[PATCH 5/6] drm/amdgpu: add get_clockgating callback for mmhub v1

Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index b1e0e6b..68e5f7a 100644 ---

[PATCH 0/6] drm/amdgpu: add get clockgating functions for new asic

Hi all, This patch set adds get_clockgating functions, after that, we can use debugfs pm to check the dynamic clockgating status. Thanks, Rui Huang Rui (6): drm/amdgpu: add get_clockgating callback for gfx v9 drm/amdgpu: add get_clockgating callback for nbio v6.1 drm/amdgpu: add

[PATCH 4/6] drm/amdgpu: add get_clockgating for sdma v4

Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 7347326..df4b1d3 100644 ---

[PATCH 2/6] drm/amdgpu: add get_clockgating callback for nbio v6.1

Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 1 + drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 15 +++ drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 1 + 3 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c