Re: [PATCH xf86-video-ati] Set correct DRM event context version

On 10/04/17 06:42 PM, Emil Velikov wrote: > On 10 April 2017 at 09:37, Michel Dänzer wrote: >> From: Daniel Stone >> >> DRM_EVENT_CONTEXT_VERSION is the latest context version supported by >> whatever version of libdrm is present. We were blindly

答复: [PATCH] drm/amdgpu: Fix firmware UCODE_ID_STORAGE issue

Don't change bare-metal logic, so please use amdgpu_sriov_vf() to differentiate -4 or -4 for the ID_MAXIMUM With that addressed, this patch is : Reviewed-by: Monk Liu -邮件原件- 发件人: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] 代表 Huang Rui 发送时间: Monday, April

RE: [PATCH] drm/amdgpu: Fix firmware UCODE_ID_STORAGE issue

Reviewed-by: Xiangliang Yu > -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Trigger Huang > Sent: Monday, April 10, 2017 2:46 PM > To: amd-gfx@lists.freedesktop.org > Cc: Huang, Ray ; Huang,

Re: [PATCH] drm: Harmonize CIK ASIC support in radeon and amdgpu (v2)

On 11/04/17 08:21 AM, Felix Kuehling wrote: > Provide convenient compile time and boot time options for selecting > CIK ASIC support in either or both drivers. > > v2: git add missing files > > Signed-off-by: Felix Kuehling [...] > diff --git

答复: [PATCH] drm/amdgpu: fix to add buffer funcs check

Reviewed-by: Ken Wang 发件人: amd-gfx 代表 Huang Rui 发送时间: 2017年4月11日 10:58:21 收件人: amd-gfx@lists.freedesktop.org; Deucher, Alexander 抄送: Huang, Ray 主题: [PATCH] drm/amdgpu: fix to add

Re: [PATCH 3/3] drm/amdgpu: fix to clear ASIC INIT COMPLETE bit on resuming phase

On Mon, Apr 10, 2017 at 08:09:17PM +0800, Grazvydas Ignotas wrote: > On Mon, Apr 10, 2017 at 12:37 PM, Huang Rui wrote: > > ASIC_INIT_COMPLETE bit must be cleared during S3 resuming phase, > because VBIOS will check the bit to decide if execute ASIC_Init > posting

[PATCH 5/8] sync_file: add support for a semaphore object

From: Dave Airlie This object can be used to implement the Vulkan semaphores. The object behaviour differs from fence, in that you can replace the underlying fence, and you cannot merge semaphores. Signed-off-by: Dave Airlie ---

[PATCH 6/8] drm/syncobj: add semaphore support helpers.

From: Dave Airlie This just adds two helper interfaces to bridge the gap from drivers to sync_file for the semaphore objects. These will be used by the amdgpu driver. Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_syncobj.c | 77

[repost] drm sync objects cleaned up

This set of sync object patches should address most of the issues raised in review. The major changes: Race on destroy should be gone, Documentation fixups amdgpu internal use p instead of adev fixups My plans are to write some igt tests this week, and try to get some more review on what the API

[PATCH 2/8] sync_file: export some interfaces needed by drm sync objects.

From: Dave Airlie These are just alloc and fdget interfaces needed by the drm sync objects code. Reviewed-by: Christian König Reviewed-by: Daniel Vetter Signed-off-by: Dave Airlie ---

[PATCH 8/8] amdgpu: use sync file for shared semaphores (v2.1)

From: Dave Airlie This creates a new command submission chunk for amdgpu to add wait and signal sync objects around the submission. Sync objects are managed via the drm syncobj ioctls. The command submission interface is enhanced with two new chunks, one for semaphore

[PATCH 1/8] sync_file: add type/flags to sync file object creation.

From: Dave Airlie This allows us to create sync files with different semantics, and clearly define the interoperation between them it also provides flags to allow for tweaks on those semantics. This provides a validation interface for drivers that accept types from userspace

[PATCH 4/8] sync_file: add a mutex to protect fence and callback members. (v4)

From: Dave Airlie This patch allows the underlying fence in a sync_file to be changed or set to NULL. This isn't currently required but for Vulkan semaphores we need to be able to swap and reset the fence. In order to faciliate this, it uses rcu to protect the fence, along

[PATCH 3/8] drm: introduce sync objects as sync file objects with no fd (v2)

From: Dave Airlie Sync objects are new toplevel drm object, that have the same semantics as sync_file objects, but without requiring an fd to be consumed to support them. This patch just enables the DRM interface to create these objects, it doesn't actually provide any

[PATCH] drm/amdgpu: fix to add buffer funcs check

This patch fixes the case when buffer funcs is empty and bo evict is executing. It must double check buffer funcs, otherwise, a NULL pointer dereference kernel panic will be encountered. BUG: unable to handle kernel NULL pointer dereference at 01a4 IP: []

Re: [PATCH] drm/amdgpu:fix race condition

On 10/04/17 07:24 PM, Monk Liu wrote: > > struct drm_amdgpu_wait_cs_in { > - /** Command submission handle */ > + /* Command submission handle Any particular reason for dropping the /** comment opening? > + * handle equals 0 means none to wait for This line and the following

Re: [PATCH] drm: Harmonize CIK ASIC support in radeon and amdgpu (v2)

On 11/04/17 08:29 AM, Felix Kuehling wrote: > I tested this with Hawaii on the KFD branch and > DRM_CIK_BOTH_DEFAULT_AMDGPU. Both modules get loaded, but radeon doesn't > initialize the device. Amdgpu works with kfdtest. Did radeon print the "CIK support disabled by module param" message? --

Re: [PATCH 1/3] drm/radeon: Make CIK support in Radeon conditional (v2)

On 11/04/17 03:13 AM, Felix Kuehling wrote: > On 17-04-09 09:28 PM, Michel Dänzer wrote: >> On 10/04/17 09:56 AM, Michel Dänzer wrote: >>> On 08/04/17 05:15 AM, Felix Kuehling wrote: Advertise CIK PCI IDs only when they are not supported by amdgpu. Use the CONFIG_DRM_AMDGPU_CIK to check

Re: [PATCH] drm: Harmonize CIK ASIC support in radeon and amdgpu (v2)

I tested this with Hawaii on the KFD branch and DRM_CIK_BOTH_DEFAULT_AMDGPU. Both modules get loaded, but radeon doesn't initialize the device. Amdgpu works with kfdtest. To keep the driver code clean I only use straight-forward per-driver options in #ifdefs. The CONFIG_DRM_CIK_... options that

[PATCH] drm: Harmonize CIK ASIC support in radeon and amdgpu (v2)

Provide convenient compile time and boot time options for selecting CIK ASIC support in either or both drivers. v2: git add missing files Signed-off-by: Felix Kuehling --- drivers/gpu/drm/Kconfig | 51 ++ drivers/gpu/drm/amd/amdgpu/Kconfig

[PATCH] drm: Harmonize CIK ASIC support in radeon and amdgpu

Provide convenient compile time and boot time options for selecting CIK ASIC support in either or both drivers. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/Kconfig | 10 ++- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +

Re: [PATCH 3/3] drm/amdgpu: CIK support is no longer experimental

On 17-04-08 04:50 AM, Nicolai Hähnle wrote: > On 07.04.2017 22:15, Felix Kuehling wrote: >> Change the wording of the CONFIG_DRM_AMDGPU_CIK option to indicate >> that it's no longer experimental. >> >> Signed-off-by: Felix Kuehling >> --- >>

[PATCH 2/2] drm/amdgpu/gfx8: enable cp/rlc ints after we disable clockgating

Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[PATCH 1/2] drm/amdgpu/gfx7: enable cp/rlc ints after we disable clockgating

Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 11 +++ 1 file changed, 7 insertions(+), 4

Re: [PATCH 1/3] drm/radeon: Make CIK support in Radeon conditional (v2)

On 17-04-10 02:50 PM, Alex Deucher wrote: > On Mon, Apr 10, 2017 at 2:13 PM, Felix Kuehling > wrote: >> >> Are there any other ideas or requests, before I go spend more time on this? > > In the short term, it would probably be good to just have a tri-state option: > 1.

[PATCH 1/2] drm/amdgpu: fix spelling in header comment

Signed-off-by: Alex Deucher --- include/uapi/drm/amdgpu_drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 92262d8..95260e5 100644 --- a/include/uapi/drm/amdgpu_drm.h +++

[PATCH 2/2] drm/amdgpu: bump version number to note race fix and new fence functionality

fixed in: "drm/amdgpu:fix race condition" Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Re: [PATCH 1/3] drm/radeon: Make CIK support in Radeon conditional (v2)

On Mon, Apr 10, 2017 at 2:13 PM, Felix Kuehling wrote: > On 17-04-09 09:28 PM, Michel Dänzer wrote: >> On 10/04/17 09:56 AM, Michel Dänzer wrote: >>> On 08/04/17 05:15 AM, Felix Kuehling wrote: Advertise CIK PCI IDs only when they are not supported by amdgpu. Use

Re: [PATCH 1/3] drm/radeon: Make CIK support in Radeon conditional (v2)

On 17-04-09 09:28 PM, Michel Dänzer wrote: > On 10/04/17 09:56 AM, Michel Dänzer wrote: >> On 08/04/17 05:15 AM, Felix Kuehling wrote: >>> Advertise CIK PCI IDs only when they are not supported by amdgpu. >>> Use the CONFIG_DRM_AMDGPU_CIK to check so that a single option in >>> the kernel config

Re: [PATCH] drm/amdgpu/gfx8: move MEC doorbell range setting

Patch was Tested-by and Reviewed-by: Rex Zhu Best Regards Rex From: amd-gfx on behalf of Alex Deucher Sent: Tuesday, April 11, 2017 1:02:02 AM To: amd-gfx@lists.freedesktop.org

Re: [PATCH] drm/amdgpu/gfx8: set doorbell range for polaris as well

Patch was Tested-by and Reviewed-by: Rex Zhu Best Regards Rex From: amd-gfx on behalf of Alex Deucher Sent: Tuesday, April 11, 2017 12:51:01 AM To:

Re: Port various SOC15 drivers over to new macros

Am 10.04.2017 um 18:19 schrieb Tom St Denis: This series ports a variety of vega10 drivers over to the new SOC15 macros and introduces a pair of OFFSET ready macros to help with MC related code. Patch #1 is Reviewed-by: Christian König Patches #2-#10 are Acked-by:

[PATCH] drm/amdgpu/gfx8: move MEC doorbell range setting

It's global, not queue specific, so move it out of the kiq register init function. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 26 -- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git

[PATCH] drm/amdgpu/gfx8: set doorbell range for polaris as well

Add missing chips to the doorbell range setup. These were missed in the KIQ code. Fixes power and performance regressions with KIQ. Spotted by Rex. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +-- 1 file changed, 5 insertions(+), 2

Port various SOC15 drivers over to new macros

This series ports a variety of vega10 drivers over to the new SOC15 macros and introduces a pair of OFFSET ready macros to help with MC related code. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org

[PATCH 10/10] drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index

[PATCH 04/10] drm/amd/amdgpu: Port MMHUB over to new SOC15 macros

No functional changes. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 201 1 file changed, 100 insertions(+), 101 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

[PATCH 06/10] drm/amd/amdgpu: Port VCE 4.0 over to new SOC15 macros

Note this commit also fixes a few typos in the commented out portions which were missing closing parenthesis on the original coding style. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 176 +- 1 file changed, 88

[PATCH 03/10] drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns

Swap a couple of read/set/write patterns for WREG32_FIELD15. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

[PATCH 05/10] drm/amd/amdgpu: Cleanup mmhub read-modify-write patterns

Change read/set/write patterns into WREG32_FIELD15 calls. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

[PATCH 01/10] drm/amd/amdgpu: Add offset variant to SOC15 macros

Allows reading/writing via SOC15 macros with offset for various register banks. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h

[PATCH 02/10] drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros

No functional changes in this patch. Simply re-writing read/writes into new macros. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 182 +++ 1 file changed, 91 insertions(+), 91 deletions(-) diff --git

[PATCH 09/10] drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 44 ++ 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index

[PATCH 08/10] drm/amd/amdgpu: Port GMC v9.0 driver to new SOC15 macros

As well swap a read/set/write pattern over to WREG32_FIELD15. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

[PATCH 07/10] drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros

This patch also fixes some bugs in commented out code where parenthesis were missing on various SOC15 macros. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 206 +- 1 file changed, 103 insertions(+), 103 deletions(-)

Re: [RfC PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

On Mon, Apr 10, 2017 at 8:02 AM, Daniel Vetter wrote: > On Mon, Apr 10, 2017 at 12:12:01PM +0200, Gerd Hoffmann wrote: >> Ok, this is really a kickstart for a discussion. While working on >> graphics support for virtual machines on ppc64 (which exists in both >> little and big

Re: [RfC PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

On Mon, Apr 10, 2017 at 10:45 AM, Ilia Mirkin wrote: > On Mon, Apr 10, 2017 at 10:17 AM, Gerd Hoffmann wrote: >> Hi, >> >>> which software have you used as representative of "reality"? >> >> ppc64 (big endian) virtual machine, running with qemu stdvga &

Re: [RfC PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

On Mon, Apr 10, 2017 at 11:09 AM, Pekka Paalanen wrote: > On Mon, 10 Apr 2017 16:17:27 +0200 > Gerd Hoffmann wrote: > >> Hi, >> >> > which software have you used as representative of "reality"? >> >> ppc64 (big endian) virtual machine, running with qemu

Re: [RfC PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

On Mon, 10 Apr 2017 16:17:27 +0200 Gerd Hoffmann wrote: > Hi, > > > which software have you used as representative of "reality"? > > ppc64 (big endian) virtual machine, running with qemu stdvga & bochs-drm > driver. Xorg with modesetting driver uses DRM_FORMAT_XRGB

RE: [PATCH 3/3] drm/amdgpu: fix to clear ASIC INIT COMPLETE bit on resuming phase

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Huang Rui > Sent: Monday, April 10, 2017 5:38 AM > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander > Cc: Huang, Ray > Subject: [PATCH 3/3] drm/amdgpu: fix to clear ASIC INIT COMPLETE

RE: [PATCH xf86-video-ati] Set correct DRM event context version

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Michel Dänzer > Sent: Monday, April 10, 2017 4:38 AM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH xf86-video-ati] Set correct DRM event context version > > From: Daniel Stone

RE: [PATCH xf86-video-amdgpu] Set correct DRM event context version

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Michel Dänzer > Sent: Monday, April 10, 2017 4:38 AM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH xf86-video-amdgpu] Set correct DRM event context version > > From: Daniel Stone

RE: [PATCH] drm/amd/powerplay: set sensitivity of fan reaction to temepature changes.

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Monday, April 10, 2017 4:08 AM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH] drm/amd/powerplay: set sensitivity of fan reaction to > temepature

Re: [RfC PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

Hi, > which software have you used as representative of "reality"? ppc64 (big endian) virtual machine, running with qemu stdvga & bochs-drm driver. Xorg with modesetting driver uses DRM_FORMAT_XRGB (one and only format supported by bochs-drm), and we have to interpret that in bigendian

Re: [PATCH 3/3] drm/amdgpu: fix to clear ASIC INIT COMPLETE bit on resuming phase

On Mon, Apr 10, 2017 at 12:37 PM, Huang Rui wrote: > ASIC_INIT_COMPLETE bit must be cleared during S3 resuming phase, > because VBIOS will check the bit to decide if execute ASIC_Init > posting via kernel driver. > > Signed-off-by: Huang Rui > --- >

Re: [RfC PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

On Mon, Apr 10, 2017 at 12:12:01PM +0200, Gerd Hoffmann wrote: > Ok, this is really a kickstart for a discussion. While working on > graphics support for virtual machines on ppc64 (which exists in both > little and big endian variants) I've figured the comments in the header > file don't match

Re: [PATCH] drm/amdgpu:fix race condition

Am 10.04.2017 um 12:24 schrieb Monk Liu: sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Change-Id: Ib7a03f3cf5594deeb4ad333cc59b47a6bddfd1ad Signed-off-by: Monk Liu

[PATCH] drm/amdgpu:fix race condition

sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Change-Id: Ib7a03f3cf5594deeb4ad333cc59b47a6bddfd1ad Signed-off-by: Monk Liu ---

Re: 答复: [PATCH] drm/amdgpu:fix race condition

Am 10.04.2017 um 12:16 schrieb Liu, Monk: Is that so ? Seq is already type of "uint64_t", GCC still compiles ~0 as 0x, but not 0x ? You mean that it sign extend the value? Good point, that could be as well. I'll change to use ~0ull anyway, Yeah, that should make

答复: [PATCH] drm/amdgpu:fix race condition

Is that so ? Seq is already type of "uint64_t", GCC still compiles ~0 as 0x, but not 0x ? I'll change to use ~0ull anyway, BR Monk -邮件原件- 发件人: Christian König [mailto:deathsim...@vodafone.de] 发送时间: Monday, April 10, 2017 4:10 PM 收件人: Liu, Monk

[RfC PATCH] drm: fourcc byteorder: brings header file comments in line with reality.

Ok, this is really a kickstart for a discussion. While working on graphics support for virtual machines on ppc64 (which exists in both little and big endian variants) I've figured the comments in the header file don't match reality. They are not considered little endian (as suggested by the

Re: [PATCH xf86-video-ati] Set correct DRM event context version

On 10 April 2017 at 09:37, Michel Dänzer wrote: > From: Daniel Stone > > DRM_EVENT_CONTEXT_VERSION is the latest context version supported by > whatever version of libdrm is present. We were blindly asserting we > supported whatever version that may be,

[PATCH 2/3] drm/amdgpu: do not free fence buf when driver probes.

Fence buf needs to be used on suspend/resume phase. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

[PATCH 3/3] drm/amdgpu: fix to clear ASIC INIT COMPLETE bit on resuming phase

ASIC_INIT_COMPLETE bit must be cleared during S3 resuming phase, because VBIOS will check the bit to decide if execute ASIC_Init posting via kernel driver. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 5 -

[PATCH 1/3] drm/amd/powerplay: fix suspend error on DPM disabled

Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 9da5b0b..f73e80c 100644 ---

[PATCH xf86-video-ati] Set correct DRM event context version

From: Daniel Stone DRM_EVENT_CONTEXT_VERSION is the latest context version supported by whatever version of libdrm is present. We were blindly asserting we supported whatever version that may be, even if we actually didn't. With libdrm 2.4.78, setting a higher context

[PATCH xf86-video-amdgpu] Set correct DRM event context version

From: Daniel Stone DRM_EVENT_CONTEXT_VERSION is the latest context version supported by whatever version of libdrm is present. We were blindly asserting we supported whatever version that may be, even if we actually didn't. With libdrm 2.4.78, setting a higher context

[PATCH] drm/amd/powerplay: set sensitivity of fan reaction to temepature changes.

Change-Id: Ia7b9b3e619368d1fd3009be1352f5a587485d245 Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

Re: [PATCH] drm/amdgpu:fix race condition

Am 10.04.2017 um 09:39 schrieb Monk Liu: sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Well you are still not using ~0ull as I said. Using ~0 here will cause

[PATCH] drm/amdgpu:fix race condition

sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Change-Id: Ib7a03f3cf5594deeb4ad333cc59b47a6bddfd1ad Signed-off-by: Monk Liu ---

RE: [PATCH 3/5] drm/amdgpu/vce4: workaround multi vce engine encoding hang issue

> Am 09.04.2017 um 14:31 schrieb Xiangliang Yu: > > For SRIOV, multi vce engine will hang when encoding. Add VMHUB flush > > to workaround it, will continue to find the root cause later. > > NAK, that won't work and can cause hangs as well. > > The hang you experience could be a known issue with

答复: [PATCH] drm/amdgpu:fix race condition

>That is unnecessary the "if (seq + amdgpu_sched_jobs < cring->sequence) {" >will catch this case. But what if user land pass in seq 0 on purpose , but the latest cring->sequence value is only 3 ? Without this "if (seq == 0)" the logic seems goes to a wrong direction BR Monk -邮件原件-

答复: [PATCH] drm/amdgpu:fix race condition

Oh yeah~~ thanks -邮件原件- 发件人: Christian König [mailto:deathsim...@vodafone.de] 发送时间: Monday, April 10, 2017 3:22 PM 收件人: Liu, Monk ; amd-gfx@lists.freedesktop.org 主题: Re: [PATCH] drm/amdgpu:fix race condition Am 10.04.2017 um 09:18 schrieb Monk Liu: > sequence is

Re: [PATCH] drm/amdgpu:fix race condition

Am 10.04.2017 um 09:18 schrieb Monk Liu: sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Change-Id: Ib7a03f3cf5594deeb4ad333cc59b47a6bddfd1ad Signed-off-by: Monk Liu

[PATCH] drm/amdgpu:fix race condition

sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Change-Id: Ib7a03f3cf5594deeb4ad333cc59b47a6bddfd1ad Signed-off-by: Monk Liu ---

Re: [PATCH] drm/amdgpu: reserve space before adding a shared fence

Mhm, did you run into an actual issue or was that just from reading the code? The caller should have reserved a shared slot before calling amdgpu_vm_update_directories() and I just double checked that and we seem to do this everywhere. Regards, Christian. Am 10.04.2017 um 08:54 schrieb

[PATCH] drm/amdgpu: Fix firmware UCODE_ID_STORAGE issue

In Tonga's virtualization environment, for firmware UCODE_ID_STORAGE, there is no actual firmware data, but we still need alloc a BO and tell the BO's mc address to HW, or world switch will hang on VFs. Signed-off-by: Trigger Huang ---

[PATCH] drm/amdgpu: reserve space before adding a shared fence

Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 157ae50..55af909 100644 ---

Re: [PATCH] drm/amdgpu: Fix firmware UCODE_ID_STORAGE issue

On Mon, Apr 10, 2017 at 02:45:49PM +0800, Trigger Huang wrote: > In Tonga's virtualization environment, for firmware UCODE_ID_STORAGE, > there is no actual firmware data, but we still need alloc a BO and > tell the BO's mc address to HW, or world switch will hang on VFs. > > Signed-off-by:

Re: [PATCH 3/5] drm/amdgpu/vce4: workaround multi vce engine encoding hang issue

Am 09.04.2017 um 14:31 schrieb Xiangliang Yu: For SRIOV, multi vce engine will hang when encoding. Add VMHUB flush to workaround it, will continue to find the root cause later. NAK, that won't work and can cause hangs as well. The hang you experience could be a known issue with old libdrm, do