Re: [pull] radeon and amdgpu drm-next-4.12

[Michel Dänzer]

On 29/04/17 06:54 AM, Alex Deucher wrote:
> Hi Dave,
> 
> Fixes for 4.12.  Mostly updates for vega10 which is new for
> 4.12.  Highlights:
> - Lots of vega10 fixes
> - fix interruptable wait mixup
> - misc display fixes for radeon and amdgpu
> - misc bug fixes

[...]

> Michel Dänzer (1):
>   drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup

Maybe 'Revert "drm/amdgpu: Refactor flip into prepare submit and submit.
(v2)"' can be picked up for 4.12 as well? It's not technically a fix,
but it makes amdgpu_crtc_page_flip_target easier to grok again.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup

[Michel Dänzer]

On 28/04/17 11:12 PM, Xie, AlexBin wrote:
>> Am 28.04.2017 um 10:47 schrieb Michel Dänzer:
>>> From: Michel Dänzer 
>>>
>>> Some of these paths probably cannot be interrupted by a signal anyway.
>>> Those that can would fail to clean up things if they actually got
>>> interrupted.
>>>
>>> Signed-off-by: Michel Dänzer 
>> 
>> Reviewed-by: Christian König 
> 
> Alex X: Just a reminder: amdgpu_unpin_work_func is called by work queue.
> Signal is blocked already. un-interruptible waiting might slow thing
> down very slightly.

How so?


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: Move kiq ring lock out of virt strucure

[Liu, Shaoyun]

Thanks , Andres . 
Changed as suggested  .

Regards
Shaoyun.liu


-Original Message-
From: Andres Rodriguez [mailto:andre...@gmail.com] 
Sent: Friday, April 28, 2017 5:41 PM
To: Liu, Shaoyun; amd-gfx list (amd-gfx@lists.freedesktop.org); Deucher, 
Alexander
Cc: brahma_sw_dev
Subject: Re: Move kiq ring lock out of virt strucure

I actually have a similar patch in my tree at the moment.

Only a minor nitpick (the original base also has the same problem). Can you 
rename 'lock_ring' to  'ring_mutex'? Usually the _lock suffix is used for 
spinlock_t and _mutex is used for mutexes.

With that fixed you can add:
Reviewed-by: Andres Rodriguez 

Regards,
Andres

On 2017-04-28 05:26 PM, Liu, Shaoyun wrote:
> From c520110807459bdd3fa4d6c86b2f2ab291051ebc Mon Sep 17 00:00:00 2001
> From: Shaoyun Liu 
> Date: Fri, 28 Apr 2017 17:18:26 -0400
> Subject: [PATCH] drm/amdgpu: Move kiq ring lock out of virt structure
>
> The usage of kiq should not depend on the virtualization.
>
> Change-Id: I39a439383b0c48d8f410cd362325b8404382cd53
> Signed-off-by: Shaoyun Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 9 -  
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 -
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 ++
>  5 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index e330009..dbd0cb2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -909,6 +909,7 @@ struct amdgpu_mec {  struct amdgpu_kiq {
>   u64 eop_gpu_addr;
>   struct amdgpu_bo*eop_obj;
> + struct mutexlock_ring;
>   struct amdgpu_ring  ring;
>   struct amdgpu_irq_src   irq;
>  };
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 1363239..4da15e8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -108,7 +108,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
>   adev->cg_flags = 0;
>   adev->pg_flags = 0;
>
> - mutex_init(>virt.lock_kiq);
>   mutex_init(>virt.lock_reset);
>  }
>
> @@ -122,12 +121,12 @@ uint32_t amdgpu_virt_kiq_rreg(struct 
> amdgpu_device *adev, uint32_t reg)
>
>   BUG_ON(!ring->funcs->emit_rreg);
>
> - mutex_lock(>virt.lock_kiq);
> + mutex_lock(>lock_ring);
>   amdgpu_ring_alloc(ring, 32);
>   amdgpu_ring_emit_rreg(ring, reg);
>   amdgpu_fence_emit(ring, );
>   amdgpu_ring_commit(ring);
> - mutex_unlock(>virt.lock_kiq);
> + mutex_unlock(>lock_ring);
>
>   r = fence_wait(f, false);
>   if (r)
> @@ -148,12 +147,12 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device 
> *adev, uint32_t reg, uint32_t v)
>
>   BUG_ON(!ring->funcs->emit_wreg);
>
> - mutex_lock(>virt.lock_kiq);
> + mutex_lock(>lock_ring);
>   amdgpu_ring_alloc(ring, 32);
>   amdgpu_ring_emit_wreg(ring, reg, v);
>   amdgpu_fence_emit(ring, );
>   amdgpu_ring_commit(ring);
> - mutex_unlock(>virt.lock_kiq);
> + mutex_unlock(>lock_ring);
>
>   r = fence_wait(f, false);
>   if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index a8ed162..6f2b7df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -52,7 +52,6 @@ struct amdgpu_virt {
>   uint64_tcsa_vmid0_addr;
>   bool chained_ib_support;
>   uint32_treg_val_offs;
> - struct mutexlock_kiq;
>   struct mutexlock_reset;
>   struct amdgpu_irq_src   ack_irq;
>   struct amdgpu_irq_src   rcv_irq;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index ac64e01..d649479 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1385,6 +1385,8 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device 
> *adev,
>   struct amdgpu_kiq *kiq = >gfx.kiq;
>   int r = 0;
>
> + mutex_init(>lock_ring);
> +
>   r = amdgpu_wb_get(adev, >virt.reg_val_offs);
>   if (r)
>   return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 08daa3f..9b68d33 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -615,6 +615,8 @@ static int gfx_v9_0_kiq_init_ring(struct amdgpu_device 
> *adev,
>   struct amdgpu_kiq *kiq = >gfx.kiq;
>   int r = 0;
>
> + mutex_init(>lock_ring);
> +
>   r = amdgpu_wb_get(adev, >virt.reg_val_offs);
>   if (r)
>   return r;
> -- 1.9.1

Set invalidation reg set used in amdgpu to avoid the confliction for vega10

[Liu, Shaoyun]

Please have  a look.

Regards
Shaoyun.liu


0001-drm-amdgpu-Reserve-0-2-invalidation-reg-sets-for-non.patch
Description: 0001-drm-amdgpu-Reserve-0-2-invalidation-reg-sets-for-non.patch
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[pull] radeon and amdgpu drm-next-4.12

[Alex Deucher]

Hi Dave,

Fixes for 4.12.  Mostly updates for vega10 which is new for
4.12.  Highlights:
- Lots of vega10 fixes
- fix interruptable wait mixup
- misc display fixes for radeon and amdgpu
- misc bug fixes

The following changes since commit 73ba2d5c2bd4ecfec8fe37f20e962889b8a4c972:

  Merge tag 'drm-intel-next-fixes-2017-04-27' of 
git://anongit.freedesktop.org/git/drm-intel into drm-next (2017-04-29 05:50:27 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.12

for you to fetch changes up to c81a1a74037f61c578f6b8218b079aa434e300b4:

  drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup 
(2017-04-28 17:33:16 -0400)


Alex Deucher (3):
  drm/amdgpu: fix spelling in header comment
  drm/amdgpu: bump version number to note race fix and new fence 
functionality
  Revert "drm/amd/amdgpu: Set VCE/UVD off during late init"

Alex Xie (8):
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Real return value can be over-written when clean up
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting

Christian König (14):
  drm/amdgpu: add VMHUB to ring association
  drm/amdgpu: drop VMID per ring tracking
  drm/amdgpu: split VMID management by VMHUB
  drm/amdgpu: invalidate only the currently needed VMHUB v2
  drm/amdgpu: assign VM invalidation engine manually v2
  drm/amdgpu: allow concurrent VM flushes
  drm/amdgpu: trace the vmhub in grab_id as well
  drm/amdgpu: trace vm hub during flush as well v2
  drm/radeon: force the UVD DPB into VRAM as well
  drm/amdgpu: fix coding style and printing in amdgpu_doorbell_init
  drm/amdgpu: fix amdgpu_vm_clear_freed v2
  drm/amdgpu: fix amdgpu_ttm_bo_eviction_valuable
  drm/amdgpu: fix VM clearing in amdgpu_gem_object_close
  drm/amdgpu: remove unused and mostly unimplemented CGS functions v2

Chunming Zhou (6):
  drm/amdgpu: add gtt print like vram when dump mm table V2
  drm/amdgpu: increase gtt size to 3GB by default v2
  drm/amdgpu: fix no-vmid job
  drm/amdgpu: fix gpu reset crash
  drm/amdgpu: fix NULL pointer error
  drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2

Daniel Wang (2):
  drm/amdgpu/psp: skip loading SDMA/RLCG under SRIOV VF
  drm/amdgpu/vce4: fix a PSP loading VCE issue

Evan Quan (1):
  drm/amdgpu: update smu9 driver interface

Frank Min (7):
  drm/amdgpu/vce4: update VCE initialization sequence for SRIOV
  drm/amdgpu/vce4: enable ring & ib test for sriov
  drm/amdgpu/vce4: move mm table constructions functions into mmsch header 
file
  drm/amdgpu/uvd7: add sriov uvd initialization sequences
  drm/amdgpu/uvd7: add uvd doorbell initialization for sriov
  drm/amdgpu/uvd7: add UVD hw init sequences for sriov
  drm/amdgpu/soc15: enable UVD code path for sriov

Huang Rui (14):
  drm/amdgpu: split psp tmr init function
  drm/amdgpu: add psp firmware private memory
  drm/amdgpu: use private memory to store psp firmware data
  drm/amdgpu: split psp asd function
  drm/amdgpu: split psp ring init function
  drm/amdgpu: add hw_start and non-psp firmware loading into resume
  drm/amd/powerplay: fix suspend error on DPM disabled
  drm/amdgpu: do not free fence buf when driver probes.
  drm/amdgpu: fix to clear ASIC INIT COMPLETE bit on resuming phase
  drm/amdgpu: fix to add buffer funcs check
  drm/amdgpu: fix dead lock if any ip block resume failed in s3
  drm/amdgpu: fix to print incorrect wptr address
  drm/ttm: cleanup unuse ret value
  drm/amd/powerplay: add error message to remind user updating firmware

Junwei Zhang (3):
  drm/amdgpu: fix double_offchip_lds_buf for gfx v6
  drm/amdgpu: export more gpu info for gfx9
  drm/amdgpu: bump version for exporting gpu info for gfx9

Mario Kleiner (3):
  drm/amdgpu: Add missing lb_vblank_lead_lines setup to DCE-6 path.
  drm/radeon: Avoid overflows/divide-by-zero in latency_watermark 
calculations.
  drm/radeon: Make display watermark calculations more accurate

Michel Dänzer (1):
  drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup

Monk Liu (1):
  drm/amdgpu:fix race condition

Pan Bian (2):
  drm/radeon: check return value of radeon_ring_lock
  drm/radeon: check return value of radeon_fence_emit

Pixel Ding (1):
  drm/amdgpu/virt: don't check VALID bit for FLR completion message

Rex Zhu (16):
  drm/amd/powerplay: align with VBIOS to support new AVFS structure
  drm/amdgpu: Remove redundant itermediate return val in sdma_v4_0.c
  

Re: Move kiq ring lock out of virt strucure

[Andres Rodriguez]

I actually have a similar patch in my tree at the moment.

Only a minor nitpick (the original base also has the same problem). Can 
you rename 'lock_ring' to  'ring_mutex'? Usually the _lock suffix is 
used for spinlock_t and _mutex is used for mutexes.


With that fixed you can add:
Reviewed-by: Andres Rodriguez 

Regards,
Andres

On 2017-04-28 05:26 PM, Liu, Shaoyun wrote:

From c520110807459bdd3fa4d6c86b2f2ab291051ebc Mon Sep 17 00:00:00 2001
From: Shaoyun Liu 
Date: Fri, 28 Apr 2017 17:18:26 -0400
Subject: [PATCH] drm/amdgpu: Move kiq ring lock out of virt structure

The usage of kiq should not depend on the virtualization.

Change-Id: I39a439383b0c48d8f410cd362325b8404382cd53
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 9 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 -
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 ++
 5 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e330009..dbd0cb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -909,6 +909,7 @@ struct amdgpu_mec {
 struct amdgpu_kiq {
u64 eop_gpu_addr;
struct amdgpu_bo*eop_obj;
+   struct mutexlock_ring;
struct amdgpu_ring  ring;
struct amdgpu_irq_src   irq;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 1363239..4da15e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -108,7 +108,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
adev->cg_flags = 0;
adev->pg_flags = 0;

-   mutex_init(>virt.lock_kiq);
mutex_init(>virt.lock_reset);
 }

@@ -122,12 +121,12 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, 
uint32_t reg)

BUG_ON(!ring->funcs->emit_rreg);

-   mutex_lock(>virt.lock_kiq);
+   mutex_lock(>lock_ring);
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_rreg(ring, reg);
amdgpu_fence_emit(ring, );
amdgpu_ring_commit(ring);
-   mutex_unlock(>virt.lock_kiq);
+   mutex_unlock(>lock_ring);

r = fence_wait(f, false);
if (r)
@@ -148,12 +147,12 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, 
uint32_t reg, uint32_t v)

BUG_ON(!ring->funcs->emit_wreg);

-   mutex_lock(>virt.lock_kiq);
+   mutex_lock(>lock_ring);
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_wreg(ring, reg, v);
amdgpu_fence_emit(ring, );
amdgpu_ring_commit(ring);
-   mutex_unlock(>virt.lock_kiq);
+   mutex_unlock(>lock_ring);

r = fence_wait(f, false);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index a8ed162..6f2b7df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -52,7 +52,6 @@ struct amdgpu_virt {
uint64_tcsa_vmid0_addr;
bool chained_ib_support;
uint32_treg_val_offs;
-   struct mutexlock_kiq;
struct mutexlock_reset;
struct amdgpu_irq_src   ack_irq;
struct amdgpu_irq_src   rcv_irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index ac64e01..d649479 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1385,6 +1385,8 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device 
*adev,
struct amdgpu_kiq *kiq = >gfx.kiq;
int r = 0;

+   mutex_init(>lock_ring);
+
r = amdgpu_wb_get(adev, >virt.reg_val_offs);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 08daa3f..9b68d33 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -615,6 +615,8 @@ static int gfx_v9_0_kiq_init_ring(struct amdgpu_device 
*adev,
struct amdgpu_kiq *kiq = >gfx.kiq;
int r = 0;

+   mutex_init(>lock_ring);
+
r = amdgpu_wb_get(adev, >virt.reg_val_offs);
if (r)
return r;
-- 1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Move kiq ring lock out of virt strucure

[Liu, Shaoyun]

Please have  a look.

Regards
Shaoyun.liu


0001-drm-amdgpu-Move-kiq-ring-lock-out-of-virt-structure.patch
Description: 0001-drm-amdgpu-Move-kiq-ring-lock-out-of-virt-structure.patch
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH umr] Avoid opening the DRM file by default

[Alex Deucher]

On Thu, Apr 27, 2017 at 12:41 PM, Tom St Denis  wrote:
> Opening the DRM file (/dev/dri/card%d) triggers all sorts of KMD
> work to happen which is not useful if the KMD is hung or not working.
>
> Since --top is the only user of the file currently we simply defer
> opening it until --top is invoked.
>
> Signed-off-by: Tom St Denis 

Reviewed-by: Alex Deucher 

> ---
>  src/app/top.c  | 7 +++
>  src/lib/discover.c | 3 +--
>  2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/src/app/top.c b/src/app/top.c
> index 364180eb70f6..a4d3aa8e699d 100644
> --- a/src/app/top.c
> +++ b/src/app/top.c
> @@ -933,8 +933,15 @@ void umr_top(struct umr_asic *asic)
> time_t tt;
> uint64_t ts;
> char hostname[64] = { 0 };
> +   char fname[64];
> pthread_t sensor_thread;
>
> +   // open drm file if not already open
> +   if (asic->fd.drm < 0) {
> +   snprintf(fname, sizeof(fname)-1, "/dev/dri/card%d", 
> asic->instance);
> +   asic->fd.drm = open(fname, O_RDWR);
> +   }
> +
> if (getenv("HOSTNAME")) strcpy(hostname, getenv("HOSTNAME"));
>
> // init stats
> diff --git a/src/lib/discover.c b/src/lib/discover.c
> index d561efafe4d4..c9c2f74a4818 100644
> --- a/src/lib/discover.c
> +++ b/src/lib/discover.c
> @@ -127,8 +127,7 @@ struct umr_asic *umr_discover_asic(struct umr_options 
> *options)
> asic->fd.vram = open(fname, O_RDWR);
> snprintf(fname, sizeof(fname)-1, 
> "/sys/kernel/debug/dri/%d/amdgpu_gpr", asic->instance);
> asic->fd.gpr = open(fname, O_RDWR);
> -   snprintf(fname, sizeof(fname)-1, "/dev/dri/card%d", 
> asic->instance);
> -   asic->fd.drm = open(fname, O_RDWR);
> +   asic->fd.drm = -1; // default to closed
> // if appending to the fd list remember to update 
> close_asic() and discover_by_did()...
>
> if (options->use_pci) {
> --
> 2.12.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 3/3] drm/amd/powerplay: implement stop dpm task for vega10.

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, April 28, 2017 1:20 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 3/3] drm/amd/powerplay: implement stop dpm task for
> vega10.
> 
> Change-Id: I19202f1e54ce6a1b8b54aacbc0d42dbba7605662
> Signed-off-by: Rex Zhu 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 97
> ++
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 23 +
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h |  1 +
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c   |  2 +-
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h   |  1 +
>  5 files changed, 123 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 5e3e89b..68eae52 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2420,6 +2420,26 @@ static int
> vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
>   return 0;
>  }
> 
> +static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
> +{
> + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr-
> >backend);
> +
> + if (data->smu_features[GNLD_THERMAL].supported) {
> + if (!data->smu_features[GNLD_THERMAL].enabled)
> + pr_info("THERMAL Feature Already disabled!");
> +
> + PP_ASSERT_WITH_CODE(
> + !vega10_enable_smc_features(hwmgr-
> >smumgr,
> + false,
> + data-
> >smu_features[GNLD_THERMAL].smu_feature_bitmap),
> + "disable THERMAL Feature Failed!",
> + return -1);
> + data->smu_features[GNLD_THERMAL].enabled = false;
> + }
> +
> + return 0;
> +}
> +
>  static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
>  {
>   struct vega10_hwmgr *data =
> @@ -2498,6 +2518,37 @@ static int
> vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
>   return 0;
>  }
> 
> +static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
> +{
> + struct vega10_hwmgr *data =
> + (struct vega10_hwmgr *)(hwmgr->backend);
> + uint32_t i, feature_mask = 0;
> +
> +
> + if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
> +
>   PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr-
> >smumgr,
> + true, data-
> >smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
> + "Attempt to Enable LED DPM feature Failed!", return -
> EINVAL);
> + data->smu_features[GNLD_LED_DISPLAY].enabled = true;
> + }
> +
> + for (i = 0; i < GNLD_DPM_MAX; i++) {
> + if (data->smu_features[i].smu_feature_bitmap & bitmap) {
> + if (data->smu_features[i].supported) {
> + if (data->smu_features[i].enabled) {
> + feature_mask |= data-
> >smu_features[i].
> +
>   smu_feature_bitmap;
> + data->smu_features[i].enabled =
> false;
> + }
> + }
> + }
> + }
> +
> + vega10_enable_smc_features(hwmgr->smumgr, false,
> feature_mask);
> +
> + return 0;
> +}
> +
>  /**
>   * @brief Tell SMC to enabled the supported DPMs.
>   *
> @@ -4356,11 +4407,55 @@ static int vega10_check_states_equal(struct
> pp_hwmgr *hwmgr,
>   return is_update_required;
>  }
> 
> +static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
> +{
> + int tmp_result, result = 0;
> +
> + tmp_result = (vega10_is_dpm_running(hwmgr)) ? 0 : -1;
> + PP_ASSERT_WITH_CODE(tmp_result == 0,
> + "DPM is not running right now, no need to disable
> DPM!",
> + return 0);
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_ThermalController))
> + vega10_disable_thermal_protection(hwmgr);
> +
> + tmp_result = vega10_disable_power_containment(hwmgr);
> + PP_ASSERT_WITH_CODE((tmp_result == 0),
> + "Failed to disable power containment!", result =
> tmp_result);
> +
> + tmp_result = vega10_avfs_enable(hwmgr, false);
> + PP_ASSERT_WITH_CODE((tmp_result == 0),
> + "Failed to disable AVFS!", result = tmp_result);
> +
> + tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
> + PP_ASSERT_WITH_CODE((tmp_result == 0),
> + "Failed to stop DPM!", result = tmp_result);
> +
> + return result;
> +}
> +
> +static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
> +{
> + struct vega10_hwmgr *data = (struct 

RE: [PATCH] drm/amdgpu: add cu info wave_front_size

[Deucher, Alexander]

> -Original Message-
> From: Junwei Zhang [mailto:jerry.zh...@amd.com]
> Sent: Thursday, April 27, 2017 11:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Wang, Ken; Zhang, Jerry
> Subject: [PATCH] drm/amdgpu: add cu info wave_front_size
> 
> missed that for gfx v9 info export
> 
> Signed-off-by: Junwei Zhang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 503010a..e330009 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -986,6 +986,7 @@ struct amdgpu_gfx_config {
>  struct amdgpu_cu_info {
>   uint32_t number; /* total active CU number */
>   uint32_t ao_cu_mask;
> + uint32_t wave_front_size;
>   uint32_t bitmap[4][4];
>  };
> 
> --
> 1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: CZ EDC param and support

[Panariti, David]

Actually, the attachment was an oversight.
It's easier for me to attach, open the attachment and then delete the 
attachment.
I got only 2/3 this time.
I've gotten a comment that inline patches are preferred.

Sorry for the inconvenience.

davep

From: Koenig, Christian
Sent: Friday, April 28, 2017 4:06 AM
To: Panariti, David ; gpudriverdevsupport 
; amd-gfx@lists.freedesktop.org
Subject: Re: CZ EDC param and support

You somehow messed up the attachment.

Instead of individual files everything is squashed together as all-edc.patch.

Please fix that otherwise proper review won't be possible.

Christian.

Am 28.04.2017 um 00:13 schrieb Panariti, David:
The changes in the workarounds function use DRM_INFO rather than DRM_DEBUG 
because CZs with EDC are often used in embedded environments and any info can 
be useful especially in the case of an intermittent problem.

>From e1ce383592c275b58ad95bd80b5479af8c1f9dae Mon Sep 17 00:00:00 2001
From: David Panariti 
Date: Fri, 14 Apr 2017 13:41:52 -0400
Subject: [PATCH 1/3] drm/amdgpu: Moved gfx_v8_0_select_se_sh() in lieu of
re-redundant prototype.

Will be needed for the rest of the EDC workarounds patch.

Change-Id: Ie586ab38a69e98a91c6cb5747e285ce8bfdd1c86
Signed-off-by: David Panariti 

---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 46 +--
1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 2ff5f19..27b57cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1500,6 +1500,29 @@ static int gfx_v8_0_kiq_init(struct amdgpu_device *adev)
   return 0;
}
+static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
+   u32 se_num, u32 
sh_num, u32 instance)
+{
+ u32 data;
+
+ if (instance == 0x)
+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);
+
+ if (se_num == 0x)
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_INDEX, se_num);
+
+ if (sh_num == 0x)
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_BROADCAST_WRITES, 1);
+ else
+ data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_INDEX, sh_num);
+
+ WREG32(mmGRBM_GFX_INDEX, data);
+}
+
static const u32 vgpr_init_compute_shader[] =
{
   0x7e000209, 0x7e020208,
@@ -3556,29 +3579,6 @@ static void gfx_v8_0_tiling_mode_table_init(struct 
amdgpu_device *adev)
   }
}
-static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
-u32 se_num, 
u32 sh_num, u32 instance)
-{
-  u32 data;
-
-  if (instance == 0x)
-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);
-
-  if (se_num == 0x)
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SE_INDEX, se_num);
-
-  if (sh_num == 0x)
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_BROADCAST_WRITES, 1);
-  else
-  data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 
SH_INDEX, sh_num);
-
-  WREG32(mmGRBM_GFX_INDEX, data);
-}
-
static u32 gfx_v8_0_create_bitmask(u32 bit_width)
{
   return (u32)((1ULL << bit_width) - 1);
--
2.7.4


>From 38fac8cab73dbc07e0ee7599b52106bc09dd32ea Mon Sep 17 00:00:00 2001
From: David Panariti 
Date: Mon, 24 Apr 2017 11:05:45 -0400
Subject: [PATCH 2/3] drm/amdgpu: Complete Carrizo EDC (Error Detection and
Correction) workarounds.

The workarounds are unconditionally performed on CZs with EDC enabled.
EDC detects uncorrected ECC errors and uses data poisoning to prevent
corrupted compute results from being used (read).
EDC enabled CZs are often used in embedded environments.

Change-Id: I84c261785329beeb797f11efbe0ec35790f2996c
Signed-off-by: David Panariti 

---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 148 --
1 file 

Re: [PATCH] drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup

[Xie, AlexBin]

Am 28.04.2017 um 10:47 schrieb Michel Dänzer:
> From: Michel Dänzer 
>
> Some of these paths probably cannot be interrupted by a signal anyway.
> Those that can would fail to clean up things if they actually got
> interrupted.
>
> Signed-off-by: Michel Dänzer 

Reviewed-by: Christian König 

Alex X: Just a reminder: amdgpu_unpin_work_func is called by work queue.
Signal is blocked already. un-interruptible waiting might slow thing down very 
slightly.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c|  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c   |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c  |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  |  6 +++---
>   drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  |  6 +++---
>   drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   |  6 +++---
>   drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   |  6 +++---
>   drivers/gpu/drm/amd/amdgpu/dce_virtual.c|  2 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 +++---
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   | 10 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  8 
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  8 
>   16 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 771a6aae58d6..af64448a565c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -123,7 +123,7 @@ static void amdgpu_unpin_work_func(struct work_struct 
> *__work)
>int r;
>
>/* unpin of the old buffer */
> - r = amdgpu_bo_reserve(work->old_abo, false);
> + r = amdgpu_bo_reserve(work->old_abo, true);
>if (likely(r == 0)) {
>r = amdgpu_bo_unpin(work->old_abo);
>if (unlikely(r != 0)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> index 9dea2f661f1d..e869e60994ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> @@ -113,7 +113,7 @@ static void amdgpufb_destroy_pinned_object(struct 
> drm_gem_object *gobj)
>struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
>int ret;
>
> - ret = amdgpu_bo_reserve(abo, false);
> + ret = amdgpu_bo_reserve(abo, true);
>if (likely(ret == 0)) {
>amdgpu_bo_kunmap(abo);
>amdgpu_bo_unpin(abo);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index 6d691abe889c..e7406ce7093c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -183,7 +183,7 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device 
> *adev)
>if (adev->gart.robj == NULL) {
>return;
>}
> - r = amdgpu_bo_reserve(adev->gart.robj, false);
> + r = amdgpu_bo_reserve(adev->gart.robj, true);
>if (likely(r == 0)) {
>amdgpu_bo_kunmap(adev->gart.robj);
>amdgpu_bo_unpin(adev->gart.robj);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index ec5b1bc0e428..d40b8ac745cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -819,7 +819,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
>
>if (amdgpu_sriov_vf(adev)) {
>/* TODO: how to handle reserve failure */
> - BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
> + BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
>amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
>fpriv->vm.csa_bo_va = NULL;
>amdgpu_bo_unreserve(adev->virt.csa_obj);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> index 3826d5aea0a6..6bdc866570ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> @@ -113,7 +113,7 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj)
>struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
>int ret = 0;
>
> - ret = amdgpu_bo_reserve(bo, false);
> + ret = amdgpu_bo_reserve(bo, true);
>if (unlikely(ret != 0))
>return;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
> index 7b56d9988aba..de4ebcf4ac2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
> @@ -130,7 +130,7 @@ int amdgpu_sa_bo_manager_suspend(struct amdgpu_device 

[PATCH umr] Add 'no_kernel' option

[Tom St Denis]

This flag allows umr to perform some operations it would normally
need the kernel for in userspace.  This is useful if the kernel driver
is misbehaving.  Don't use this on a healthy system as it could invoke
race conditions.

This flag enables userland activities such as

- reading/writing MMIO registers (with bank selection)
- reading wave status and SGPR registers

Signed-off-by: Tom St Denis 
---
 doc/umr.1 |  5 +++
 src/app/main.c|  5 ++-
 src/app/scan.c|  6 +++-
 src/app/set_bit.c |  4 +++
 src/app/set_reg.c |  4 +++
 src/lib/discover.c| 49 +--
 src/lib/mmio.c| 57 ++-
 src/lib/read_sgpr.c   | 58 +---
 src/lib/wave_status.c | 92 ++-
 src/umr.h | 23 +++--
 10 files changed, 252 insertions(+), 51 deletions(-)

diff --git a/doc/umr.1 b/doc/umr.1
index 90be2d6316ce..50ce03330b5c 100644
--- a/doc/umr.1
+++ b/doc/umr.1
@@ -138,6 +138,11 @@ separated strings.
  Enable colour output for --top command, scales from blue, green, yellow, 
to red.  Also
  accepted is 'use_color'.
 
+.B no_kernel
+ Disable using kernel files to access the device.  Implies ''use_pci''.  
This is meant to
+ be used only if the KMD is hung or otherwise not working correctly.  
Using it on live systems
+ may result in race conditions.
+
 .SH "Notes"
 
 - The "Waves" field in the DRM section of --top only works if GFX PG has been 
disabled.  Otherwise,
diff --git a/src/app/main.c b/src/app/main.c
index 96a790cbec7c..1d9ef9edceb8 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -109,6 +109,9 @@ static void parse_options(char *str)
options.quiet = 1;
} else if (!strcmp(option, "follow_ib")) {
options.follow_ib = 1;
+   } else if (!strcmp(option, "no_kernel")) {
+   options.no_kernel = 1;
+   options.use_pci = 1;
} else {
printf("error: Unknown option [%s]\n", option);
exit(EXIT_FAILURE);
@@ -413,7 +416,7 @@ int main(int argc, char **argv)
"\n\t\tRead 'size' bytes (in hex) from a given address (in hex) to 
stdout. Optionally"
"\n\t\tspecify the VMID (in decimal) treating the address as a virtual 
address instead.\n"
 "\n\t--option -O [,,...]\n\t\tEnable various flags: risky, 
bits, bitsfull, empty_log, follow, named, many,"
-   "\n\t\tuse_pci, use_colour, read_smc, quiet.\n"
+   "\n\t\tuse_pci, use_colour, read_smc, quiet, no_kernel.\n"
 "\n\n", UMR_BUILD_VER, UMR_BUILD_REV);
exit(EXIT_SUCCESS);
} else {
diff --git a/src/app/scan.c b/src/app/scan.c
index e91fbd4649c8..3320509f8be2 100644
--- a/src/app/scan.c
+++ b/src/app/scan.c
@@ -88,7 +88,11 @@ int umr_scan_asic(struct umr_asic *asic, char *asicname, 
char *ipname, char *reg
goto error;
}
} else if 
(asic->blocks[i]->regs[j].type == REG_MMIO) {
-   
asic->blocks[i]->regs[j].value = asic->pci.mem[asic->blocks[i]->regs[j].addr];
+   if (options.use_bank && 
options.no_kernel)
+   
umr_grbm_select_index(asic, options.se_bank, options.sh_bank, 
options.instance_bank);
+   
asic->blocks[i]->regs[j].value = umr_read_reg(asic, 
asic->blocks[i]->regs[j].addr * 4);
+   if (options.use_bank && 
options.no_kernel)
+   
umr_grbm_select_index(asic, 0x, 0x, 0x);
}
if (regname[0]) {
if (options.named)
diff --git a/src/app/set_bit.c b/src/app/set_bit.c
index bed7ee858b6a..49f6c4750b8a 100644
--- a/src/app/set_bit.c
+++ b/src/app/set_bit.c
@@ -96,9 +96,13 @@ int umr_set_register_bit(struct umr_asic *asic, char 
*regpath, char *regvalue)

}
}
} else if 
(asic->blocks[i]->regs[j].type == REG_MMIO) {
+   if 
(options.use_bank && options.no_kernel)
+   
umr_grbm_select_index(asic, options.se_bank, options.sh_bank, 

Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format

[Gerd Hoffmann]

  Hi,

> > So just not using the swapping indeed looks like the only sensible
> > option.  Which in turn implies there is no BGRA support for dumb
> > bos.  Hmm, I can see the problem.  Userspace expectation appears to be
> > that ADDFB configures a native endian framebuffer, which the driver
> > simply can't do on bigendian.
> 
> ... with pre-R600 GPUs.

Sure.

> > So, what can/should the driver do here?  Throw errors for ADDFB and
> > force userspace to use ADDFB2?  From a design point of view the best
> > option, but in the other hand I suspect that could break the xorg radeon
> > driver ...
> 
> Yes, it would.

> One thing we could do is provide a way for userspace to query the
> effective format(s) as seen by the GPU and/or CPU.

We already have almost no testing on bigendian.  I doubt adding generic
interfaces specifically to handle this case is going to work because
most userspace will simply not implement that correctly (or at all).

Having support for this in the radeon ioctls might work, because only
radeon kernel + xorg driver have to get things right then.  But I
suspect we already have that.  You've mentioned elsewhere in the thread
that the xorg driver doesn't turn on byteswapping, so the ability to
configure that seems to be somewhere in the API ...

> It might also make sense for the radeon driver to set the
> RADEON_TILING_SWAP_{16,32}BIT flags for dumb BOs.

That could work.  But I guess someone with test hardware needs to try,
to make sure we don't miss corner cases here.

cheers,
  Gerd

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu: add interface for reserve/unserve vmid

[zhoucm1]

anyone could give a quick review?

Regards,
David Zhou

On 2017年04月28日 17:22, Chunming Zhou wrote:

Change-Id: If533576eb8a65bd019a3480d6fe2a64f23e3c944
Signed-off-by: Chunming Zhou 
---
  amdgpu/amdgpu.h| 13 +
  amdgpu/amdgpu_cs.c | 30 ++
  2 files changed, 43 insertions(+)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 4772006..7afade0 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1626,6 +1626,19 @@ int amdgpu_cs_signal_sem(amdgpu_device_handle dev,
 uint32_t ip_instance,
 uint32_t ring,
 amdgpu_sem_handle sem);
+/**
+ *  reserve vmid for this process
+ *
+ * \param   dev- [in] Device handle. See #amdgpu_device_initialize()
+ */
+int amdgpu_cs_reserved_vmid(amdgpu_device_handle dev);
+
+/**
+ *  unreserve vmid for this process
+ *
+ * \param   dev- [in] Device handle. See #amdgpu_device_initialize()
+ */
+int amdgpu_cs_unreserved_vmid(amdgpu_device_handle dev);
  
  /**

   *  wait sem
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 62b595a..df362ee 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -754,3 +754,33 @@ int amdgpu_cs_destroy_sem(amdgpu_device_handle dev,
  
  	return 0;

  }
+
+int amdgpu_cs_unreserved_vmid(amdgpu_device_handle dev)
+{
+   union drm_amdgpu_vm args;
+   int r;
+
+   if (NULL == dev)
+   return -EINVAL;
+
+   /* Create the context */
+   memset(, 0, sizeof(args));
+   args.in.op = AMDGPU_VM_OP_UNRESERVE_VMID;
+   r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, , sizeof(args));
+   return r;
+}
+
+int amdgpu_cs_reserved_vmid(amdgpu_device_handle dev)
+{
+   union drm_amdgpu_vm args;
+   int r;
+
+   if (NULL == dev)
+   return -EINVAL;
+
+   /* Create the context */
+   memset(, 0, sizeof(args));
+   args.in.op = AMDGPU_VM_OP_RESERVE_VMID;
+   r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, , sizeof(args));
+   return r;
+}


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] amdgpu: add interface for reserve/unserve vmid

[Chunming Zhou]

Change-Id: If533576eb8a65bd019a3480d6fe2a64f23e3c944
Signed-off-by: Chunming Zhou 
---
 amdgpu/amdgpu.h| 13 +
 amdgpu/amdgpu_cs.c | 30 ++
 2 files changed, 43 insertions(+)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 4772006..7afade0 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1626,6 +1626,19 @@ int amdgpu_cs_signal_sem(amdgpu_device_handle dev,
 uint32_t ip_instance,
 uint32_t ring,
 amdgpu_sem_handle sem);
+/**
+ *  reserve vmid for this process
+ *
+ * \param   dev- [in] Device handle. See #amdgpu_device_initialize()
+ */
+int amdgpu_cs_reserved_vmid(amdgpu_device_handle dev);
+
+/**
+ *  unreserve vmid for this process
+ *
+ * \param   dev- [in] Device handle. See #amdgpu_device_initialize()
+ */
+int amdgpu_cs_unreserved_vmid(amdgpu_device_handle dev);
 
 /**
  *  wait sem
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 62b595a..df362ee 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -754,3 +754,33 @@ int amdgpu_cs_destroy_sem(amdgpu_device_handle dev,
 
return 0;
 }
+
+int amdgpu_cs_unreserved_vmid(amdgpu_device_handle dev)
+{
+   union drm_amdgpu_vm args;
+   int r;
+
+   if (NULL == dev)
+   return -EINVAL;
+
+   /* Create the context */
+   memset(, 0, sizeof(args));
+   args.in.op = AMDGPU_VM_OP_UNRESERVE_VMID;
+   r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, , sizeof(args));
+   return r;
+}
+
+int amdgpu_cs_reserved_vmid(amdgpu_device_handle dev)
+{
+   union drm_amdgpu_vm args;
+   int r;
+
+   if (NULL == dev)
+   return -EINVAL;
+
+   /* Create the context */
+   memset(, 0, sizeof(args));
+   args.in.op = AMDGPU_VM_OP_RESERVE_VMID;
+   r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, , sizeof(args));
+   return r;
+}
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] Revert "drm/amdgpu: Refactor flip into prepare submit and submit. (v2)"

[Christian König]

Am 28.04.2017 um 10:48 schrieb Michel Dänzer:

On 28/04/17 05:23 PM, Christian König wrote:

Am 28.04.2017 um 08:59 schrieb Michel Dänzer:

On 27/04/17 07:04 PM, Christian König wrote:

Am 27.04.2017 um 10:18 schrieb Michel Dänzer:

From: Michel Dänzer 

This reverts commit cb341a319f7e66f879d69af929c3dadfc1a8f31e.

The purpose of the refactor was for amdgpu_crtc_prepare/submit_flip to
be used by the DC code, but that's no longer the case.

Signed-off-by: Michel Dänzer 

[...]


+pflip_cleanup:
+if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {

Well here we explicitly shouldn't use an interruptible wait, otherwise
we would keep the BO pinned.

Makes sense, but this patch just reverts another commit and moves this
code unchanged.

Actually, after rebasing to current amd-staging-4.9, it already looks
like you suggested. Can I get your Reviewed-by for that?


Yes, feel free to add my rb.

Christian.





I'll send a follow-up patch which fixes this (possibly also in other
error paths).

Sounds good, and feel free to CC me as well.

Done.




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup

[Christian König]

Am 28.04.2017 um 10:47 schrieb Michel Dänzer:

From: Michel Dänzer 

Some of these paths probably cannot be interrupted by a signal anyway.
Those that can would fail to clean up things if they actually got
interrupted.

Signed-off-by: Michel Dänzer 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  |  6 +++---
  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  |  6 +++---
  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   |  6 +++---
  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   |  6 +++---
  drivers/gpu/drm/amd/amdgpu/dce_virtual.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 +++---
  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   | 10 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  8 
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  8 
  16 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 771a6aae58d6..af64448a565c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -123,7 +123,7 @@ static void amdgpu_unpin_work_func(struct work_struct 
*__work)
int r;
  
  	/* unpin of the old buffer */

-   r = amdgpu_bo_reserve(work->old_abo, false);
+   r = amdgpu_bo_reserve(work->old_abo, true);
if (likely(r == 0)) {
r = amdgpu_bo_unpin(work->old_abo);
if (unlikely(r != 0)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 9dea2f661f1d..e869e60994ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -113,7 +113,7 @@ static void amdgpufb_destroy_pinned_object(struct 
drm_gem_object *gobj)
struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
int ret;
  
-	ret = amdgpu_bo_reserve(abo, false);

+   ret = amdgpu_bo_reserve(abo, true);
if (likely(ret == 0)) {
amdgpu_bo_kunmap(abo);
amdgpu_bo_unpin(abo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 6d691abe889c..e7406ce7093c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -183,7 +183,7 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device 
*adev)
if (adev->gart.robj == NULL) {
return;
}
-   r = amdgpu_bo_reserve(adev->gart.robj, false);
+   r = amdgpu_bo_reserve(adev->gart.robj, true);
if (likely(r == 0)) {
amdgpu_bo_kunmap(adev->gart.robj);
amdgpu_bo_unpin(adev->gart.robj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index ec5b1bc0e428..d40b8ac745cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -819,7 +819,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
  
  	if (amdgpu_sriov_vf(adev)) {

/* TODO: how to handle reserve failure */
-   BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
+   BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
fpriv->vm.csa_bo_va = NULL;
amdgpu_bo_unreserve(adev->virt.csa_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 3826d5aea0a6..6bdc866570ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -113,7 +113,7 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj)
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
int ret = 0;
  
-	ret = amdgpu_bo_reserve(bo, false);

+   ret = amdgpu_bo_reserve(bo, true);
if (unlikely(ret != 0))
return;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c

index 7b56d9988aba..de4ebcf4ac2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -130,7 +130,7 @@ int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
return -EINVAL;
}
  
-	r = amdgpu_bo_reserve(sa_manager->bo, false);

+   r = amdgpu_bo_reserve(sa_manager->bo, true);
if (!r) {
amdgpu_bo_kunmap(sa_manager->bo);
amdgpu_bo_unpin(sa_manager->bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 

Re: [PATCH] Revert "drm/amdgpu: Refactor flip into prepare submit and submit. (v2)"

[Michel Dänzer]

On 28/04/17 05:23 PM, Christian König wrote:
> Am 28.04.2017 um 08:59 schrieb Michel Dänzer:
>> On 27/04/17 07:04 PM, Christian König wrote:
>>> Am 27.04.2017 um 10:18 schrieb Michel Dänzer:
 From: Michel Dänzer 

 This reverts commit cb341a319f7e66f879d69af929c3dadfc1a8f31e.

 The purpose of the refactor was for amdgpu_crtc_prepare/submit_flip to
 be used by the DC code, but that's no longer the case.

 Signed-off-by: Michel Dänzer 
>> [...]
>>
 +pflip_cleanup:
 +if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
>>> Well here we explicitly shouldn't use an interruptible wait, otherwise
>>> we would keep the BO pinned.
>> Makes sense, but this patch just reverts another commit and moves this
>> code unchanged.

Actually, after rebasing to current amd-staging-4.9, it already looks
like you suggested. Can I get your Reviewed-by for that?


>> I'll send a follow-up patch which fixes this (possibly also in other
>> error paths).
> 
> Sounds good, and feel free to CC me as well.

Done.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup

[Michel Dänzer]

From: Michel Dänzer 

Some of these paths probably cannot be interrupted by a signal anyway.
Those that can would fail to clean up things if they actually got
interrupted.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  |  6 +++---
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  |  6 +++---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   |  6 +++---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   |  6 +++---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 +++---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   | 10 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  8 
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  8 
 16 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 771a6aae58d6..af64448a565c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -123,7 +123,7 @@ static void amdgpu_unpin_work_func(struct work_struct 
*__work)
int r;
 
/* unpin of the old buffer */
-   r = amdgpu_bo_reserve(work->old_abo, false);
+   r = amdgpu_bo_reserve(work->old_abo, true);
if (likely(r == 0)) {
r = amdgpu_bo_unpin(work->old_abo);
if (unlikely(r != 0)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 9dea2f661f1d..e869e60994ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -113,7 +113,7 @@ static void amdgpufb_destroy_pinned_object(struct 
drm_gem_object *gobj)
struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
int ret;
 
-   ret = amdgpu_bo_reserve(abo, false);
+   ret = amdgpu_bo_reserve(abo, true);
if (likely(ret == 0)) {
amdgpu_bo_kunmap(abo);
amdgpu_bo_unpin(abo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 6d691abe889c..e7406ce7093c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -183,7 +183,7 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device 
*adev)
if (adev->gart.robj == NULL) {
return;
}
-   r = amdgpu_bo_reserve(adev->gart.robj, false);
+   r = amdgpu_bo_reserve(adev->gart.robj, true);
if (likely(r == 0)) {
amdgpu_bo_kunmap(adev->gart.robj);
amdgpu_bo_unpin(adev->gart.robj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index ec5b1bc0e428..d40b8ac745cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -819,7 +819,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
 
if (amdgpu_sriov_vf(adev)) {
/* TODO: how to handle reserve failure */
-   BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
+   BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
fpriv->vm.csa_bo_va = NULL;
amdgpu_bo_unreserve(adev->virt.csa_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 3826d5aea0a6..6bdc866570ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -113,7 +113,7 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj)
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
int ret = 0;
 
-   ret = amdgpu_bo_reserve(bo, false);
+   ret = amdgpu_bo_reserve(bo, true);
if (unlikely(ret != 0))
return;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 7b56d9988aba..de4ebcf4ac2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -130,7 +130,7 @@ int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
return -EINVAL;
}
 
-   r = amdgpu_bo_reserve(sa_manager->bo, false);
+   r = amdgpu_bo_reserve(sa_manager->bo, true);
if (!r) {
amdgpu_bo_kunmap(sa_manager->bo);
amdgpu_bo_unpin(sa_manager->bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 58873cf027e8..11c6c4494e0a 100644
--- 

Re: [PATCH] drm/amdgpu: add cu info wave_front_size

[Zhang, Jerry (Junwei)]

Sorry about that missing, since it's originally created on amdgpu-pro stack, 
which is a bit different about cu info definition.


I will keep an eye on those patches squashing when Alex prepares the patch 
merging.

Jerry

On 04/28/2017 04:20 PM, Christian König wrote:

Do I get it right that the branch doesn't compile without that?

If yes please add a comment in the commit message so that Alex has a chance of
squashing this into the original one during upstreaming.

Either way the patch is Reviewed-by: Christian König 
as well.

Regards,
Christian.

Am 28.04.2017 um 05:20 schrieb Wang, Ken:


Reviewed-by: Ken Wang 

---
*From:* Junwei Zhang 
*Sent:* Friday, April 28, 2017 11:10:46 AM
*To:* amd-gfx@lists.freedesktop.org
*Cc:* Deucher, Alexander; Wang, Ken; Zhang, Jerry
*Subject:* [PATCH] drm/amdgpu: add cu info wave_front_size
missed that for gfx v9 info export

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 503010a..e330009 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -986,6 +986,7 @@ struct amdgpu_gfx_config {
 struct amdgpu_cu_info {
 uint32_t number; /* total active CU number */
 uint32_t ao_cu_mask;
+   uint32_t wave_front_size;
 uint32_t bitmap[4][4];
 };

--
1.9.1



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2

[zhoucm1]

Agree, but libdrm doesn't allow concurrent submissions from same 
context, like protection 'pthread_mutex_lock(>sequence_mutex);' 
in amdgpu_cs_submit_one.


Regards,
David Zhou
On 2017年04月28日 16:15, Christian König wrote:
Indeed, but after a bit of thinking I've found another problem with 
that patch.


When two threads are pushing jobs into the same scheduler context we 
don't guarantee correct execution order any more!


Before that patch it was handled by the exclusiveness we had because 
of reserving the VM page tables, but now nothing prevents us from 
calling amd_sched_entity_push_job() in nondeterministic order.


In other words we need an additional lock in amdgpu_ctx_ring or 
something like that.


Regards,
Christian.

Am 28.04.2017 um 04:51 schrieb Zhang, Jerry:

Nice catch!
Reviewed-by: Junwei Zhang 

Regards,
Jerry (Junwei Zhang)

Linux Base Graphics
SRDC Software Development
_



-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On 
Behalf Of

Chunming Zhou
Sent: Friday, April 28, 2017 10:46
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH] drm/amdgpu: fix deadlock of reservation between cs 
and gpu

reset v2

the case could happen when gpu reset:
1. when gpu reset, cs can be continue until sw queue is full, then 
push job will

wait with holding pd reservation.
2. gpu_reset routine will also need pd reservation to restore page 
table from

their shadow.
3. cs is waiting for gpu_reset complete, but gpu reset is waiting 
for cs releases

reservation.

v2: handle amdgpu_cs_submit error path.

Change-Id: I0f66d04b2bef3433035109623c8a5c5992c84202
Signed-off-by: Chunming Zhou 
Reviewed-by: Christian König 
Reviewed-by: Junwei Zhang 
Reviewed-by: Monk Liu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 26168df..699f5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1074,6 +1074,7 @@ static int amdgpu_cs_submit(struct 
amdgpu_cs_parser

*p,
  cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
  job->uf_sequence = cs->out.handle;
  amdgpu_job_free_resources(job);
+amdgpu_cs_parser_fini(p, 0, true);

  trace_amdgpu_cs_ioctl(job);
  amd_sched_entity_push_job(>base);
@@ -1129,7 +1130,10 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void
*data, struct drm_file *filp)
  goto out;

  r = amdgpu_cs_submit(, cs);
+if (r)
+goto out;

+return 0;
  out:
  amdgpu_cs_parser_fini(, r, reserved_buffers);
  return r;
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx





___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [RFC] drm/amd/amdgpu: get rid of else branch

[Christian König]

Am 27.04.2017 um 18:17 schrieb Nikola Pajkovsky:

This is super simple elimination of else branch and I should
probably even use unlikely in

if (ring->count_dw < count_dw) {

However, amdgpu_ring_write() has similar if condition, but does not
return after DRM_ERROR and it looks suspicious. On error, we still
adding v to ring and keeping count_dw-- below zero.

if (ring->count_dw <= 0)
DRM_ERROR("amdgpu: writing more dwords to the ring than 
expected!\n");
ring->ring[ring->wptr++] = v;
ring->wptr &= ring->ptr_mask;
ring->count_dw--;

I can obviously be totaly wrong. Hmm?


That's just choosing the lesser evil.

When we write more DW to the ring than expected it is possible (but not 
likely) that we override stuff on the ring buffer which is still 
executed by the command processor leading to a possible CP crash.


But when we completely drop the write the commands in the ring buffer 
will certainly be invalid and so the CP will certainly crash sooner or 
later.


Please add the unlikely() as well and then send out the patch with a 
signed-of-by line and I will be happy to push it into our upstream branch.


Regards,
Christian.



8<8<8<8<8<8<8<8<8<
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c1b913541739..c6f4f874ea68 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1596,28 +1596,29 @@ static inline void amdgpu_ring_write_multiple(struct 
amdgpu_ring *ring, void *sr
  
  	if (ring->count_dw < count_dw) {

DRM_ERROR("amdgpu: writing more dwords to the ring than 
expected!\n");
-   } else {
-   occupied = ring->wptr & ring->ptr_mask;
-   dst = (void *)>ring[occupied];
-   chunk1 = ring->ptr_mask + 1 - occupied;
-   chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
-   chunk2 = count_dw - chunk1;
-   chunk1 <<= 2;
-   chunk2 <<= 2;
-
-   if (chunk1)
-   memcpy(dst, src, chunk1);
-
-   if (chunk2) {
-   src += chunk1;
-   dst = (void *)ring->ring;
-   memcpy(dst, src, chunk2);
-   }
-
-   ring->wptr += count_dw;
-   ring->wptr &= ring->ptr_mask;
-   ring->count_dw -= count_dw;
+   return;
}
+
+   occupied = ring->wptr & ring->ptr_mask;
+   dst = (void *)>ring[occupied];
+   chunk1 = ring->ptr_mask + 1 - occupied;
+   chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
+   chunk2 = count_dw - chunk1;
+   chunk1 <<= 2;
+   chunk2 <<= 2;
+
+   if (chunk1)
+   memcpy(dst, src, chunk1);
+
+   if (chunk2) {
+   src += chunk1;
+   dst = (void *)ring->ring;
+   memcpy(dst, src, chunk2);
+   }
+
+   ring->wptr += count_dw;
+   ring->wptr &= ring->ptr_mask;
+   ring->count_dw -= count_dw;
  }
  
  static inline struct amdgpu_sdma_instance *



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] Revert "drm/amdgpu: Refactor flip into prepare submit and submit. (v2)"

[Christian König]

Am 28.04.2017 um 08:59 schrieb Michel Dänzer:

On 27/04/17 07:04 PM, Christian König wrote:

Am 27.04.2017 um 10:18 schrieb Michel Dänzer:

From: Michel Dänzer 

This reverts commit cb341a319f7e66f879d69af929c3dadfc1a8f31e.

The purpose of the refactor was for amdgpu_crtc_prepare/submit_flip to
be used by the DC code, but that's no longer the case.

Signed-off-by: Michel Dänzer 

[...]


+pflip_cleanup:
+if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {

Well here we explicitly shouldn't use an interruptible wait, otherwise
we would keep the BO pinned.

Makes sense, but this patch just reverts another commit and moves this
code unchanged. I'll send a follow-up patch which fixes this (possibly
also in other error paths).


Sounds good, and feel free to CC me as well.

Christian.

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: add cu info wave_front_size

[Christian König]

Do I get it right that the branch doesn't compile without that?

If yes please add a comment in the commit message so that Alex has a 
chance of squashing this into the original one during upstreaming.


Either way the patch is Reviewed-by: Christian König 
 as well.


Regards,
Christian.

Am 28.04.2017 um 05:20 schrieb Wang, Ken:


Reviewed-by: Ken Wang 


*From:* Junwei Zhang 
*Sent:* Friday, April 28, 2017 11:10:46 AM
*To:* amd-gfx@lists.freedesktop.org
*Cc:* Deucher, Alexander; Wang, Ken; Zhang, Jerry
*Subject:* [PATCH] drm/amdgpu: add cu info wave_front_size
missed that for gfx v9 info export

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 503010a..e330009 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -986,6 +986,7 @@ struct amdgpu_gfx_config {
 struct amdgpu_cu_info {
 uint32_t number; /* total active CU number */
 uint32_t ao_cu_mask;
+   uint32_t wave_front_size;
 uint32_t bitmap[4][4];
 };

--
1.9.1



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2

[Christian König]

Indeed, but after a bit of thinking I've found another problem with that 
patch.


When two threads are pushing jobs into the same scheduler context we 
don't guarantee correct execution order any more!


Before that patch it was handled by the exclusiveness we had because of 
reserving the VM page tables, but now nothing prevents us from calling 
amd_sched_entity_push_job() in nondeterministic order.


In other words we need an additional lock in amdgpu_ctx_ring or 
something like that.


Regards,
Christian.

Am 28.04.2017 um 04:51 schrieb Zhang, Jerry:

Nice catch!
Reviewed-by: Junwei Zhang 

Regards,
Jerry (Junwei Zhang)

Linux Base Graphics
SRDC Software Development
_



-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chunming Zhou
Sent: Friday, April 28, 2017 10:46
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH] drm/amdgpu: fix deadlock of reservation between cs and gpu
reset v2

the case could happen when gpu reset:
1. when gpu reset, cs can be continue until sw queue is full, then push job will
wait with holding pd reservation.
2. gpu_reset routine will also need pd reservation to restore page table from
their shadow.
3. cs is waiting for gpu_reset complete, but gpu reset is waiting for cs 
releases
reservation.

v2: handle amdgpu_cs_submit error path.

Change-Id: I0f66d04b2bef3433035109623c8a5c5992c84202
Signed-off-by: Chunming Zhou 
Reviewed-by: Christian König 
Reviewed-by: Junwei Zhang 
Reviewed-by: Monk Liu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 26168df..699f5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1074,6 +1074,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser
*p,
cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
job->uf_sequence = cs->out.handle;
amdgpu_job_free_resources(job);
+   amdgpu_cs_parser_fini(p, 0, true);

trace_amdgpu_cs_ioctl(job);
amd_sched_entity_push_job(>base);
@@ -1129,7 +1130,10 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void
*data, struct drm_file *filp)
goto out;

r = amdgpu_cs_submit(, cs);
+   if (r)
+   goto out;

+   return 0;
  out:
amdgpu_cs_parser_fini(, r, reserved_buffers);
return r;
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: CZ EDC param and support

[Christian König]

You somehow messed up the attachment.

Instead of individual files everything is squashed together as 
all-edc.patch.


Please fix that otherwise proper review won't be possible.

Christian.

Am 28.04.2017 um 00:13 schrieb Panariti, David:


The changes in the workarounds function use DRM_INFO rather than 
DRM_DEBUG because CZs with EDC are often used in embedded environments 
and any info can be useful especially in the case of an intermittent 
problem.


From e1ce383592c275b58ad95bd80b5479af8c1f9dae Mon Sep 17 00:00:00 2001

From: David Panariti 

Date: Fri, 14 Apr 2017 13:41:52 -0400

Subject: [PATCH 1/3] drm/amdgpu: Moved gfx_v8_0_select_se_sh() in lieu of

re-redundant prototype.

Will be needed for the rest of the EDC workarounds patch.

Change-Id: Ie586ab38a69e98a91c6cb5747e285ce8bfdd1c86

Signed-off-by: David Panariti 

---

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 46 
+--


1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c


index 2ff5f19..27b57cb 100644

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

@@ -1500,6 +1500,29 @@ static int gfx_v8_0_kiq_init(struct 
amdgpu_device *adev)


   return 0;

}

+static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,

+   u32 se_num, u32 sh_num, u32 instance)

+{

+ u32 data;

+

+ if (instance == 0x)

+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);


+ else

+ data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);


+

+ if (se_num == 0x)

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);


+ else

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_INDEX, se_num);


+

+ if (sh_num == 0x)

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);


+ else

+ data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_INDEX, sh_num);


+

+ WREG32(mmGRBM_GFX_INDEX, data);

+}

+

static const u32 vgpr_init_compute_shader[] =

{

   0x7e000209, 0x7e020208,

@@ -3556,29 +3579,6 @@ static void 
gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)


   }

}

-static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,

-   u32 se_num, u32 sh_num, u32 instance)

-{

-  u32 data;

-

-  if (instance == 0x)

-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_BROADCAST_WRITES, 1);


-  else

-  data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 
INSTANCE_INDEX, instance);


-

-  if (se_num == 0x)

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);


-  else

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SE_INDEX, se_num);


-

-  if (sh_num == 0x)

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);


-  else

-  data = REG_SET_FIELD(data, 
GRBM_GFX_INDEX, SH_INDEX, sh_num);


-

-  WREG32(mmGRBM_GFX_INDEX, data);

-}

-

static u32 gfx_v8_0_create_bitmask(u32 bit_width)

{

   return (u32)((1ULL << bit_width) - 1);

--

2.7.4

From 38fac8cab73dbc07e0ee7599b52106bc09dd32ea Mon Sep 17 00:00:00 2001

From: David Panariti 

Date: Mon, 24 Apr 2017 11:05:45 -0400

Subject: [PATCH 2/3] drm/amdgpu: Complete Carrizo EDC (Error Detection and

Correction) workarounds.

The workarounds are unconditionally performed on CZs with EDC enabled.

EDC detects uncorrected ECC errors and uses data poisoning to prevent

corrupted compute results from being used (read).

EDC enabled CZs are often used in embedded environments.

Change-Id: I84c261785329beeb797f11efbe0ec35790f2996c

Signed-off-by: David Panariti 

---

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 148 
--


1 file changed, 106 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c


index 27b57cb..2f5bf5f 100644

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

@@ -1645,35 +1645,92 @@ static const u32 sgpr2_init_regs[] =

   mmCOMPUTE_USER_DATA_9, 0xedcedc09,

};

-static const u32 sec_ded_counter_registers[] =

-{

-  mmCPC_EDC_ATC_CNT,

-  mmCPC_EDC_SCRATCH_CNT,

-  mmCPC_EDC_UCODE_CNT,

-  mmCPF_EDC_ATC_CNT,

-  mmCPF_EDC_ROQ_CNT,

-

Re: [PATCH] Revert "drm/amdgpu: Refactor flip into prepare submit and submit. (v2)"

[Michel Dänzer]

On 27/04/17 07:04 PM, Christian König wrote:
> Am 27.04.2017 um 10:18 schrieb Michel Dänzer:
>> From: Michel Dänzer 
>>
>> This reverts commit cb341a319f7e66f879d69af929c3dadfc1a8f31e.
>>
>> The purpose of the refactor was for amdgpu_crtc_prepare/submit_flip to
>> be used by the DC code, but that's no longer the case.
>>
>> Signed-off-by: Michel Dänzer 

[...]

>> +pflip_cleanup:
>> +if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
> 
> Well here we explicitly shouldn't use an interruptible wait, otherwise
> we would keep the BO pinned.

Makes sense, but this patch just reverts another commit and moves this
code unchanged. I'll send a follow-up patch which fixes this (possibly
also in other error paths).


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx