Re: [RFC] Problems with SRBM select on KIQ

We ran into a similar problem when we played with priorities on KFD queues. You can't change an MQD of a currently mapped queue. To change a queue priority we need to unmap it, update the MQD, and then map it again. I wonder if a queue can change its own priority by using register write commands

Re: [RFC] Problems with SRBM select on KIQ

On Fri, May 5, 2017 at 1:10 PM, Andres Rodriguez wrote: > Hey Everyone, > > On one of the previous comments for this series I received feedback that > the register programming should be done through the KIQ. This series has > the relevant changes. > > However, register writes

[PATCH 4/8] drm/amdgpu: convert kiq ring_mutex to a spinlock

First step towards enabling kiq register operations from an interrupt handler Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +- 2 files changed, 6 insertions(+), 6 deletions(-)

[PATCH 1/8] drm/amdgpu: add parameter to allocate high priority contexts v9

Add a new context creation parameter to express a global context priority. The priority ranking in descending order is as follows: * AMDGPU_CTX_PRIORITY_HIGH * AMDGPU_CTX_PRIORITY_NORMAL * AMDGPU_CTX_PRIORITY_LOW The driver will attempt to schedule work to the hardware according to the

[PATCH 7/8] drm/amdgpu/vi: add mechanism to edit the kiq srbm window

The kiq's srbm window is independent of the MMIO srbm window. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 34

[PATCH 6/8] drm/amdgpu: add macro for asynchronous KIQ register writes

Add WREG32_KIQ_ASYNC() to allow for a caller to perform a register write without waiting for the result to be commited. This allows us to queue register writes from a context that cannot sleep. It may also be useful for long sequences of register writes performed through the kiq. Where only the

[PATCH 5/8] drm/amdgpu: add option to force register ops through kiq

Use the [WR]REG32_KIQ() macros when a register operation should go through the kiq. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 -- 2 files changed, 7 insertions(+), 2 deletions(-)

[PATCH 8/8] drm/amdgpu: implement ring set_priority for gfx_v8 compute v7

Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over other queues on the same pipe. Multiple queues on a pipe are timesliced so this gives us full precedence over other queues. Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the wave as follows: 0x2:

[PATCH 2/8] drm/amdgpu: add framework for HW specific priority settings v6

Add an initial framework for changing the HW priorities of rings. The framework allows requesting priority changes for the lifetime of an amdgpu_job. After the job completes the priority will decay to the next lowest priority for which a request is still valid. A new ring function set_priority()

[PATCH 3/8] drm/amdgpu: separate KIQ operations from amdgpu_virt

KIQ is now used for baremetal compute initialization. Since it is no longer compute specific, move the KIQ reg opts to a more general location. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

[RFC] Problems with SRBM select on KIQ

Hey Everyone, On one of the previous comments for this series I received feedback that the register programming should be done through the KIQ. This series has the relevant changes. However, register writes that require an srbm_select are not working correctly. The effect is as if the write

[PATCH 1/2] drm/amdgpu/atomfirmware: add function to update engine hang status

Update the scratch reg for when the engine is hung. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 13 + drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 ++ 2 files changed, 15 insertions(+) diff --git

[PATCH 2/2] drm/amdgpu/soc15: use atomfirmware for setting bios scratch for reset

Need to use the atomfirmware interface rather than atombios since soc15 is atomfirmware based. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

RE: [PATCH 5/5] drm/amd/powerplay: refine pwm1_enable callback functions on CI.

Patch 2 is missing your signed-off-by. With that fixed, the series is: Reviewed-by: Alex Deucher From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Zhu, Rex Sent: Friday, May 05, 2017 8:43 AM To: amd-gfx@lists.freedesktop.org Cc: Zhu, Rex

RE: [PATCH 2/6] drm/amdgpu: reset GDW, GWS and OA software copy to update them

can you check if vega the same -Original Message- From: Yu, Xiangliang Sent: Friday, May 5, 2017 5:18 PM To: Ding, Pixel ; Liu, Monk ; amd-gfx@lists.freedesktop.org Subject: RE: [PATCH 2/6] drm/amdgpu: reset GDW, GWS and OA software copy to

Re: [PATCH 1/2] drm/amdgpu: fix ring0 failed on firepro card

On Fri, May 5, 2017 at 2:45 AM, Chunming Zhou wrote: > the root cause is vram content is lost completely after pci reset. > > Change-Id: I012cea984702894410b0f05149fd017bb62b624c > Signed-off-by: Chunming Zhou Let's see if it makes sense to change the

[PATCH 2/2] drm/amd/display: make dc_commit_surfaces_to_stream() re-entrant

From: Shirish S dc_commit_surfaces_to_stream() function currently is handle's only one plane at a time. This will not work if multiple planes have to be set to a crtc. The functionality of dc_commit_surfaces_to_stream() with this patch is slit into 1. Accumulate and

[PATCH 0/2] DC Linux Patches May 5, 2017

Missed these patches the other day. This is some of the recent work to hook up underlay support. Shirish S (2): drm/amd/display: update the YUV plane offsets drm/amd/display: make dc_commit_surfaces_to_stream() re-entrant .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 85

[PATCH 1/2] drm/amd/display: update the YUV plane offsets

From: Shirish S This patch updates the planes default offsets to the appropriate ones, and aligns the pitch to 64 bits. BUG=SWDEV-119421 TEST=Boots to UI on jadeite TEST= plane_test --format AR24 --size 500x50 -p --format YV12 --size 500x500 plane_test --format AR24

Fw: [PATCH 1/5] drm/amdgpu: add amd fan ctrl mode define.

Change-Id: Ida8f8168d9600503146b5140ea47c913733888cf Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/include/amd_shared.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index

Fw: [PATCH 3/5] drm/amd/powerplay: refine pwm1_enable callback functions on vega10.

Change-Id: Ib8681558cabab99da804d1d10987aca63435b1e5 Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 43 -- .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 1 + 2 files changed, 25 insertions(+), 19 deletions(-) diff

Fw: [PATCH 4/5] drm/amd/powerplay: refine pwm1_enable callback functions on vi.

Signed-off-by: Rex Zhu Change-Id: I72d61851630e5d4ff5b3236ca33abac6f5b200c6 --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 35 -- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 9 +++--- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h |

Fw: [PATCH 5/5] drm/amd/powerplay: refine pwm1_enable callback functions on CI.

Change-Id: Ieb05cfa95e4072357e18f631ab71780de0688008 Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 27 +++ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c

Re: [PATCH 2/2] drm/amdgpu: print when gpu reset successed

Reviewed-by: Christian König Am 05.05.2017 um 09:47 schrieb He, Hongbo: Reviewed-by: Roger.He -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Chunming Zhou Sent: Friday, May 05, 2017 2:46 PM

Re: [PATCH] drm/amdgpu: extend lock range for race condition when gpu reset

Reviewed-by: Christian König Am 05.05.2017 um 09:33 schrieb zhoucm1: Reviewed-by: Chunming Zhou On 2017年05月05日 15:22, Roger.He wrote: to cover below case: 1. A task gart bind/unbind but not add to adev->gtt_list yet 2. at this time gpu reset,

Re: [PATCH] drm/amdgpu/gfx9: move define to header file

Am 05.05.2017 um 05:34 schrieb Zhang, Jerry (Junwei): On 05/04/2017 10:33 PM, Alex Deucher wrote: rather than defining it locally. Signed-off-by: Alex Deucher Reviewed-by: Junwei Zhang Reviewed-by: Christian König

RE: [PATCH 2/2] drm/amdgpu: print when gpu reset successed

Reviewed-by: Roger.He -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Chunming Zhou Sent: Friday, May 05, 2017 2:46 PM To: amd-gfx@lists.freedesktop.org Cc: Zhou, David(ChunMing) Subject: [PATCH 2/2] drm/amdgpu: print when

Re: [PATCH] drm/amdgpu: extend lock range for race condition when gpu reset

Reviewed-by: Chunming Zhou On 2017年05月05日 15:22, Roger.He wrote: to cover below case: 1. A task gart bind/unbind but not add to adev->gtt_list yet 2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list Change-Id: Ifb4360e3b68624f2be67fa82100623cf4c451873

[PATCH] drm/amdgpu: extend lock range for race condition when gpu reset

to cover below case: 1. A task gart bind/unbind but not add to adev->gtt_list yet 2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list Change-Id: Ifb4360e3b68624f2be67fa82100623cf4c451873 Signed-off-by: Roger.He --- drivers/gpu/drm/amd/amdgpu/amdgpu.h

RE: [PATCH 4/6] drm/amdgpu/psp: Do not load asd for SRIOV

> -Original Message- > From: Huang Rui [mailto:ray.hu...@amd.com] > Sent: Friday, May 05, 2017 2:47 PM > To: Yu, Xiangliang > Cc: amd-gfx@lists.freedesktop.org; Wang, Daniel(Xiaowei) > > Subject: Re: [PATCH 4/6] drm/amdgpu/psp: Do not load

Re: [PATCH 4/6] drm/amdgpu/psp: Do not load asd for SRIOV

On Thu, May 04, 2017 at 02:36:35PM +0800, Xiangliang Yu wrote: > If psp version doesn't match asd version, asd loading will be > failed. Add workaround to bypass it for sriov. > > Signed-off-by: Daniel Wang > Signed-off-by: Xiangliang Yu > --- >

[PATCH 1/2] drm/amdgpu: fix ring0 failed on firepro card

the root cause is vram content is lost completely after pci reset. Change-Id: I012cea984702894410b0f05149fd017bb62b624c Signed-off-by: Chunming Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 57 ++ 1 file changed, 50 insertions(+), 7