Re: [PATCH 01/12] drm/amdgpu: move ring helpers to amdgpu_ring.h

Thank you Christian! The series is Acked-by: Felix Kuehling Minor nit-pick in patch 6: I spotted 4-space indentation in amdgpu_ttm_backend_bind. I'm looking at patches 5 and 9 more closely, because I'll need to make similar changes to the KFD IPC copy code. Regards,

[PATCH 3/5] drm/amdgpu/atombios: add function for whether we need asic_init

Check the atom scratch registers to see if asic_init is complete or not. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 10 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 1 + 2 files changed, 11 insertions(+) diff --git

[PATCH 1/5] drm/amdgpu/atombios: use bios_scratch_reg_offset for atombios

Align with the atomfirmware code. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

[PATCH 4/5] drm/amdgpu: check scratch registers to see if we need post

Rather than checking the CONGIG_MEMSIZE register as that may not be reliable on some APUs. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git

[PATCH 2/5] drm/amdgpu: unify some atombios/atomfirmware scratch reg functions

Now that we use a pointer to the scratch reg start offset, most of the functions were duplicated. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 35 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 4 ---

[PATCH libdrm 2/2] radeon: use asic id table to get chipset name

Change-Id: I24b6624789d1a9dc0fd3a446b0e6f21ed5183ff2 Signed-off-by: Samuel Li --- radeon/Makefile.am | 6 +++ radeon/Makefile.sources | 6 ++- radeon/radeon_asic_id.c | 106 radeon/radeon_asic_id.h | 37

[PATCH libdrm 1/2] util: move some files to an ASIC neutral directory.

Change-Id: Iac1c4870253e8b8860a61b7cf175e7a25cc95921 Signed-off-by: Samuel Li --- Makefile.sources | 10 +- amdgpu/Makefile.am | 3 +- amdgpu/Makefile.sources | 7 +- amdgpu/amdgpu_asic_id.c | 219 --- amdgpu/amdgpu_device.c | 7

Re: [PATCH 12/12] drm/amdgpu: add gtt_sys_limit

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > Limit the size of the GART table for the system domain. > > This saves us a bunch of visible VRAM, but also limitates the maximum BO size > we can swap out.

Re: [PATCH 11/12] drm/amdgpu: remove maximum BO size limitation.

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > We can finally remove this now. > > Signed-off-by: Christian König Woot! Reviewed-by: Alex Deucher > ---

Re: [PATCH 10/12] drm/amdgpu: stop mapping BOs to GTT

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > No need to map BOs to GTT on eviction and intermediate transfers any more. > > Signed-off-by: Christian König Acked-by: Alex Deucher

Re: [PATCH 09/12] drm/amdgpu: use the GTT windows for BO moves

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > This way we don't need to map the full BO at a time any more. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher

Re: [PATCH 08/12] drm/amdgpu: add amdgpu_gart_map function

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > This allows us to write the mapped PTEs into > an IB instead of the table directly. > > Signed-off-by: Christian König Reviewed-by:

Re: [PATCH 07/12] drm/amdgpu: reserve the first 2x2MB of GART

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > We want to use them as remap address space. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c |

Re: [PATCH 06/12] drm/amdgpu: bind BOs with GTT space allocated directly

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > This avoids binding them later on. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16

RE: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

Hi , Christian The new code actually will not use the fence function , it just need a memory that expose both CPU and GPU address . Do you really want to add the wrap functions that just expose the CPU and GPU address in this case ? Regards Shaoyun.liu -Original Message- From:

Re: [PATCH 05/12] drm/amdgpu: bind BOs to TTM only once

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > No need to do this on every round. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher > --- >

Re: [PATCH 04/12] drm/amdgpu: add vm_needs_flush parameter to amdgpu_copy_buffer

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > This allows us to flush the system VM here. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher

Re: [PATCH 03/12] drm/amdgpu: allow flushing VMID0 before IB execution as well

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > This allows us to queue IBs which needs an up to date system domain as well. > > Signed-off-by: Christian König Reviewed-by: Alex

Re: [PATCH 01/12] drm/amdgpu: move ring helpers to amdgpu_ring.h

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > Keep them where they belong. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher > --- >

Re: [PATCH 02/12] drm/amdgpu: fix amdgpu_ring_write_multiple

On Fri, Jun 30, 2017 at 7:22 AM, Christian König wrote: > From: Christian König > > Overwriting still used ring content has a low probability to cause > problems, not writing at all has 100% probability to cause problems. > > Signed-off-by:

[PATCH 3/3] drm/amdgpu: Use polling for KIQ read/write register

Change-Id: I87762bfc9903401ac06892bed10efa1767c15025 Signed-off-by: Shaoyun Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 47 +++- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

[PATCH 1/3] drm/amdgpu: Use spin_lock instead of mutex for KIQ

KIQ read/write register will be called in atomic context so mutex can not be used Change-Id: Ifa14293b3cdfcf74cd7930a4058154d0a7d7f97c Signed-off-by: Shaoyun Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-

[PATCH] drm/amdgpu/acp: properly handle powergating in hw_fini

Stoney does not have powergating, so make the powergating teardown dependent on whether we have a genpd structure. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff

[PATCH 2/3] drm/amdgpu: Add wrap function for fence driver to expose cpu and gpu address

Change-Id: I5c6267253bfe5507a8821a482cf378852946 Signed-off-by: Shaoyun Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

[PATCH RFC 2/2] drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM

When a BO is moved to VRAM, clear AMDGPU_BO_FLAG_CPU_ACCESS. This allows it to potentially later move to invisible VRAM if the CPU does not access it again. Setting the CPU_ACCESS flag in amdgpu_fault_reserve_notify() also means that we can remove the loop to restrict lpfn to the end of visible

[PATCH RFC 1/2] drm/amdgpu: Add AMDGPU_BO_FLAG_CPU_ACCESS

For userspace BO allocations, replace AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED with a new AMDGPU_BO_FLAG_CPU_ACCESS flag. This flag will be used to indicate that a BO should currently be CPU accessible. Unlike the CPU_ACCESS_REQUIRED flag, it is meant to be an ephemeral rather than a permanent

[PATCH RFC 0/2] Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

> On 30/06/17 03:59 PM, Christian König wrote: >> Am 30.06.2017 um 08:51 schrieb Michel Dänzer: >>> We can deal with that internally in the kernel, while fixing the >>> existing flag for userspace. >> And as I said, NAK to that approach. I'm not going to add a >> CPU_ACCESS_REALLY_REQUIRED flag in

RE: [PATCH xf86-video-ati] Use pRADEONEnt->fd exclusively for the DRM file descriptor

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Michel Dänzer > Sent: Friday, June 30, 2017 5:20 AM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH xf86-video-ati] Use pRADEONEnt->fd exclusively for the > DRM file descriptor > >

RE: [PATCH] /drm/amd/amdgpu: move get memory type function from early init to sw init

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Jim Qu > Sent: Friday, June 30, 2017 1:32 AM > To: amd-gfx@lists.freedesktop.org > Cc: Qu, Jim > Subject: [PATCH] /drm/amd/amdgpu: move get memory type function from > early init to sw init

Re: [PATCH] amdgpu: Set cik/si_support to 1 by default if radeon isn't built

Hi Michel, MODULE_PARM_DESC is "used to document arguments that the module can take. It takes two parameters: a variable name and a free form string describing that variable" I think we should avoid changing document when config change. How about changing it to something like the following

Re: [PATCH] drm/amdgpu/cgs: always set reference clock in mode_info

Am 30.06.2017 um 16:05 schrieb Alex Deucher: It's relevent regardless of whether there are displays enabled. Fixes garbage values for ref clock in powerplay leading to incorrect fan speed reporting when displays are disabled. bug: https://bugs.freedesktop.org/show_bug.cgi?id=101653

[PATCH] drm/amdgpu/cgs: always set reference clock in mode_info

It's relevent regardless of whether there are displays enabled. Fixes garbage values for ref clock in powerplay leading to incorrect fan speed reporting when displays are disabled. bug: https://bugs.freedesktop.org/show_bug.cgi?id=101653 Signed-off-by: Alex Deucher

Re: [PATCH 4/8] ASoC: AMD: added condition checks for CZ specific code

On Thu, Jun 29, 2017 at 12:58:02PM +, Mukunda, Vijendar wrote: > -Original Message- > From: Mark Brown [mailto:broo...@kernel.org] > Sent: Wednesday, June 28, 2017 11:36 PM > To: Alex Deucher Please fix your mail client to quote mails in a more normal fashion, this looks pretty

Re: Resizeable PCI BAR support V5

Hi Dieter, thanks a lot for testing that. But I think my poor little FUJITSU PRIMERGY TX150 S7, Xeon X3470 (Nehalem), PCIe 2.0, 24 GB is to old for this stuff... Well, actually you only need to figure out how to enable a PCIe window above the 4GB limit. Could be that the BIOS supports this

Re: [PATCH 4/5] drm/amdgpu: Set/clear CPU_ACCESS_REQUIRED flag on page fault and CS

Am 30.06.2017 um 14:39 schrieb Daniel Vetter: On Fri, Jun 30, 2017 at 08:47:27AM +0200, Christian König wrote: Am 30.06.2017 um 04:24 schrieb Michel Dänzer: On 29/06/17 07:05 PM, Daniel Vetter wrote: On Thu, Jun 29, 2017 at 06:58:05PM +0900, Michel Dänzer wrote: On 29/06/17 05:23 PM,

Re: [PATCH 4/5] drm/amdgpu: Set/clear CPU_ACCESS_REQUIRED flag on page fault and CS

On Fri, Jun 30, 2017 at 08:47:27AM +0200, Christian König wrote: > Am 30.06.2017 um 04:24 schrieb Michel Dänzer: > > On 29/06/17 07:05 PM, Daniel Vetter wrote: > > > On Thu, Jun 29, 2017 at 06:58:05PM +0900, Michel Dänzer wrote: > > > > On 29/06/17 05:23 PM, Christian König wrote: > > > > > Am

Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

On Fri, Jun 30, 2017 at 12:34 PM, Christian König wrote: > Am 30.06.2017 um 09:14 schrieb Michel Dänzer: >> >> On 30/06/17 03:59 PM, Christian König wrote: >>> >>> Am 30.06.2017 um 08:51 schrieb Michel Dänzer: We can deal with that internally in the kernel,

[PATCH 07/12] drm/amdgpu: reserve the first 2x2MB of GART

From: Christian König We want to use them as remap address space. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 5 - drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +++ 2 files changed, 7

[PATCH 04/12] drm/amdgpu: add vm_needs_flush parameter to amdgpu_copy_buffer

From: Christian König This allows us to flush the system VM here. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 4 ++--

[PATCH 05/12] drm/amdgpu: bind BOs to TTM only once

From: Christian König No need to do this on every round. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 70 ++--- 1 file changed, 29 insertions(+), 41 deletions(-) diff --git

[PATCH 11/12] drm/amdgpu: remove maximum BO size limitation.

From: Christian König We can finally remove this now. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 --- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

[PATCH 06/12] drm/amdgpu: bind BOs with GTT space allocated directly

From: Christian König This avoids binding them later on. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 49 ++---

[PATCH 12/12] drm/amdgpu: add gtt_sys_limit

From: Christian König Limit the size of the GART table for the system domain. This saves us a bunch of visible VRAM, but also limitates the maximum BO size we can swap out. Signed-off-by: Christian König ---

[PATCH 10/12] drm/amdgpu: stop mapping BOs to GTT

From: Christian König No need to map BOs to GTT on eviction and intermediate transfers any more. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 19 ++- 1 file changed, 2 insertions(+), 17

[PATCH 03/12] drm/amdgpu: allow flushing VMID0 before IB execution as well

From: Christian König This allows us to queue IBs which needs an up to date system domain as well. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 ++ 2 files

[PATCH 09/12] drm/amdgpu: use the GTT windows for BO moves

From: Christian König This way we don't need to map the full BO at a time any more. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 127 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |

[PATCH 02/12] drm/amdgpu: fix amdgpu_ring_write_multiple

From: Christian König Overwriting still used ring content has a low probability to cause problems, not writing at all has 100% probability to cause problems. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4

[PATCH 01/12] drm/amdgpu: move ring helpers to amdgpu_ring.h

From: Christian König Keep them where they belong. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 44 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 42

Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

Am 30.06.2017 um 09:14 schrieb Michel Dänzer: On 30/06/17 03:59 PM, Christian König wrote: Am 30.06.2017 um 08:51 schrieb Michel Dänzer: We can deal with that internally in the kernel, while fixing the existing flag for userspace. And as I said, NAK to that approach. I'm not going to add a

[PATCH xf86-video-ati] Use pRADEONEnt->fd exclusively for the DRM file descriptor

From: Michel Dänzer This brings us closer to amdgpu. Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 151 + src/drmmode_display.h | 1 - src/radeon.h | 14 +++--

[PATCH] amdgpu: Set cik/si_support to 1 by default if radeon isn't built

From: Michel Dänzer It was required to explicitly set these parameters to 1, even if the radeon driver isn't built at all, which is not intuitive. Reported-by: Shawn Starr Signed-off-by: Michel Dänzer ---

Re: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

Am 30.06.2017 um 03:21 schrieb Michel Dänzer: On 30/06/17 06:08 AM, Shaoyun Liu wrote: 1. Use spin lock instead of mutex in KIQ 2. Directly write to KIQ fence address instead of using fence_emit() 3. Disable the interrupt for KIQ read/write and use CPU polling This list indicates that this

RE: [PATCH] drm/amd/amdgpu: move get memory type function from early init to sw init

Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Jim Qu Sent: Friday, June 30, 2017 14:57 To: amd-gfx@lists.freedesktop.org Cc: Qu, Jim Subject: [PATCH]

[PATCH] drm/amd/amdgpu: move get memory type function from early init to sw init

On PX system, it will get memory type before gpu post , and get unkown type. Change-Id: I79e3760dd789c21a5f552bc4e5754f7a2defdaae Signed-off-by: Jim Qu --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

On 30/06/17 03:59 PM, Christian König wrote: > Am 30.06.2017 um 08:51 schrieb Michel Dänzer: >> We can deal with that internally in the kernel, while fixing the >> existing flag for userspace. > > And as I said, NAK to that approach. I'm not going to add a > CPU_ACCESS_REALLY_REQUIRED flag in the

[PATCH] /drm/amd/amdgpu: move get memory type function from early init to sw init

On PX system, it will get memory type before gpu post , and get unkown type. Change-Id: I79e3760dd789c21a5f552bc4e5754f7a2defdaae Signed-off-by: Jim Qu --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

Am 30.06.2017 um 08:51 schrieb Michel Dänzer: We can deal with that internally in the kernel, while fixing the existing flag for userspace. And as I said, NAK to that approach. I'm not going to add a CPU_ACCESS_REALLY_REQUIRED flag in the kernel just because mesa has messed up it's use case.

Re: [PATCH 4/5] drm/amdgpu: Set/clear CPU_ACCESS_REQUIRED flag on page fault and CS

Am 30.06.2017 um 04:24 schrieb Michel Dänzer: On 29/06/17 07:05 PM, Daniel Vetter wrote: On Thu, Jun 29, 2017 at 06:58:05PM +0900, Michel Dänzer wrote: On 29/06/17 05:23 PM, Christian König wrote: Am 29.06.2017 um 04:35 schrieb Michel Dänzer: On 29/06/17 08:26 AM, John Brooks wrote: On Wed,

Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

Am 30.06.2017 um 03:36 schrieb Michel Dänzer: On 30/06/17 12:03 AM, Marek Olšák wrote: Do you have any concern if we also stop using the CPU_ACCESS flag on radeon? No concern from my side for radeon. On Thu, Jun 29, 2017 at 4:51 PM, Christian König wrote: Yeah, I