Re: [PATCH v2 1/3] drm/amdgpu: remove superfluous check

the series is Reviewed-by: Junwei Zhang Jerry On 07/05/2017 01:32 PM, Huang Rui wrote: Signed-off-by: Huang Rui --- Changes from V1 -> V2 - amdgpu_bo_free_kernel is safe even the bo is NULL, so remove the "if" check. Thanks, Ray ---

[PATCH v2 1/3] drm/amdgpu: remove superfluous check

Signed-off-by: Huang Rui --- Changes from V1 -> V2 - amdgpu_bo_free_kernel is safe even the bo is NULL, so remove the "if" check. Thanks, Ray --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 8 2 files

[PATCH v2 3/3] drm/amdgpu: make psp cmd buffer as a reserve memory

Signed-off-by: Huang Rui --- Changes from V1 -> V2 - amdgpu_bo_free_kernel is safe even the bo is NULL, so remove the "if" check. - error handling of ring_init should be returned as failed_mem. Thanks, Ray --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 38

RE: The amd-stagint-4.11 doen't contain the commit ab51ee31dda1a37b473074e402394f879c51d591 in amd-staging-4.9

+ amd-gfx We really need to understand why this commit is not shown in 4.11 staging, because we worry other patches may meet same issue, and cause regression BR Monk From: Deng, Emily Sent: Tuesday, July 04, 2017 11:31 PM To: Deucher, Alexander ; Liu, Monk

RE: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

What do you mean HDP flush code ? Can you elaborate it ? the only HDP flush I remember via CPU is the one in GMC_V9's gpu_tlb_flush, I saw it is still using regular register access, but I agree change it to CPU direct access BR Monk From: Liu, Shaoyun Sent: Tuesday, July 04, 2017 2:14 PM To:

Re: [PATCH] drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu.

On 04/07/17 05:42 PM, Rex Zhu wrote: > when hw_fini, pp will disable dpm.so remove sysfs before > disable dpm. > > Change-Id: I17114f5c964b870802abbde32544b28eeb6173ab > Signed-off-by: Rex Zhu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 6 +++--- > 1 file changed, 3

[PATCH v3 00/16] improve the fb_setcmap helper

Hi! While trying to get CLUT support for the atmel_hlcdc driver, and specifically for the emulated fbdev interface, I received some push-back that my feeble in-driver attempts should be solved by the core. This is my attempt to do it right. I have obviously not tested all of this with more than

[PATCH v3 04/16] drm/color-mgmt: move atomic state/commit out from .gamma_set

Handle the atomics directly in the ioctl instead, in preparation for the fb_setcmap helper needing to commit the gamma map for several crtc in one commit. Signed-off-by: Peter Rosin --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c |

Re: [PATCH 07/11] drm/amdgpu: rename GART to SYSVM

On 05/07/17 06:11 AM, Felix Kuehling wrote: > I'm afraid this will lead to more confusion when talking to different > teams in AMD. At least to me "GART" was always understood to be the > system-wide address translation table (VMID-0). The remnant from the > pre-GPUVM days. You're now calling that

RE: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name

> do you also have a Mesa patch showing how the new APIs will be used? Sent out to mesa dev just now. > Remove these lines. Right. > Please consistently either use this, or don't add the util directory to the > include path anywhere. OK. > Put an empty line between declarations and statements.

Re: [PATCH 12/12] drm/amdgpu: enable foreign DMA-buf objects

On 17-07-04 12:39 PM, Christian König wrote: > Long story short all those cases must cleanly be handled before this > patch series can land upstream (or even be in any hybrid release). FWIW, it's in 17.20. > I'm pretty sure that the patch as is would break A+A laptops, so > pushing it to any

RE: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

Hi , Monk The TLB flush code is not used from IRQ , but it's been called while holding spin_lock . This is the reason why I want to change the routine be atomic. After check the register spec again , I found that the TLB invalidation and HDP coherency cntl register are safe to use in the

[PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

nbio hdp flush routine are called within atomic context. Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register since this register has its own VF copy Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6 Signed-off-by: Shaoyun Liu ---

Re: [PATCH 12/12] drm/amdgpu: enable foreign DMA-buf objects

Am 04.07.2017 um 17:56 schrieb Felix Kuehling: On 17-07-04 03:32 AM, Christian König wrote: Am 03.07.2017 um 23:11 schrieb Felix Kuehling: + +list_add(>list, >gem_objects); +gobj->bo = amdgpu_bo_ref(bo); +bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; It's a bit more tricker

[PATCH umr 2/2] Avoid using debugfs config data in no_kernel mode

Signed-off-by: Tom St Denis --- src/app/print_config.c | 2 +- src/lib/discover.c | 21 - src/lib/scan_config.c | 9 +++-- src/umr.h | 2 +- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/src/app/print_config.c

[PATCH umr 1/2] Tidy up formatting in new discovery code.

Signed-off-by: Tom St Denis --- src/lib/discover.c | 36 +++- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/src/lib/discover.c b/src/lib/discover.c index a95fe57c9b4d..2faed79334ee 100644 --- a/src/lib/discover.c +++

Re: [PATCH 12/12] drm/amdgpu: enable foreign DMA-buf objects

On 17-07-04 03:32 AM, Christian König wrote: > Am 03.07.2017 um 23:11 schrieb Felix Kuehling: >> + >> +list_add(>list, >gem_objects); >> +gobj->bo = amdgpu_bo_ref(bo); >> +bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; > > It's a bit more tricker than that. IIRC my original patch

RE: [PATCH] drm/amdgpu: fix S3 failure on specific platform

> -Original Message- > From: Christian König [mailto:deathsim...@vodafone.de] > Sent: Tuesday, July 04, 2017 3:50 AM > To: Deucher, Alexander; Wang, Ken; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/amdgpu: fix S3 failure on specific platform > > Am 04.07.2017 um 06:47 schrieb

[PATCH v3 14/16] drm: radeon: remove dead code and pointless local lut storage

The redundant fb helpers .load_lut, .gamma_set and .gamma_get are no longer used. Remove the dead code and hook up the crtc .gamma_set to use the crtc gamma_store directly instead of duplicating that info locally. Signed-off-by: Peter Rosin ---

[PATCH v3 06/16] drm: amd: remove dead code and pointless local lut storage

The redundant fb helpers .load_lut, .gamma_set and .gamma_get are no longer used. Remove the dead code and hook up the crtc .gamma_set to use the crtc gamma_store directly instead of duplicating that info locally. Signed-off-by: Peter Rosin ---

Re: [PATCH] drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu.

On Tue, Jul 4, 2017 at 4:42 AM, Rex Zhu wrote: > when hw_fini, pp will disable dpm.so remove sysfs before > disable dpm. > > Change-Id: I17114f5c964b870802abbde32544b28eeb6173ab > Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher >

Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

On Tue, Jul 4, 2017 at 10:09 AM, Michel Dänzer wrote: > On 03/07/17 10:03 PM, Marek Olšák wrote: >> On Mon, Jul 3, 2017 at 12:08 PM, Michel Dänzer wrote: >>> On 30/06/17 08:43 PM, Marek Olšák wrote: I don't know what is being talked about here

Re: [PATCH] drm/amdgpu: set firmware loading type as direct by default for raven

On 07/04/2017 05:59 PM, Huang Rui wrote: On Tue, Jul 04, 2017 at 05:39:51PM +0800, Zhang, Jerry wrote: Hi Ray, Thanks for your initial patch to enable PSP option for Raven. To simplify it, we may leverage VEGA10 case for Raven directly. And remove all Raven existing code under "case

Re: [PATCH] drm/amdgpu: set firmware loading type as direct by default for raven

On Tue, Jul 04, 2017 at 05:39:51PM +0800, Zhang, Jerry wrote: > Hi Ray, > > Thanks for your initial patch to enable PSP option for Raven. > > To simplify it, we may leverage VEGA10 case for Raven directly. > And remove all Raven existing code under "case CHIP_RAVEN" > How do you think about it?

Re: [PATCH 3/3] drm/amdgpu: make psp cmd buffer as a reserve memory

On Tue, Jul 04, 2017 at 04:25:25PM +0800, Zhang, Jerry (Junwei) wrote: > Yeah, when I had a glance at this func, flashed a similar idea. > A little comment inline, please confirm it. > > Regards, > Jerry > > On 07/04/2017 02:10 PM, Huang Rui wrote: > >We would like to use a reserve vram to store

Re: [PATCH] drm/amdgpu: set firmware loading type as direct by default for raven

Hi Ray, Thanks for your initial patch to enable PSP option for Raven. To simplify it, we may leverage VEGA10 case for Raven directly. And remove all Raven existing code under "case CHIP_RAVEN" How do you think about it? Jerry On 07/04/2017 04:35 PM, Huang Rui wrote: In previous case, driver

Re: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name

Hi Sam, do you also have a Mesa patch showing how the new APIs will be used? Without seeing that, some minor comments below. On 01/07/17 04:25 AM, Samuel Li wrote: > > +//#include > +//#include Remove these lines. > +#include "util/util_asic_id.h" Patch 1 adds the util directory to

[PATCH] drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu.

when hw_fini, pp will disable dpm.so remove sysfs before disable dpm. Change-Id: I17114f5c964b870802abbde32544b28eeb6173ab Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

Re: [PATCH 07/11] drm/amdgpu: rename GART to SYSVM

Am 04.07.2017 um 10:09 schrieb Huang Rui: On Mon, Jul 03, 2017 at 11:44:32AM +0200, Christian König wrote: From: Christian König Just mass rename all names related to the hardware GART/GTT functions to SYSVM. The name of symbols related to the TTM TT domain stay the

[PATCH] drm/amdgpu: set firmware loading type as direct by default for raven

In previous case, driver can't enable psp via the kernel parameter for raven. We should open this path and set it as direct by default till psp firmware loading is workable. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 +- 1 file changed, 1

Re: [PATCH 3/3] drm/amdgpu: make psp cmd buffer as a reserve memory

Yeah, when I had a glance at this func, flashed a similar idea. A little comment inline, please confirm it. Regards, Jerry On 07/04/2017 02:10 PM, Huang Rui wrote: We would like to use a reserve vram to store all non-psp firmware data when it is submmited. And needn't alloc/free when each

Re: Deprecation of AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

On 03/07/17 10:03 PM, Marek Olšák wrote: > On Mon, Jul 3, 2017 at 12:08 PM, Michel Dänzer wrote: >> On 30/06/17 08:43 PM, Marek Olšák wrote: >>> >>> I don't know what is being talked about here anymore, but I wouldn't >>> like to use CPU_ACCESS_REQUIRED or

Re: [PATCH 07/11] drm/amdgpu: rename GART to SYSVM

I have no strong opinion with that, this patch is Acked-by: Chunming Zhou On 2017年07月04日 15:43, Christian König wrote: Maybe we just need rename GART functions to SYSVM. That is essentially what I've did. In recent discussion we a couple of times the problem that we

Re: [PATCH 1/3] drm/amdgpu: move check from cpu address to bo

On Tue, Jul 04, 2017 at 03:19:17PM +0800, Koenig, Christian wrote: > Actually amdgpu_bo_free_kernel is NULL save, so you should rather remove > the "if"s here altogether. > I see, will remove all "if" in front of bo free. Thanks, Rui ___ amd-gfx

Re: [PATCH] drm/amdgpu: fix S3 failure on specific platform

Am 04.07.2017 um 06:47 schrieb Deucher, Alexander: -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Ken Wang Sent: Tuesday, July 04, 2017 12:26 AM To: amd-gfx@lists.freedesktop.org Cc: Wang, Ken Subject: [PATCH] drm/amdgpu: fix S3 failure on

Re: [PATCH 1/2] drm/amdgpu/gfx8: fix driver reload with KIQ

Am 04.07.2017 um 08:00 schrieb Alex Deucher: Drop the deactivation in KIQ init and drop the KCQ disabling via KIQ. We disable the MEC shortly after anyway, so there is no need to wait for all of this. Doing so seems to leave the MEC in a bad way. Signed-off-by: Alex Deucher

Re: [PATCH 07/11] drm/amdgpu: rename GART to SYSVM

Maybe we just need rename GART functions to SYSVM. That is essentially what I've did. In recent discussion we a couple of times the problem that we need to distinguish between the system VM and the GART/GTT domain from TTM. See starting with R6xx I think we used the system VM to implement

Re: [PATCH 12/12] drm/amdgpu: enable foreign DMA-buf objects

Am 03.07.2017 um 23:11 schrieb Felix Kuehling: From: Christian König We should be able to handle BOs from other instances as well. Signed-off-by: Christian König Reviewed-by: Felix Kuehling ---

Re: [PATCH 2/3] drm/amdgpu: fix missed asd bo free when hw_fini

Am 04.07.2017 um 08:10 schrieb Huang Rui: Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 1469e6d..7b43c60

Re: [PATCH 07/12] drm: export drm_gem_prime_dmabuf_ops

Am 04.07.2017 um 08:26 schrieb Daniel Vetter: On Tue, Jul 04, 2017 at 02:55:00PM +1000, Dave Airlie wrote: On 4 Jul. 2017 11:23, "Michel Dänzer" wrote: Adding the dri-devel list, since this is a core DRM patch. On 04/07/17 06:11 AM, Felix Kuehling wrote: From:

Re: [PATCH 1/3] drm/amdgpu: move check from cpu address to bo

Actually amdgpu_bo_free_kernel is NULL save, so you should rather remove the "if"s here altogether. Christian. Am 04.07.2017 um 08:10 schrieb Huang Rui: Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

Re: [PATCH 1/2] drm/amdgpu/gfx8: fix driver reload with KIQ

On 04/07/17 03:00 PM, Alex Deucher wrote: > Drop the deactivation in KIQ init and drop the KCQ disabling > via KIQ. We disable the MEC shortly after anyway, so there is > no need to wait for all of this. Doing so seems to leave the > MEC in a bad way. > > Signed-off-by: Alex Deucher

Re: [PATCH libdrm] amdgpu: move asic id table to a separate file

2017-06-12 17:50 GMT+08:00 Michel Dänzer : > From: Xiaojie Yuan > > v2: fix an off by one error and leading white spaces > v3: use thread safe strtok_r(); initialize len before calling getline(); > change printf() to drmMsg(); add initial amdgpu.ids >

Re: [PATCH 07/12] drm: export drm_gem_prime_dmabuf_ops

On Tue, Jul 04, 2017 at 02:55:00PM +1000, Dave Airlie wrote: > On 4 Jul. 2017 11:23, "Michel Dänzer" wrote: > > > Adding the dri-devel list, since this is a core DRM patch. > > > On 04/07/17 06:11 AM, Felix Kuehling wrote: > > From: Christian König

[PATCH 3/3] drm/amdgpu: make psp cmd buffer as a reserve memory

We would like to use a reserve vram to store all non-psp firmware data when it is submmited. And needn't alloc/free when each firmware submits again and again, we can reuse that just one page size buffer. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |

[PATCH 1/3] drm/amdgpu: move check from cpu address to bo

Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

[PATCH 2/3] drm/amdgpu: fix missed asd bo free when hw_fini

Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 1469e6d..7b43c60 100644 ---

[PATCH 2/2] drm/amdgpu/gfx9: fix driver reload with KIQ

Drop the KCQ disabling via KIQ. We disable the MEC shortly after anyway, so there is no need to wait for all of this. Doing so seems to leave the MEC in a bad way. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 51

[PATCH 1/2] drm/amdgpu/gfx8: fix driver reload with KIQ

Drop the deactivation in KIQ init and drop the KCQ disabling via KIQ. We disable the MEC shortly after anyway, so there is no need to wait for all of this. Doing so seems to leave the MEC in a bad way. Signed-off-by: Alex Deucher ---