Re: [PATCH] drm/amd/pp: fix mclk fixed in high when no display connected

[Tom St Denis]

Hi Alex,

This also seems to work on my setup.

Cheers,
Tom

On 02/02/18 10:23 AM, Alex Deucher wrote:

On Thu, Feb 1, 2018 at 11:52 PM, Rex Zhu  wrote:

Change-Id: I2d7663e164ff8eeafe0a4fed99e106b1d130a285
Signed-off-by: Rex Zhu 
---
  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index ba3c7d6..6700839 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2919,10 +2919,10 @@ static int smu7_apply_state_adjust_rules(struct 
pp_hwmgr *hwmgr,
 
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);


-   disable_mclk_switching = ((1 < info.display_count) ||
- disable_mclk_switching_for_frame_lock ||
+   disable_mclk_switching = ((1 < info.display_count) &&
+ (disable_mclk_switching_for_frame_lock ||
   smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us) ||
- (mode_info.refresh_rate > 120));
+ (mode_info.refresh_rate > 120)));


I think this will break the logic to handle single display over 120 hz
and the vblank too short cases.  I think you want 1 <= display_count.
It might be better to make the logic more clear.  How about the
attached patch?

Alex



 sclk = smu7_ps->performance_levels[0].engine_clock;
 mclk = smu7_ps->performance_levels[0].memory_clock;
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH libdrm 3/4] amdgpu: use the high VA range if possible v2

[Christian König]

Hi Marek,

it looks like the hardware sign extends bit 47 into bits 48-63. E.g. 
0x8000 gets extended to 0x8000.


Christian.

Am 03.02.2018 um 03:02 schrieb Marek Olšák:

Hi Christian,

How does this work with 48-bit addresses that the 3D engine uses? It
can't set 0x8000 for the high bits. It's trimmed to 0x8000.

Thanks,
Marek

On Sun, Jan 7, 2018 at 10:11 AM, Christian König
 wrote:

Retire the low range on Vega10 this frees up everything below 
0x8000 for HMM.

v2: keep the 32bit range working.

Signed-off-by: Christian König 
---
  amdgpu/amdgpu_device.c | 18 ++
  1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index d7077184..a0d01727 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -264,13 +264,23 @@ int amdgpu_device_initialize(int fd,
 goto cleanup;
 }

-   start = dev->dev_info.virtual_address_offset;
-   max = MIN2(dev->dev_info.virtual_address_max, 0x1ULL);
+   if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) {
+   start = dev->dev_info.high_va_offset;
+   max = dev->dev_info.high_va_max;
+   } else {
+   start = dev->dev_info.virtual_address_offset;
+   max = dev->dev_info.virtual_address_max;
+   }
+
+   max = MIN2(max, (start & ~0x) + 0x1ULL);
 amdgpu_vamgr_init(>vamgr_32, start, max,
   dev->dev_info.virtual_address_alignment);

-   start = MAX2(dev->dev_info.virtual_address_offset, 0x1ULL);
-   max = MAX2(dev->dev_info.virtual_address_max, 0x1ULL);
+   start = max;
+   if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max)
+   max = dev->dev_info.high_va_max;
+   else
+   max = dev->dev_info.virtual_address_max;
 amdgpu_vamgr_init(>vamgr, start, max,
   dev->dev_info.virtual_address_alignment);

--
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx