Re: [PATCH] drm/amd/pp: Refine add irq logic in powerplay

[Alex Deucher]

On Wed, Mar 21, 2018 at 12:54 AM, Rex Zhu  wrote:
> 1. register smu irq when sw init.
> 2. delete useless function argument.

If you split this into two patches, one for each logical change above, it's:
Reviewed-by: Alex Deucher 

>
> Change-Id: Ie817e524327f14edfde62843fbdd2a7999489819
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 6 +++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   | 4 
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  | 5 ++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 5 ++---
>  drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   | 2 +-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +--
>  7 files changed, 11 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 0381317..7e8ad30 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -117,6 +117,8 @@ static int pp_sw_init(void *handle)
>
> ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
>
> +   phm_register_irq_handlers(hwmgr);
> +
> pr_debug("amdgpu: powerplay sw initialized\n");
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index b784131..ae2e933 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -202,12 +202,12 @@ int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
> return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
>  }
>
> -int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
> +int phm_register_irq_handlers(struct pp_hwmgr *hwmgr)
>  {
> PHM_FUNC_CHECK(hwmgr);
>
> -   if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL)
> -   return 
> hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
> +   if (hwmgr->hwmgr_func->register_irq_handlers != NULL)
> +   return hwmgr->hwmgr_func->register_irq_handlers(hwmgr);
>
> return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index fbcdda5..6318438 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -200,10 +200,6 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> if (ret)
> goto err2;
>
> -   ret = phm_register_thermal_interrupt(hwmgr, NULL);
> -   if (ret)
> -   goto err2;
> -
> return 0;
>  err2:
> if (hwmgr->hwmgr_func->backend_fini)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 4083387..8a81360 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3996,8 +3996,7 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr 
> *hwmgr, uint16_t us_max_f
> PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
>  }
>
> -static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
> -   const void *thermal_interrupt_info)
> +static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
>  {
> return 0;
>  }
> @@ -4982,7 +4981,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr 
> *hwmgr, long *input, uint
> .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
> .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
> .uninitialize_thermal_controller = 
> smu7_thermal_ctrl_uninitialize_thermal_controller,
> -   .register_internal_thermal_interrupt = 
> smu7_register_internal_thermal_interrupt,
> +   .register_irq_handlers = smu7_register_irq_handlers,
> .check_smc_update_required_for_display_configuration = 
> smu7_check_smc_update_required_for_display_configuration,
> .check_states_equal = smu7_check_states_equal,
> .set_fan_control_mode = smu7_set_fan_control_mode,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index eb9884e..7bb9dd9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4819,8 +4819,7 @@ static int vega10_get_thermal_temperature_range(struct 
> pp_hwmgr *hwmgr,
> .process = phm_irq_process,
>  };
>
> -static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
> -   const void *info)
> +static int vega10_register_irq_handlers(struct pp_hwmgr *hwmgr)
>  {
> struct amdgpu_irq_src *source =
>   

[PATCH] drm/amd/pp: Refine add irq logic in powerplay

[Rex Zhu]

1. register smu irq when sw init.
2. delete useless function argument.

Change-Id: Ie817e524327f14edfde62843fbdd2a7999489819
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 6 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   | 4 
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  | 5 ++---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 5 ++---
 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +--
 7 files changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 0381317..7e8ad30 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -117,6 +117,8 @@ static int pp_sw_init(void *handle)
 
ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
 
+   phm_register_irq_handlers(hwmgr);
+
pr_debug("amdgpu: powerplay sw initialized\n");
}
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index b784131..ae2e933 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -202,12 +202,12 @@ int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
 }
 
-int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
+int phm_register_irq_handlers(struct pp_hwmgr *hwmgr)
 {
PHM_FUNC_CHECK(hwmgr);
 
-   if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL)
-   return 
hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
+   if (hwmgr->hwmgr_func->register_irq_handlers != NULL)
+   return hwmgr->hwmgr_func->register_irq_handlers(hwmgr);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index fbcdda5..6318438 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -200,10 +200,6 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
if (ret)
goto err2;
 
-   ret = phm_register_thermal_interrupt(hwmgr, NULL);
-   if (ret)
-   goto err2;
-
return 0;
 err2:
if (hwmgr->hwmgr_func->backend_fini)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4083387..8a81360 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3996,8 +3996,7 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr 
*hwmgr, uint16_t us_max_f
PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
 }
 
-static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
-   const void *thermal_interrupt_info)
+static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
 {
return 0;
 }
@@ -4982,7 +4981,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, uint
.get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
.set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
.uninitialize_thermal_controller = 
smu7_thermal_ctrl_uninitialize_thermal_controller,
-   .register_internal_thermal_interrupt = 
smu7_register_internal_thermal_interrupt,
+   .register_irq_handlers = smu7_register_irq_handlers,
.check_smc_update_required_for_display_configuration = 
smu7_check_smc_update_required_for_display_configuration,
.check_states_equal = smu7_check_states_equal,
.set_fan_control_mode = smu7_set_fan_control_mode,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index eb9884e..7bb9dd9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4819,8 +4819,7 @@ static int vega10_get_thermal_temperature_range(struct 
pp_hwmgr *hwmgr,
.process = phm_irq_process,
 };
 
-static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
-   const void *info)
+static int vega10_register_irq_handlers(struct pp_hwmgr *hwmgr)
 {
struct amdgpu_irq_src *source =
kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
@@ -4978,7 +4977,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, ui
.avfs_control = vega10_avfs_enable,
.notify_cac_buffer_info = vega10_notify_cac_buffer_info,
.get_thermal_temperature_range = vega10_get_thermal_temperature_range,
-   .register_internal_thermal_interrupt = 

Re: [PATCH] drm/amd/pp: Fix handle kernel paging request when reset pp table

[Alex Deucher]

On Tue, Mar 20, 2018 at 11:06 PM, Rex Zhu  wrote:
> Change-Id: I885e1b6a682a20baa0c8ca5bf9d1027375a00812
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index dbb0e69..0381317 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -738,7 +738,7 @@ static int amd_powerplay_reset(void *handle)
> if (ret)
> return ret;
>
> -   ret = pp_hw_fini(hwmgr);
> +   ret = hwmgr_hw_fini(hwmgr);
> if (ret)
> return ret;
>
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/pp: Fix handle kernel paging request when reset pp table

[Rex Zhu]

Change-Id: I885e1b6a682a20baa0c8ca5bf9d1027375a00812
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index dbb0e69..0381317 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -738,7 +738,7 @@ static int amd_powerplay_reset(void *handle)
if (ret)
return ret;
 
-   ret = pp_hw_fini(hwmgr);
+   ret = hwmgr_hw_fini(hwmgr);
if (ret)
return ret;
 
-- 
1.9.1

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Re: [PATCH] drm/amdgpu: Remove wrapper layer of cgs irq handling

[Zhang, Jerry (Junwei)]

On 03/20/2018 07:25 PM, Rex Zhu wrote:

1. remove struct cgs_os_ops
2. delete cgs_linux.h
3. refine the irq code for vega10

Change-Id: I1b1b56c38596e632fe627c436a5072ae5b359b8c
Signed-off-by: Rex Zhu 


Acked-by: Junwei Zhang 

Nice to see that

Jerry


---
  drivers/gpu/drm/amd/acp/include/acp_gfx_if.h   |   1 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 111 ---
  drivers/gpu/drm/amd/display/dc/os_types.h  |   2 +-
  drivers/gpu/drm/amd/include/cgs_common.h   |   1 -
  drivers/gpu/drm/amd/include/cgs_linux.h| 119 -
  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c|  46 +---
  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c   |  28 +
  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h   |   5 +
  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  36 ---
  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |   5 -
  10 files changed, 56 insertions(+), 298 deletions(-)
  delete mode 100644 drivers/gpu/drm/amd/include/cgs_linux.h

diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h 
b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
index a72ddb2f..feab8eb 100644
--- a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
+++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
@@ -25,7 +25,6 @@
  #define _ACP_GFX_IF_H

  #include 
-#include "cgs_linux.h"
  #include "cgs_common.h"

  int amd_acp_hw_init(struct cgs_device *cgs_device,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 5b37c1a..0f2b376 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -28,7 +28,6 @@
  #include 
  #include 
  #include "amdgpu.h"
-#include "cgs_linux.h"
  #include "atom.h"
  #include "amdgpu_ucode.h"

@@ -182,109 +181,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct 
cgs_device *cgs_device, unsigne
adev->mode_info.atom_context, table, args);
  }

-struct cgs_irq_params {
-   unsigned src_id;
-   cgs_irq_source_set_func_t set;
-   cgs_irq_handler_func_t handler;
-   void *private_data;
-};
-
-static int cgs_set_irq_state(struct amdgpu_device *adev,
-struct amdgpu_irq_src *src,
-unsigned type,
-enum amdgpu_interrupt_state state)
-{
-   struct cgs_irq_params *irq_params =
-   (struct cgs_irq_params *)src->data;
-   if (!irq_params)
-   return -EINVAL;
-   if (!irq_params->set)
-   return -EINVAL;
-   return irq_params->set(irq_params->private_data,
-  irq_params->src_id,
-  type,
-  (int)state);
-}
-
-static int cgs_process_irq(struct amdgpu_device *adev,
-  struct amdgpu_irq_src *source,
-  struct amdgpu_iv_entry *entry)
-{
-   struct cgs_irq_params *irq_params =
-   (struct cgs_irq_params *)source->data;
-   if (!irq_params)
-   return -EINVAL;
-   if (!irq_params->handler)
-   return -EINVAL;
-   return irq_params->handler(irq_params->private_data,
-  irq_params->src_id,
-  entry->iv_entry);
-}
-
-static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
-   .set = cgs_set_irq_state,
-   .process = cgs_process_irq,
-};
-
-static int amdgpu_cgs_add_irq_source(void *cgs_device,
-unsigned client_id,
-unsigned src_id,
-unsigned num_types,
-cgs_irq_source_set_func_t set,
-cgs_irq_handler_func_t handler,
-void *private_data)
-{
-   CGS_FUNC_ADEV;
-   int ret = 0;
-   struct cgs_irq_params *irq_params;
-   struct amdgpu_irq_src *source =
-   kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
-   if (!source)
-   return -ENOMEM;
-   irq_params =
-   kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
-   if (!irq_params) {
-   kfree(source);
-   return -ENOMEM;
-   }
-   source->num_types = num_types;
-   source->funcs = _irq_funcs;
-   irq_params->src_id = src_id;
-   irq_params->set = set;
-   irq_params->handler = handler;
-   irq_params->private_data = private_data;
-   source->data = (void *)irq_params;
-   ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
-   if (ret) {
-   kfree(irq_params);
-   kfree(source);
-   }
-
-   return ret;
-}
-
-static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
- unsigned src_id, unsigned type)
-{
-   CGS_FUNC_ADEV;
-
-   if 

Re: [PATCH 09/34] drm/amd/display: fix lexa bw bounding box

[Zhang, Jerry (Junwei)]

Please adhere to the naming of Polaris12 in commit log as well.
thanks.

Jerry

On 03/21/2018 03:12 AM, Harry Wentland wrote:

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Bhawanpreet Lakha 
Acked-by: Harry Wentland 
---
  drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 121 ++-
  drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h   |   1 +
  2 files changed, 120 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 0cbab81ab304..3d05e82652af 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -52,10 +52,11 @@ static enum bw_calcs_version 
bw_calcs_version_from_asic_id(struct hw_asic_id asi
return BW_CALCS_VERSION_CARRIZO;

case FAMILY_VI:
+   if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
+   return BW_CALCS_VERSION_LEXA;
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS10;
-   if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
-   
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
+   if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS11;
return BW_CALCS_VERSION_INVALID;

@@ -2373,6 +2374,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
break;
+   case BW_CALCS_VERSION_LEXA:
+   vbios.memory_type = bw_def_gddr5;
+   vbios.dram_channel_width_in_bits = 32;
+   vbios.number_of_dram_channels = asic_id.vram_width / 
vbios.dram_channel_width_in_bits;
+   vbios.number_of_dram_banks = 8;
+   vbios.high_yclk = bw_int_to_fixed(6000);
+   vbios.mid_yclk = bw_int_to_fixed(3200);
+   vbios.low_yclk = bw_int_to_fixed(1000);
+   vbios.low_sclk = bw_int_to_fixed(678);
+   vbios.mid1_sclk = bw_int_to_fixed(864);
+   vbios.mid2_sclk = bw_int_to_fixed(900);
+   vbios.mid3_sclk = bw_int_to_fixed(920);
+   vbios.mid4_sclk = bw_int_to_fixed(940);
+   vbios.mid5_sclk = bw_int_to_fixed(960);
+   vbios.mid6_sclk = bw_int_to_fixed(980);
+   vbios.high_sclk = bw_int_to_fixed(1049);
+   vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
+   vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
+   vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
+   vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
+   vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
+   vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
+   vbios.data_return_bus_width = bw_int_to_fixed(32);
+   vbios.trc = bw_int_to_fixed(48);
+   if (vbios.number_of_dram_channels == 2) // 64-bit
+   vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
+   else
+   vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
+   vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
+   vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
+   vbios.nbp_state_change_latency = bw_int_to_fixed(250);
+   vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
+   vbios.scatter_gather_enable = false;
+   vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
+   vbios.cursor_width = 32;
+   vbios.average_compression_rate = 4;
+   vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel 
= 256;
+   vbios.blackout_duration = bw_int_to_fixed(0); /* us */
+   vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
+
+   
dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation
 = 100;
+   
dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation
 = 100;
+   dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 
100;
+   dceip.large_cursor = false;
+   dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
+   dceip.dmif_pipe_en_fbc_chunk_tracker = false;
+   dceip.cursor_max_outstanding_group_num = 1;
+   dceip.lines_interleaved_into_lb = 2;
+   dceip.chunk_width = 256;
+   dceip.number_of_graphics_pipes = 5;
+   dceip.number_of_underlay_pipes = 

RE: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Li, Samuel]

Also, the change here is only for display buffer, so it is not really a "big" 
waste.

Regards,
Samuel Li

From: Li, Samuel
Sent: Tuesday, March 20, 2018 4:38 PM
To: Deucher, Alexander 
Cc: Alex Deucher ; Michel Dänzer ; 
amd-gfx list ; Marek Olšák ; 
Koenig, Christian 
Subject: RE: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support


O  I think we can also have the case of systems with similar amounts of carve 
out and system ram.  E.g., on a system with 4 GB of system memory with 1 GB 
carved out for vram.  It would be a big waste not to use VRAM.  We'll probably 
need a heuristic at some point.
Agreed. But for CZ/ST, due to hardware limitation as discussed before, we 
either use VRAM or GTT, not both. That might be changed for later ASICs, but it 
is beyond the scope of this patch.


Regards,
Samuel Li

From: Koenig, Christian
Sent: Tuesday, March 20, 2018 4:17 PM
To: Deucher, Alexander 
>; Marek Olšák 
>
Cc: Alex Deucher >; Michel 
Dänzer >; Li, Samuel 
>; amd-gfx list 
>
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

That's what I meant with use up the otherwise unused VRAM. I don't see any 
disadvantage of always setting GTT as second domain on APUs.

My assumption was that we dropped this in userspace for displayable surfaces, 
but Marek proved that wrong.

So what we should do is actually to add GTT as fallback to all BOs on APUs in 
Mesa and only make sure that the kernel is capable of handling GTT with optimal 
performance (e.g. have user huge pages etc..).

Christian.

Am 20.03.2018 um 21:04 schrieb Deucher, Alexander:

I think we can also have the case of systems with similar amounts of carve out 
and system ram.  E.g., on a system with 4 GB of system memory with 1 GB carved 
out for vram.  It would be a big waste not to use VRAM.  We'll probably need a 
heuristic at some point.



Alex


From: Christian König 

Sent: Tuesday, March 20, 2018 2:32:49 PM
To: Marek Olšák; Koenig, Christian
Cc: Alex Deucher; Deucher, Alexander; Michel Dänzer; Li, Samuel; amd-gfx list
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

I don't think that is a good idea.

Ideally GTT should now have the same performance as VRAM on APUs and we should 
use VRAM only for things where we absolutely have to and to actually use up the 
otherwise unused VRAM.

Can you run some tests with all BOs forced to GTT and see if there is any 
performance regression?

Christian.

Am 20.03.2018 um 15:51 schrieb Marek Olšák:
On Tue, Mar 20, 2018 at 9:55 AM, Christian König 
> 
wrote:
Yes, exactly. And if I remember correctly Mesa used to always set GTT as 
fallback on APUs, correct?

"used to" is the key part. Mesa doesn't force GTT on APUs anymore. It expects 
that the combination of BO priorities and BO move throttling will result in 
optimal BO placements over time.
Marek


The problem seems to be that this fallback isn't set for displayable BOs.

So what needs to be done is to just enable this fallback for displayable BOs as 
well if the kernel can handle it.

Christian.


Am 20.03.2018 um 00:01 schrieb Marek Olšák:
In theory, Mesa doesn't have to do anything. It can continue setting VRAM and 
if the kernel has to put a display buffer into GTT, it doesn't matter (for 
Mesa). Whether the VRAM placement is really used is largely determined by BO 
priorities.

The way I understand scather/gather is that it only allows the GTT placement. 
It doesn't force the GTT placement. Mesa also doesn't force the GTT placement.

Marek

On Mon, Mar 19, 2018 at 5:12 PM, Alex Deucher 
> wrote:
On Mon, Mar 19, 2018 at 4:29 PM, Li, Samuel 
> wrote:
>>to my earlier point, there may be cases where it is advantageous to put
>> display buffers in vram even if s/g display is supported
>
> Agreed. That is also why the patch has the options to let user select where
> to put display buffers.
>
> As whether to put the option in Mesa or kernel, it seems the difference is
> not much. Also, since amdgpufb can request even without mesa, kernel might
> be a better choice. In addition, putting in the kernel can save client's
> duplicate work(mesa, ogl, vulkan, 2d, kernel...)

Why do we even expose different memory pools to the UMDs in the first
place ;)  Each pool has performance 

Re: [PATCH 2/2] drm/amdgpu: mitigate workaround for i915

[Mike Lothian]

On Mon, 19 Feb 2018 at 13:58 Christian König  wrote:

> To be able to use DRI_PRIME with amdgpu and i915 we add all our fences
> only as exclusive ones.
>
> Disable that behavior when sharing between amdgpu itself cause it
> hinders concurrent execution.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 31
> ---
>  1 file changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> index f6d7f6404a07..8ce74a1d9966 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> @@ -30,6 +30,8 @@
>  #include 
>  #include 
>
> +static const struct dma_buf_ops amdgpu_dmabuf_ops;
> +
>  struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object
> *obj)
>  {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
> @@ -129,20 +131,27 @@ static int amdgpu_gem_map_attach(struct dma_buf
> *dma_buf,
> if (unlikely(r != 0))
> goto error_detach;
>
> -   /*
> -* Wait for all shared fences to complete before we switch to
> future
> -* use of exclusive fence on this prime shared bo.
> -*/
> -   r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
> -   MAX_SCHEDULE_TIMEOUT);
> -   if (unlikely(r < 0)) {
> -   DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);
> -   goto error_unreserve;
> +
> +   if (dma_buf->ops != _dmabuf_ops) {
> +   /*
> +* Wait for all shared fences to complete before we switch
> to future
> +* use of exclusive fence on this prime shared bo.
> +*/
> +   r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
> +   true, false,
> +
>  MAX_SCHEDULE_TIMEOUT);
> +   if (unlikely(r < 0)) {
> +   DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);
> +   goto error_unreserve;
> +   }
> }
>
> /* pin buffer into GTT */
> r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
> -   if (likely(r == 0))
> +   if (r)
> +   goto error_unreserve;
> +
> +   if (dma_buf->ops != _dmabuf_ops)
> bo->prime_shared_count++;
>
>  error_unreserve:
> @@ -166,7 +175,7 @@ static void amdgpu_gem_map_detach(struct dma_buf
> *dma_buf,
> goto error;
>
> amdgpu_bo_unpin(bo);
> -   if (bo->prime_shared_count)
> +   if (dma_buf->ops != _dmabuf_ops && bo->prime_shared_count)
> bo->prime_shared_count--;
> amdgpu_bo_unreserve(bo);
>
> --
> 2.14.1
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


Hi

This patch causes tearing / stuttering on my i915/amdgpu prime setup

Reverting this patch and some of  "[PATCH 3/3] drm/amdgpu: further mitigate
workaround for i915" to get it to compile, gets things working again

Sorry for not noticing this sooner

Let me know if you'd like me to test any follow up patches

Cheers

Mike
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RE: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Li, Samuel]

O  I think we can also have the case of systems with similar amounts of carve 
out and system ram.  E.g., on a system with 4 GB of system memory with 1 GB 
carved out for vram.  It would be a big waste not to use VRAM.  We'll probably 
need a heuristic at some point.
Agreed. But for CZ/ST, due to hardware limitation as discussed before, we 
either use VRAM or GTT, not both. That might be changed for later ASICs, but it 
is beyond the scope of this patch.


Regards,
Samuel Li

From: Koenig, Christian
Sent: Tuesday, March 20, 2018 4:17 PM
To: Deucher, Alexander ; Marek Olšák 

Cc: Alex Deucher ; Michel Dänzer ; 
Li, Samuel ; amd-gfx list 
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

That's what I meant with use up the otherwise unused VRAM. I don't see any 
disadvantage of always setting GTT as second domain on APUs.

My assumption was that we dropped this in userspace for displayable surfaces, 
but Marek proved that wrong.

So what we should do is actually to add GTT as fallback to all BOs on APUs in 
Mesa and only make sure that the kernel is capable of handling GTT with optimal 
performance (e.g. have user huge pages etc..).

Christian.

Am 20.03.2018 um 21:04 schrieb Deucher, Alexander:

I think we can also have the case of systems with similar amounts of carve out 
and system ram.  E.g., on a system with 4 GB of system memory with 1 GB carved 
out for vram.  It would be a big waste not to use VRAM.  We'll probably need a 
heuristic at some point.



Alex


From: Christian König 

Sent: Tuesday, March 20, 2018 2:32:49 PM
To: Marek Olšák; Koenig, Christian
Cc: Alex Deucher; Deucher, Alexander; Michel Dänzer; Li, Samuel; amd-gfx list
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

I don't think that is a good idea.

Ideally GTT should now have the same performance as VRAM on APUs and we should 
use VRAM only for things where we absolutely have to and to actually use up the 
otherwise unused VRAM.

Can you run some tests with all BOs forced to GTT and see if there is any 
performance regression?

Christian.

Am 20.03.2018 um 15:51 schrieb Marek Olšák:
On Tue, Mar 20, 2018 at 9:55 AM, Christian König 
> 
wrote:
Yes, exactly. And if I remember correctly Mesa used to always set GTT as 
fallback on APUs, correct?

"used to" is the key part. Mesa doesn't force GTT on APUs anymore. It expects 
that the combination of BO priorities and BO move throttling will result in 
optimal BO placements over time.
Marek


The problem seems to be that this fallback isn't set for displayable BOs.

So what needs to be done is to just enable this fallback for displayable BOs as 
well if the kernel can handle it.

Christian.


Am 20.03.2018 um 00:01 schrieb Marek Olšák:
In theory, Mesa doesn't have to do anything. It can continue setting VRAM and 
if the kernel has to put a display buffer into GTT, it doesn't matter (for 
Mesa). Whether the VRAM placement is really used is largely determined by BO 
priorities.

The way I understand scather/gather is that it only allows the GTT placement. 
It doesn't force the GTT placement. Mesa also doesn't force the GTT placement.

Marek

On Mon, Mar 19, 2018 at 5:12 PM, Alex Deucher 
> wrote:
On Mon, Mar 19, 2018 at 4:29 PM, Li, Samuel 
> wrote:
>>to my earlier point, there may be cases where it is advantageous to put
>> display buffers in vram even if s/g display is supported
>
> Agreed. That is also why the patch has the options to let user select where
> to put display buffers.
>
> As whether to put the option in Mesa or kernel, it seems the difference is
> not much. Also, since amdgpufb can request even without mesa, kernel might
> be a better choice. In addition, putting in the kernel can save client's
> duplicate work(mesa, ogl, vulkan, 2d, kernel...)

Why do we even expose different memory pools to the UMDs in the first
place ;)  Each pool has performance characteristics that may be
relevant for a particular work load.  Only the UMDs really know the
finer points of those workloads. In general, you don't want the kernel
dictating policy if you can avoid it.  The kernel exposes
functionality and userspace sets the policy.  With the location set in
userspace, each app/user can have whatever policy makes sense for
their use case all at the same time without needing to tweak their
kernel for every use case.

Alex



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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Christian König]

That's what I meant with use up the otherwise unused VRAM. I don't see 
any disadvantage of always setting GTT as second domain on APUs.


My assumption was that we dropped this in userspace for displayable 
surfaces, but Marek proved that wrong.


So what we should do is actually to add GTT as fallback to all BOs on 
APUs in Mesa and only make sure that the kernel is capable of handling 
GTT with optimal performance (e.g. have user huge pages etc..).


Christian.

Am 20.03.2018 um 21:04 schrieb Deucher, Alexander:


I think we can also have the case of systems with similar amounts of 
carve out and system ram.  E.g., on a system with 4 GB of system 
memory with 1 GB carved out for vram.  It would be a big waste not to 
use VRAM.  We'll probably need a heuristic at some point.



Alex


*From:* Christian König 
*Sent:* Tuesday, March 20, 2018 2:32:49 PM
*To:* Marek Olšák; Koenig, Christian
*Cc:* Alex Deucher; Deucher, Alexander; Michel Dänzer; Li, Samuel; 
amd-gfx list
*Subject:* Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display 
support

I don't think that is a good idea.

Ideally GTT should now have the same performance as VRAM on APUs and 
we should use VRAM only for things where we absolutely have to and to 
actually use up the otherwise unused VRAM.


Can you run some tests with all BOs forced to GTT and see if there is 
any performance regression?


Christian.

Am 20.03.2018 um 15:51 schrieb Marek Olšák:
On Tue, Mar 20, 2018 at 9:55 AM, Christian König 
> wrote:


Yes, exactly. And if I remember correctly Mesa used to always set
GTT as fallback on APUs, correct?


"used to" is the key part. Mesa doesn't force GTT on APUs anymore. It 
expects that the combination of BO priorities and BO move throttling 
will result in optimal BO placements over time.


Marek


The problem seems to be that this fallback isn't set for
displayable BOs.

So what needs to be done is to just enable this fallback for
displayable BOs as well if the kernel can handle it.

Christian.


Am 20.03.2018 um 00:01 schrieb Marek Olšák:

In theory, Mesa doesn't have to do anything. It can continue
setting VRAM and if the kernel has to put a display buffer into
GTT, it doesn't matter (for Mesa). Whether the VRAM placement is
really used is largely determined by BO priorities.

The way I understand scather/gather is that it only allows the
GTT placement. It doesn't force the GTT placement. Mesa also
doesn't force the GTT placement.

Marek

On Mon, Mar 19, 2018 at 5:12 PM, Alex Deucher
> wrote:

On Mon, Mar 19, 2018 at 4:29 PM, Li, Samuel
> wrote:
>>to my earlier point, there may be cases where it is
advantageous to put
>> display buffers in vram even if s/g display is supported
>
> Agreed. That is also why the patch has the options to let
user select where
> to put display buffers.
>
> As whether to put the option in Mesa or kernel, it seems
the difference is
> not much. Also, since amdgpufb can request even without
mesa, kernel might
> be a better choice. In addition, putting in the kernel can
save client’s
> duplicate work(mesa, ogl, vulkan, 2d, kernel…)

Why do we even expose different memory pools to the UMDs in
the first
place ;)  Each pool has performance characteristics that may be
relevant for a particular work load. Only the UMDs really
know the
finer points of those workloads. In general, you don't want
the kernel
dictating policy if you can avoid it. The kernel exposes
functionality and userspace sets the policy.  With the
location set in
userspace, each app/user can have whatever policy makes
sense for
their use case all at the same time without needing to tweak
their
kernel for every use case.

Alex



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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Deucher, Alexander]

I think we can also have the case of systems with similar amounts of carve out 
and system ram.  E.g., on a system with 4 GB of system memory with 1 GB carved 
out for vram.  It would be a big waste not to use VRAM.  We'll probably need a 
heuristic at some point.


Alex


From: Christian König 
Sent: Tuesday, March 20, 2018 2:32:49 PM
To: Marek Olšák; Koenig, Christian
Cc: Alex Deucher; Deucher, Alexander; Michel Dänzer; Li, Samuel; amd-gfx list
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

I don't think that is a good idea.

Ideally GTT should now have the same performance as VRAM on APUs and we should 
use VRAM only for things where we absolutely have to and to actually use up the 
otherwise unused VRAM.

Can you run some tests with all BOs forced to GTT and see if there is any 
performance regression?

Christian.

Am 20.03.2018 um 15:51 schrieb Marek Olšák:
On Tue, Mar 20, 2018 at 9:55 AM, Christian König 
> 
wrote:
Yes, exactly. And if I remember correctly Mesa used to always set GTT as 
fallback on APUs, correct?

"used to" is the key part. Mesa doesn't force GTT on APUs anymore. It expects 
that the combination of BO priorities and BO move throttling will result in 
optimal BO placements over time.

Marek


The problem seems to be that this fallback isn't set for displayable BOs.

So what needs to be done is to just enable this fallback for displayable BOs as 
well if the kernel can handle it.

Christian.


Am 20.03.2018 um 00:01 schrieb Marek Olšák:
In theory, Mesa doesn't have to do anything. It can continue setting VRAM and 
if the kernel has to put a display buffer into GTT, it doesn't matter (for 
Mesa). Whether the VRAM placement is really used is largely determined by BO 
priorities.

The way I understand scather/gather is that it only allows the GTT placement. 
It doesn't force the GTT placement. Mesa also doesn't force the GTT placement.

Marek

On Mon, Mar 19, 2018 at 5:12 PM, Alex Deucher 
> wrote:
On Mon, Mar 19, 2018 at 4:29 PM, Li, Samuel 
> wrote:
>>to my earlier point, there may be cases where it is advantageous to put
>> display buffers in vram even if s/g display is supported
>
> Agreed. That is also why the patch has the options to let user select where
> to put display buffers.
>
> As whether to put the option in Mesa or kernel, it seems the difference is
> not much. Also, since amdgpufb can request even without mesa, kernel might
> be a better choice. In addition, putting in the kernel can save client’s
> duplicate work(mesa, ogl, vulkan, 2d, kernel…)

Why do we even expose different memory pools to the UMDs in the first
place ;)  Each pool has performance characteristics that may be
relevant for a particular work load.  Only the UMDs really know the
finer points of those workloads. In general, you don't want the kernel
dictating policy if you can avoid it.  The kernel exposes
functionality and userspace sets the policy.  With the location set in
userspace, each app/user can have whatever policy makes sense for
their use case all at the same time without needing to tweak their
kernel for every use case.

Alex



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[PATCH 33/34] drm/amd/display: Only program MSA_TIMING_PARAM if it changed

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Harry Wentland 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 82ee9de23115..c18f24afa698 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1183,16 +1183,21 @@ static void enable_stream_features(struct pipe_ctx 
*pipe_ctx)
 {
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->sink->link;
-   union down_spread_ctrl downspread;
+   union down_spread_ctrl old_downspread;
+   union down_spread_ctrl new_downspread;
 
core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
-   , sizeof(downspread));
+   _downspread.raw, sizeof(old_downspread));
 
-   downspread.bits.IGNORE_MSA_TIMING_PARAM =
+   new_downspread.raw = old_downspread.raw;
+
+   new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
(stream->ignore_msa_timing_param) ? 1 : 0;
 
-   core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
-   , sizeof(downspread));
+   if (new_downspread.raw != old_downspread.raw) {
+   core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
+   _downspread.raw, sizeof(new_downspread));
+   }
 }
 
 static enum dc_status enable_link_dp(
-- 
2.14.1

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[PATCH 22/34] drm/amd/display: Separate mem input constuctors for dce 112 and 120

[Harry Wentland]

From: Mikita Lipski 

Override the memory input functions for dce120 not to program
new registers on dce112.
This will fix warnings thrown on Polaris asics.

Signed-off-by: Mikita Lipski 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 75 --
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  8 +++
 .../drm/amd/display/dc/dce120/dce120_resource.c|  2 +-
 3 files changed, 77 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 04fc86bb95a1..b235a75355b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -225,7 +225,7 @@ static void program_nbp_watermark(
}
 }
 
-static void program_stutter_watermark(
+static void dce120_program_stutter_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t stutter_mark,
@@ -244,6 +244,22 @@ static void program_stutter_watermark(
STUTTER_ENTER_SELF_REFRESH_WATERMARK, 
stutter_entry);
 }
 
+static void program_stutter_watermark(
+   struct dce_mem_input *dce_mi,
+   uint32_t wm_select,
+   uint32_t stutter_mark)
+{
+   REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
+   STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
+
+   if (REG(DPG_PIPE_STUTTER_CONTROL2))
+   REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,
+   STUTTER_EXIT_SELF_REFRESH_WATERMARK, 
stutter_mark);
+   else
+   REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
+   STUTTER_EXIT_SELF_REFRESH_WATERMARK, 
stutter_mark);
+}
+
 static void dce_mi_program_display_marks(
struct mem_input *mi,
struct dce_watermarks nbp,
@@ -266,8 +282,41 @@ static void dce_mi_program_display_marks(
program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
 
-   program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark, 
stutter_enter.a_mark); /* set a */
-   program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark, 
stutter_enter.d_mark); /* set d */
+   program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */
+   program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
+}
+
+static void dce112_mi_program_display_marks(struct mem_input *mi,
+   struct dce_watermarks nbp,
+   struct dce_watermarks stutter_exit,
+   struct dce_watermarks stutter_entry,
+   struct dce_watermarks urgent,
+   uint32_t total_dest_line_time_ns)
+{
+   struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
+   uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
+
+   program_urgency_watermark(dce_mi, 0, /* set a */
+   urgent.a_mark, total_dest_line_time_ns);
+   program_urgency_watermark(dce_mi, 1, /* set b */
+   urgent.b_mark, total_dest_line_time_ns);
+   program_urgency_watermark(dce_mi, 2, /* set c */
+   urgent.c_mark, total_dest_line_time_ns);
+   program_urgency_watermark(dce_mi, 3, /* set d */
+   urgent.d_mark, total_dest_line_time_ns);
+
+   REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
+   STUTTER_ENABLE, stutter_en,
+   STUTTER_IGNORE_FBC, 1);
+   program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */
+   program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */
+   program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
+   program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
+
+   program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark); /* set a */
+   program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark); /* set b */
+   program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark); /* set c */
+   program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark); /* set d */
 }
 
 static void dce120_mi_program_display_marks(struct mem_input *mi,
@@ -297,10 +346,10 @@ static void dce120_mi_program_display_marks(struct 
mem_input *mi,
program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
 
-   program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark, 
stutter_entry.a_mark); /* set a */
-   program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark, 
stutter_entry.b_mark); /* set b */
-   program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark, 
stutter_entry.c_mark); /* set c */
-   program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark, 
stutter_entry.d_mark); /* set d */
+   dce120_program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark, 
stutter_entry.a_mark); /* set a */
+   

[PATCH 29/34] drm/amd/display: Couple bug fixes in stats module

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Harry Wentland 
Reviewed-by: Harry Wentland 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/modules/stats/stats.c | 39 ---
 1 file changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index 041f87b73d5f..ed5f6809a64e 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -187,7 +187,7 @@ void mod_stats_dump(struct mod_stats *mod_stats)
 
for (int i = 0; i < core_stats->index && i < 
core_stats->entries; i++) {
dm_logger_write(logger, LOG_PROFILING,
-   "%u  %u  %u  %u  %u  %u  %u  %u  %u  %u 
 %u  %u  %u  %u  %u  %u  %u  %u  %u\n",
+   "%u  %u  %u  %u  %u  %u  %u  %u  %u  %u 
 %u  %u  %u  %u  %u  %u  %u  %u  %u",
time[i].render_time_in_us,
time[i].avg_render_time_in_us_last_ten,
time[i].min_window,
@@ -227,7 +227,7 @@ void mod_stats_reset_data(struct mod_stats *mod_stats)
memset(core_stats->time, 0,
sizeof(struct stats_time_cache) * core_stats->entries);
 
-   core_stats->index = 0;
+   core_stats->index = 1;
 }
 
 void mod_stats_update_flip(struct mod_stats *mod_stats,
@@ -250,7 +250,7 @@ void mod_stats_update_flip(struct mod_stats *mod_stats,
 
time[index].flip_timestamp_in_ns = timestamp_in_ns;
time[index].render_time_in_us =
-   timestamp_in_ns - time[index - 1].flip_timestamp_in_ns;
+   (timestamp_in_ns - time[index - 1].flip_timestamp_in_ns) / 1000;
 
if (index >= 10) {
for (unsigned int i = 0; i < 10; i++)
@@ -261,10 +261,12 @@ void mod_stats_update_flip(struct mod_stats *mod_stats,
 
if (time[index].num_vsync_between_flips > 0)
time[index].vsync_to_flip_time_in_us =
-   timestamp_in_ns - time[index].vupdate_timestamp_in_ns;
+   (timestamp_in_ns -
+   time[index].vupdate_timestamp_in_ns) / 1000;
else
time[index].vsync_to_flip_time_in_us =
-   timestamp_in_ns - time[index - 
1].vupdate_timestamp_in_ns;
+   (timestamp_in_ns -
+   time[index - 1].vupdate_timestamp_in_ns) / 1000;
 
core_stats->index++;
 }
@@ -275,6 +277,8 @@ void mod_stats_update_vupdate(struct mod_stats *mod_stats,
struct core_stats *core_stats = NULL;
struct stats_time_cache *time = NULL;
unsigned int index = 0;
+   unsigned int num_vsyncs = 0;
+   unsigned int prev_vsync_in_ns = 0;
 
if (mod_stats == NULL)
return;
@@ -286,14 +290,27 @@ void mod_stats_update_vupdate(struct mod_stats *mod_stats,
 
time = core_stats->time;
index = core_stats->index;
+   num_vsyncs = time[index].num_vsync_between_flips;
+
+   if (num_vsyncs < MOD_STATS_NUM_VSYNCS) {
+   if (num_vsyncs == 0) {
+   prev_vsync_in_ns =
+   time[index - 1].vupdate_timestamp_in_ns;
+
+   time[index].flip_to_vsync_time_in_us =
+   (timestamp_in_ns -
+   time[index - 1].flip_timestamp_in_ns) /
+   1000;
+   } else {
+   prev_vsync_in_ns =
+   time[index].vupdate_timestamp_in_ns;
+   }
 
-   time[index].vupdate_timestamp_in_ns = timestamp_in_ns;
-   if (time[index].num_vsync_between_flips < MOD_STATS_NUM_VSYNCS)
-   
time[index].v_sync_time_in_us[time[index].num_vsync_between_flips] =
-   timestamp_in_ns - time[index - 
1].vupdate_timestamp_in_ns;
-   time[index].flip_to_vsync_time_in_us =
-   timestamp_in_ns - time[index - 1].flip_timestamp_in_ns;
+   time[index].v_sync_time_in_us[num_vsyncs] =
+   (timestamp_in_ns - prev_vsync_in_ns) / 1000;
+   }
 
+   time[index].vupdate_timestamp_in_ns = timestamp_in_ns;
time[index].num_vsync_between_flips++;
 }
 
-- 
2.14.1

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[PATCH 34/34] drm/amd/display: Move commit_planes_to_stream to amdgpu_dm

[Harry Wentland]

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 108 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  89 --
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   7 --
 3 files changed, 103 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a97f278c4520..26d37f37f967 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4012,6 +4012,97 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
spin_unlock_irqrestore(>dev->event_lock, flags);
 }
 
+/*
+ * TODO this whole function needs to go
+ *
+ * dc_surface_update is needlessly complex. See if we can just replace this
+ * with a dc_plane_state and follow the atomic model a bit more closely here.
+ */
+static bool commit_planes_to_stream(
+   struct dc *dc,
+   struct dc_plane_state **plane_states,
+   uint8_t new_plane_count,
+   struct dm_crtc_state *dm_new_crtc_state,
+   struct dm_crtc_state *dm_old_crtc_state,
+   struct dc_state *state)
+{
+   /* no need to dynamically allocate this. it's pretty small */
+   struct dc_surface_update updates[MAX_SURFACES];
+   struct dc_flip_addrs *flip_addr;
+   struct dc_plane_info *plane_info;
+   struct dc_scaling_info *scaling_info;
+   int i;
+   struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
+   struct dc_stream_update *stream_update =
+   kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
+
+   if (!stream_update) {
+   BREAK_TO_DEBUGGER();
+   return false;
+   }
+
+   flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
+   GFP_KERNEL);
+   plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
+GFP_KERNEL);
+   scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
+  GFP_KERNEL);
+
+   if (!flip_addr || !plane_info || !scaling_info) {
+   kfree(flip_addr);
+   kfree(plane_info);
+   kfree(scaling_info);
+   kfree(stream_update);
+   return false;
+   }
+
+   memset(updates, 0, sizeof(updates));
+
+   stream_update->src = dc_stream->src;
+   stream_update->dst = dc_stream->dst;
+   stream_update->out_transfer_func = dc_stream->out_transfer_func;
+
+   for (i = 0; i < new_plane_count; i++) {
+   updates[i].surface = plane_states[i];
+   updates[i].gamma =
+   (struct dc_gamma *)plane_states[i]->gamma_correction;
+   updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
+   flip_addr[i].address = plane_states[i]->address;
+   flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
+   plane_info[i].color_space = plane_states[i]->color_space;
+   plane_info[i].input_tf = plane_states[i]->input_tf;
+   plane_info[i].format = plane_states[i]->format;
+   plane_info[i].plane_size = plane_states[i]->plane_size;
+   plane_info[i].rotation = plane_states[i]->rotation;
+   plane_info[i].horizontal_mirror = 
plane_states[i]->horizontal_mirror;
+   plane_info[i].stereo_format = plane_states[i]->stereo_format;
+   plane_info[i].tiling_info = plane_states[i]->tiling_info;
+   plane_info[i].visible = plane_states[i]->visible;
+   plane_info[i].per_pixel_alpha = 
plane_states[i]->per_pixel_alpha;
+   plane_info[i].dcc = plane_states[i]->dcc;
+   scaling_info[i].scaling_quality = 
plane_states[i]->scaling_quality;
+   scaling_info[i].src_rect = plane_states[i]->src_rect;
+   scaling_info[i].dst_rect = plane_states[i]->dst_rect;
+   scaling_info[i].clip_rect = plane_states[i]->clip_rect;
+
+   updates[i].flip_addr = _addr[i];
+   updates[i].plane_info = _info[i];
+   updates[i].scaling_info = _info[i];
+   }
+
+   dc_commit_updates_for_stream(
+   dc,
+   updates,
+   new_plane_count,
+   dc_stream, stream_update, plane_states, state);
+
+   kfree(flip_addr);
+   kfree(plane_info);
+   kfree(scaling_info);
+   kfree(stream_update);
+   return true;
+}
+
 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
struct drm_device *dev,
struct amdgpu_display_manager *dm,
@@ 

[PATCH 31/34] drm/amd/display: Add vline IRQ programming for DCN

[Harry Wentland]

From: SivapiriyanKumarasamy 

Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  6 ++
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  4 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c  | 76 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  | 14 
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  3 +
 drivers/gpu/drm/amd/display/dc/irq_types.h |  7 ++
 6 files changed, 110 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 63a3d468939a..554cf975be05 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1375,6 +1375,12 @@ static void commit_planes_for_stream(struct dc *dc,

pipe_ctx->stream_res.abm->funcs->set_abm_level(

pipe_ctx->stream_res.abm, stream->abm_level);
}
+
+   if (stream_update && 
stream_update->periodic_fn_vsync_delta &&
+   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
+   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
+   pipe_ctx->stream_res.tg, 
_ctx->stream->timing,
+   
pipe_ctx->stream->periodic_fn_vsync_delta);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 3a7093ede569..8d5161060b60 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -70,6 +70,9 @@ struct dc_stream_state {
enum color_transfer_func output_tf;
 
bool ignore_msa_timing_param;
+
+   unsigned long long periodic_fn_vsync_delta;
+
/* TODO: custom INFO packets */
/* TODO: ABM info (DMCU) */
/* PSR info */
@@ -113,6 +116,7 @@ struct dc_stream_update {
struct dc_hdr_static_metadata *hdr_static_metadata;
enum color_transfer_func color_output_tf;
unsigned int *abm_level;
+   unsigned long long *periodic_fn_vsync_delta;
 };
 
 bool dc_is_stream_unchanged(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 4bf64d1b2c60..f56eac0e4dd2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -93,6 +93,81 @@ static void optc1_disable_stereo(struct timing_generator 
*optc)
OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
 }
 
+static uint32_t get_start_vline(struct timing_generator *optc, const struct 
dc_crtc_timing *dc_crtc_timing)
+{
+   struct dc_crtc_timing patched_crtc_timing;
+   uint32_t vesa_sync_start;
+   uint32_t asic_blank_end;
+   uint32_t interlace_factor;
+   uint32_t vertical_line_start;
+
+   patched_crtc_timing = *dc_crtc_timing;
+   optc1_apply_front_porch_workaround(optc, _crtc_timing);
+
+   vesa_sync_start = patched_crtc_timing.h_addressable +
+   patched_crtc_timing.h_border_right +
+   patched_crtc_timing.h_front_porch;
+
+   asic_blank_end = patched_crtc_timing.h_total -
+   vesa_sync_start -
+   patched_crtc_timing.h_border_left;
+
+   interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
+
+   vesa_sync_start = patched_crtc_timing.v_addressable +
+   patched_crtc_timing.v_border_bottom +
+   patched_crtc_timing.v_front_porch;
+
+   asic_blank_end = (patched_crtc_timing.v_total -
+   vesa_sync_start -
+   patched_crtc_timing.v_border_top)
+   * interlace_factor;
+
+   vertical_line_start = asic_blank_end - 
optc->dlg_otg_param.vstartup_start + 1;
+   if (vertical_line_start < 0) {
+   ASSERT(0);
+   vertical_line_start = 0;
+   }
+
+   return vertical_line_start;
+}
+
+void optc1_program_vline_interrupt(
+   struct timing_generator *optc,
+   const struct dc_crtc_timing *dc_crtc_timing,
+   unsigned long long vsync_delta)
+{
+
+   struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+   unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 
), 1);
+   unsigned long long pix_clk_hundreds_khz = 
div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
+   uint32_t req_delta_lines = (uint32_t) div64_u64(
+   (req_delta_tens_of_usec * pix_clk_hundreds_khz + 
dc_crtc_timing->h_total - 1),
+

[PATCH 27/34] drm/amd/display: Add num_active_wb to DML

[Harry Wentland]

From: Eric Bernstein 

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index e296de6ca502..ce750edc1e5f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -224,6 +224,7 @@ struct  _vcs_dpi_display_output_params_st   {
int output_bpp;
int dsc_enable;
int wb_enable;
+   int num_active_wb;
int opp_input_bpc;
int output_type;
int output_format;
-- 
2.14.1

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[PATCH 01/34] drm/amd/display: correct the condition in setting cursor not visible beyond left edge

[Harry Wentland]

From: Martin Tsai 

Signed-off-by: Martin Tsai 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index e305c28c98de..3356125a6117 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -416,7 +416,7 @@ void dpp1_set_cursor_position(
if (src_x_offset >= (int)param->viewport_width)
cur_en = 0;  /* not visible beyond right edge*/
 
-   if (src_x_offset + (int)width < 0)
+   if (src_x_offset + (int)width <= 0)
cur_en = 0;  /* not visible beyond left edge*/
 
REG_UPDATE(CURSOR0_CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 39b72f696ae9..81b81e6efcd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -897,7 +897,7 @@ void hubp1_cursor_set_position(
if (src_x_offset >= (int)param->viewport_width)
cur_en = 0;  /* not visible beyond right edge*/
 
-   if (src_x_offset + (int)hubp->curs_attr.width < 0)
+   if (src_x_offset + (int)hubp->curs_attr.width <= 0)
cur_en = 0;  /* not visible beyond left edge*/
 
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
-- 
2.14.1

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[PATCH 03/34] drm/amd/display: Allow truncation to 10 bits

[Harry Wentland]

From: Mikita Lipski 

The truncation isn't being programmed if the truncation
depth is set to 2, it causes an issue with dce11.2 asic
using 6bit eDP panel. It required to truncate 12:10 in order to
perform spatial dither 10:6.

This change will allow 12:10 truncation to be enabled.

Signed-off-by: Mikita Lipski 
Reviewed-by: Jun Lei 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 3931412ab6d3..f19de13024f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -128,8 +128,7 @@ static void set_truncation(
return;
}
/* on other format-to do */
-   if (params->flags.TRUNCATE_ENABLED == 0 ||
-   params->flags.TRUNCATE_DEPTH == 2)
+   if (params->flags.TRUNCATE_ENABLED == 0)
return;
/*Set truncation depth and Enable truncation*/
REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
@@ -144,7 +143,7 @@ static void set_truncation(
 /**
  * set_spatial_dither
  * 1) set spatial dithering mode: pattern of seed
- * 2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp
+ * 2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
  * 3) set random seed
  * 4) set random mode
  * lfsr is reset every frame or not reset
-- 
2.14.1

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[PATCH 23/34] drm/amd/display: Only update mpc blend config if not full update

[Harry Wentland]

From: Eric Yang 

The current mpcc insert/remove logic does not support updating
only a single mpcc. So when pixel alpha changed but no full update
we can mistakenly shuffle the mpcc layering order. With this change
we will only insert/remove mpcc if there is full update.

Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  | 5 +++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 675a81a87099..27ae88e3a373 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1631,6 +1631,8 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx 
*pipe_ctx)
struct mpc *mpc = dc->res_pool->mpc;
struct mpc_tree *mpc_tree_params = 
&(pipe_ctx->stream_res.opp->mpc_tree_params);
 
+
+
/* TODO: proper fix once fpga works */
 
if (dc->debug.surface_visual_confirm)
@@ -1657,6 +1659,7 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx 
*pipe_ctx)
pipe_ctx->stream->output_color_space)
&& per_pixel_alpha;
 
+
/*
 * TODO: remove hack
 * Note: currently there is a bug in init_hw such that
@@ -1667,6 +1670,12 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx 
*pipe_ctx)
 */
mpcc_id = hubp->inst;
 
+   /* If there is no full update, don't need to touch MPC tree*/
+   if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
+   mpc->funcs->update_blending(mpc, _cfg, mpcc_id);
+   return;
+   }
+
/* check if this MPCC is already being used */
new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
/* remove MPCC if being used */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 6f7016a2a11e..9ca51ae46de7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -65,6 +65,7 @@ static void mpc1_update_blending(
int mpcc_id)
 {
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+   struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
 
REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
MPCC_ALPHA_BLND_MODE,   blnd_cfg->alpha_mode,
@@ -74,6 +75,7 @@ static void mpc1_update_blending(
MPCC_GLOBAL_GAIN,   blnd_cfg->global_gain);
 
mpc1_set_bg_color(mpc, _cfg->black_color, mpcc_id);
+   mpcc->blnd_cfg = *blnd_cfg;
 }
 
 void mpc1_update_stereo_mix(
@@ -235,8 +237,7 @@ struct mpcc *mpc1_insert_plane(
}
 
/* update the blending configuration */
-   new_mpcc->blnd_cfg = *blnd_cfg;
-   mpc->funcs->update_blending(mpc, _mpcc->blnd_cfg, mpcc_id);
+   mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
 
/* update the stereo mix settings, if provided */
if (sm_cfg != NULL) {
-- 
2.14.1

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[PATCH 24/34] drm/amd/display: hide inconsistent mpcc programming from dtn log

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 27ae88e3a373..e21458169d15 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -157,10 +157,11 @@ void dcn10_log_hw_state(struct dc *dc)
struct mpcc_state s = {0};
 
pool->mpc->funcs->read_mpcc_state(pool->mpc, i, );
-   DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  
%4d\n",
-   i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
-   s.mode, s.alpha_mode, s.pre_multiplied_alpha, 
s.overlap_only,
-   s.idle);
+   if (s.opp_id != 0xf)
+   DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  
%12d  %4d\n",
+   i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
+   s.mode, s.alpha_mode, s.pre_multiplied_alpha, 
s.overlap_only,
+   s.idle);
}
DTN_INFO("\n");
 
-- 
2.14.1

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[PATCH 10/34] drm/amd/display: Rename feature-specific register address init macro

[Harry Wentland]

From: Nikola Cornij 

Signed-off-by: Nikola Cornij 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index c794ce4a8177..e0d6d32357c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -95,8 +95,8 @@
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
SRI(HUBP_CLK_CNTL, HUBP, id)
 
-/* Register address initialization macro for "generic" ASICs with full 
functionality */
-#define HUBP_REG_LIST_DCN_GEN(id)\
+/* Register address initialization macro for ASICs with VM */
+#define HUBP_REG_LIST_DCN_VM(id)\
SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
@@ -105,7 +105,7 @@
 
 #define HUBP_REG_LIST_DCN10(id)\
HUBP_REG_LIST_DCN(id),\
-   HUBP_REG_LIST_DCN_GEN(id),\
+   HUBP_REG_LIST_DCN_VM(id),\
SRI(PREFETCH_SETTINS, HUBPREQ, id),\
SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
@@ -361,8 +361,8 @@
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, 
mask_sh),\
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
 
-/* Mask/shift struct generation macro for "generic" ASICs with full 
functionality */
-#define HUBP_MASK_SH_LIST_DCN_GEN(mask_sh)\
+/* Mask/shift struct generation macro for ASICs with VM */
+#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, 
mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
@@ -372,7 +372,7 @@
 
 #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
HUBP_MASK_SH_LIST_DCN(mask_sh),\
-   HUBP_MASK_SH_LIST_DCN_GEN(mask_sh),\
+   HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
-- 
2.14.1

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[PATCH 14/34] drm/amd/display: Don't call amdgpu_dm_display_resume as it doesn't exist

[Harry Wentland]

From: Mikita Lipski 

amdgpu_dm_display_resume was merged into dm_resume.
No need to call these functions separately.

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 896542418330..a97f278c4520 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1632,7 +1632,6 @@ static ssize_t s3_debug_store(struct device *device,
if (ret == 0) {
if (s3_state) {
dm_resume(adev);
-   amdgpu_dm_display_resume(adev);
drm_kms_helper_hotplug_event(adev->ddev);
} else
dm_suspend(adev);
-- 
2.14.1

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[PATCH 00/34] DC Patches Mar 20, 2018

[Harry Wentland]

 * Fix multi-channel audio
 * Fix banding on 6 bit eDP panels with Polaris
 * Fix Polaris 12 BW calcs
 * Drop EDID read during atomic_check (for MST)

Anthony Koo (3):
  drm/amd/display: Couple bug fixes in stats module
  drm/amd/display: Rename encoder_info_packet to dc_info_packet
  drm/amd/display: Only program MSA_TIMING_PARAM if it changed

Bhawanpreet Lakha (2):
  drm/amd/display: Add debug prints for bandwidth calculations
  drm/amd/display: Correct print types in DC_LOGS

Dmytro Laktyushkin (4):
  drm/amd/display: fix lexa bw bounding box
  drm/amd/display: add mpc to dtn log
  drm/amd/display: align dtn logs and add mpc idle bit print
  drm/amd/display: hide inconsistent mpcc programming from dtn log

Eric Bernstein (2):
  drm/amd/display: Change wb_h/vratio to double
  drm/amd/display: Add num_active_wb to DML

Eric Yang (1):
  drm/amd/display: Only update mpc blend config if not full update

Harry Wentland (4):
  drm/amd/display: We shouldn't set format_default on plane as atomic
driver
  drm/amd/display: Add one to EDID's audio channel count when passing to
DC
  drm/amd/display: Don't read EDID in atomic_check
  drm/amd/display: Move commit_planes_to_stream to amdgpu_dm

Julian Parkin (1):
  drm/amd/display: drop dc_validate_guaranteed

Martin Tsai (1):
  drm/amd/display: correct the condition in setting cursor not visible
beyond left edge

Mikita Lipski (6):
  drm/amd/display: Allow truncation to 10 bits
  drm/amd/display: Fix FMT truncation programming
  drm/amd/display: Don't call amdgpu_dm_display_resume as it doesn't
exist
  drm/amd/display: Adding stutter entry wm to dce bw struct
  drm/amd/display: Implementing new bandwidth registers for DCE120
  drm/amd/display: Separate mem input constuctors for dce 112 and 120

Nikola Cornij (2):
  drm/amd/display: Update ASIC header files
  drm/amd/display: Rename feature-specific register address init macro

Roman Li (1):
  drm/amd/display: add assert in enable FBC

SivapiriyanKumarasamy (1):
  drm/amd/display: Add vline IRQ programming for DCN

Tony Cheng (2):
  drm/amd/display: dal 3.1.39
  drm/amd/display: dal 3.1.40

Vitaly Prosyak (1):
  drm/amd/display: Add dc_lut_mode enum

Xingyue Tao (2):
  drm/amd/display: Add double buffer machanism to ICSC
  drm/amd/display: Add double buffer machanism to OCSC

Yongqiang Sun (1):
  drm/amd/display: Retry when read dpcd caps failed.

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 111 +++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c|  32 +-
 .../gpu/drm/amd/display/dc/calcs/calcs_logger.h| 579 +
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c   | 238 -
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  74 +--
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  95 +---
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c |  14 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  23 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  16 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 131 ++---
 drivers/gpu/drm/amd/display/dc/dc.h|   3 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  19 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h  |   9 +
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 103 +++-
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  17 +
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c   |   9 +-
 .../drm/amd/display/dc/dce/dce_stream_encoder.c|   4 +-
 .../drm/amd/display/dc/dce100/dce100_resource.c|  33 --
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  10 +-
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c |   1 +
 .../drm/amd/display/dc/dce110/dce110_resource.c|  33 --
 .../drm/amd/display/dc/dce112/dce112_resource.c|  33 --
 .../drm/amd/display/dc/dce112/dce112_resource.h|   5 -
 .../drm/amd/display/dc/dce120/dce120_resource.c|   3 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |  49 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |   9 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  47 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c|  90 ++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  |  22 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h  |  32 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  58 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  24 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   5 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c  |  76 +++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  |  14 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  36 +-
 .../drm/amd/display/dc/dml/display_mode_structs.h  |   5 +-
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.c|   2 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   6 +-
 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h  |   5 +
 

[PATCH 32/34] drm/amd/display: Add double buffer machanism to OCSC

[Harry Wentland]

From: Xingyue Tao 

- Added double buffer mechanism to output CSC
so that there's no tearing when adjusting brightness
from Radeon settings

Signed-off-by: Xingyue Tao 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 36 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 46 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 32 ++-
 3 files changed, 67 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index b81b2aa3c49f..9b5ff76a8027 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -420,6 +420,41 @@
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
 
+/*
+ *
+   DCN1 CM debug status register definition
+
+   register :ID9_CM_STATUS do
+   implement_ref :cm
+   map to:  :cmdebugind, at: j
+   width 32
+   disclosure   NEVER
+
+   field :ID9_VUPDATE_CFG, [0], R
+   field :ID9_IGAM_LUT_MODE, [2..1], R
+   field :ID9_BNS_BYPASS, [3], R
+   field :ID9_ICSC_MODE, [5..4], R
+   field :ID9_DGAM_LUT_MODE, [8..6], R
+   field :ID9_HDR_BYPASS, [9], R
+   field :ID9_GAMUT_REMAP_MODE, [11..10], R
+   field :ID9_RGAM_LUT_MODE, [14..12], R
+   #1 free bit
+   field :ID9_OCSC_MODE, [18..16], R
+   field :ID9_DENORM_MODE, [21..19], R
+   field :ID9_ROUND_TRUNC_MODE, [25..22], R
+   field :ID9_DITHER_EN, [26], R
+   field :ID9_DITHER_MODE, [28..27], R
+   end
+*/
+
+#define TF_DEBUG_REG_LIST_SH_DCN10 \
+   .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
+   .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
+
+#define TF_DEBUG_REG_LIST_MASK_DCN10 \
+   .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
+   .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x7
+
 #define TF_REG_FIELD_LIST(type) \
type EXT_OVERSCAN_LEFT; \
type EXT_OVERSCAN_RIGHT; \
@@ -1015,6 +1050,7 @@
type CM_BYPASS; \
type CM_TEST_DEBUG_INDEX; \
type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
+   type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
type FORMAT_CONTROL__ALPHA_EN; \
type CUR0_COLOR0; \
type CUR0_COLOR1; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index cc511415caee..4f373c97804f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -216,41 +216,55 @@ static void dpp1_cm_program_color_matrix(
struct dcn10_dpp *dpp,
const uint16_t *regval)
 {
-   uint32_t mode;
+   uint32_t ocsc_mode;
+   uint32_t cur_mode;
struct color_matrices_reg gam_regs;
 
-   REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, );
-
if (regval == NULL) {
BREAK_TO_DEBUGGER();
return;
}
-   mode = 4;
+
+   /* determine which CSC matrix (ocsc or comb) we are using
+* currently.  select the alternate set to double buffer
+* the CSC update so CSC is updated on frame boundary
+*/
+   REG_SET(CM_TEST_DEBUG_INDEX, 0,
+   CM_TEST_DEBUG_INDEX, 9);
+
+   REG_GET(CM_TEST_DEBUG_DATA,
+   CM_TEST_DEBUG_DATA_ID9_OCSC_MODE, _mode);
+
+   if (cur_mode != 4)
+   ocsc_mode = 4;
+   else
+   ocsc_mode = 5;
+
+
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
gam_regs.masks.csc_c11  = dpp->tf_mask->CM_OCSC_C11;
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
 
-   if (mode == 4) {
+   if (ocsc_mode == 4) {
 
gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
 
-   cm_helper_program_color_matrices(
-   dpp->base.ctx,
-   regval,
-   _regs);
-
} else {
 
gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
 
-   cm_helper_program_color_matrices(
-   dpp->base.ctx,
-   regval,
-   _regs);
}
+
+   cm_helper_program_color_matrices(
+   dpp->base.ctx,
+   regval,
+   _regs);
+
+   REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
+
 }
 
 void dpp1_cm_set_output_csc_default(

[PATCH 18/34] drm/amd/display: Implementing new bandwidth registers for DCE120

[Harry Wentland]

From: Mikita Lipski 

Registers are added and defined.
Programmed to default values.
Stutter level watermark register is being set to calculated value.
Urgent level registers are programmed to the same as urgency.
The programming of the registers is not expected to have any
functional difference in performance.

Signed-off-by: Mikita Lipski 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 58 +++---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  9 
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  3 ++
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |  1 +
 5 files changed, 55 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 0790f25c7b3b..04fc86bb95a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -174,6 +174,25 @@ static void program_urgency_watermark(
URGENCY_HIGH_WATERMARK, urgency_high_wm);
 }
 
+static void dce120_program_urgency_watermark(
+   struct dce_mem_input *dce_mi,
+   uint32_t wm_select,
+   uint32_t urgency_low_wm,
+   uint32_t urgency_high_wm)
+{
+   REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
+   URGENCY_WATERMARK_MASK, wm_select);
+
+   REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
+   URGENCY_LOW_WATERMARK, urgency_low_wm,
+   URGENCY_HIGH_WATERMARK, urgency_high_wm);
+
+   REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0,
+   URGENT_LEVEL_LOW_WATERMARK, urgency_low_wm,
+   URGENT_LEVEL_HIGH_WATERMARK, urgency_high_wm);
+
+}
+
 static void program_nbp_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
@@ -209,23 +228,27 @@ static void program_nbp_watermark(
 static void program_stutter_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
-   uint32_t stutter_mark)
+   uint32_t stutter_mark,
+   uint32_t stutter_entry)
 {
REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
 
if (REG(DPG_PIPE_STUTTER_CONTROL2))
-   REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,
-   STUTTER_EXIT_SELF_REFRESH_WATERMARK, 
stutter_mark);
+   REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2,
+   STUTTER_EXIT_SELF_REFRESH_WATERMARK, 
stutter_mark,
+   STUTTER_ENTER_SELF_REFRESH_WATERMARK, 
stutter_entry);
else
-   REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
-   STUTTER_EXIT_SELF_REFRESH_WATERMARK, 
stutter_mark);
+   REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
+   STUTTER_EXIT_SELF_REFRESH_WATERMARK, 
stutter_mark,
+   STUTTER_ENTER_SELF_REFRESH_WATERMARK, 
stutter_entry);
 }
 
 static void dce_mi_program_display_marks(
struct mem_input *mi,
struct dce_watermarks nbp,
-   struct dce_watermarks stutter,
+   struct dce_watermarks stutter_exit,
+   struct dce_watermarks stutter_enter,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
 {
@@ -243,26 +266,27 @@ static void dce_mi_program_display_marks(
program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
 
-   program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */
-   program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */
+   program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark, 
stutter_enter.a_mark); /* set a */
+   program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark, 
stutter_enter.d_mark); /* set d */
 }
 
 static void dce120_mi_program_display_marks(struct mem_input *mi,
struct dce_watermarks nbp,
-   struct dce_watermarks stutter,
+   struct dce_watermarks stutter_exit,
+   struct dce_watermarks stutter_entry,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
 {
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
 
-   program_urgency_watermark(dce_mi, 0, /* set a */
+   dce120_program_urgency_watermark(dce_mi, 0, /* set a */
urgent.a_mark, total_dest_line_time_ns);
-   program_urgency_watermark(dce_mi, 1, /* set b */
+   dce120_program_urgency_watermark(dce_mi, 1, /* set b */
urgent.b_mark, total_dest_line_time_ns);
-   program_urgency_watermark(dce_mi, 2, /* set c */
+   dce120_program_urgency_watermark(dce_mi, 2, /* set c */

[PATCH 09/34] drm/amd/display: fix lexa bw bounding box

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Bhawanpreet Lakha 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 121 ++-
 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h   |   1 +
 2 files changed, 120 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 0cbab81ab304..3d05e82652af 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -52,10 +52,11 @@ static enum bw_calcs_version 
bw_calcs_version_from_asic_id(struct hw_asic_id asi
return BW_CALCS_VERSION_CARRIZO;
 
case FAMILY_VI:
+   if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
+   return BW_CALCS_VERSION_LEXA;
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS10;
-   if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
-   
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
+   if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS11;
return BW_CALCS_VERSION_INVALID;
 
@@ -2373,6 +2374,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
break;
+   case BW_CALCS_VERSION_LEXA:
+   vbios.memory_type = bw_def_gddr5;
+   vbios.dram_channel_width_in_bits = 32;
+   vbios.number_of_dram_channels = asic_id.vram_width / 
vbios.dram_channel_width_in_bits;
+   vbios.number_of_dram_banks = 8;
+   vbios.high_yclk = bw_int_to_fixed(6000);
+   vbios.mid_yclk = bw_int_to_fixed(3200);
+   vbios.low_yclk = bw_int_to_fixed(1000);
+   vbios.low_sclk = bw_int_to_fixed(678);
+   vbios.mid1_sclk = bw_int_to_fixed(864);
+   vbios.mid2_sclk = bw_int_to_fixed(900);
+   vbios.mid3_sclk = bw_int_to_fixed(920);
+   vbios.mid4_sclk = bw_int_to_fixed(940);
+   vbios.mid5_sclk = bw_int_to_fixed(960);
+   vbios.mid6_sclk = bw_int_to_fixed(980);
+   vbios.high_sclk = bw_int_to_fixed(1049);
+   vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
+   vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
+   vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
+   vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
+   vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
+   vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
+   vbios.data_return_bus_width = bw_int_to_fixed(32);
+   vbios.trc = bw_int_to_fixed(48);
+   if (vbios.number_of_dram_channels == 2) // 64-bit
+   vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
+   else
+   vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
+   vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
+   vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
+   vbios.nbp_state_change_latency = bw_int_to_fixed(250);
+   vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
+   vbios.scatter_gather_enable = false;
+   vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
+   vbios.cursor_width = 32;
+   vbios.average_compression_rate = 4;
+   vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel 
= 256;
+   vbios.blackout_duration = bw_int_to_fixed(0); /* us */
+   vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
+
+   
dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation
 = 100;
+   
dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation
 = 100;
+   dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 
100;
+   dceip.large_cursor = false;
+   dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
+   dceip.dmif_pipe_en_fbc_chunk_tracker = false;
+   dceip.cursor_max_outstanding_group_num = 1;
+   dceip.lines_interleaved_into_lb = 2;
+   dceip.chunk_width = 256;
+   dceip.number_of_graphics_pipes = 5;
+   dceip.number_of_underlay_pipes = 0;
+   dceip.low_power_tiling_mode = 0;
+   dceip.display_write_back_supported = true;
+   

[PATCH 26/34] drm/amd/display: Correct print types in DC_LOGS

[Harry Wentland]

From: Bhawanpreet Lakha 

Correct the types used for printing in logs. This is needed for adding
dynamic printing (LINUX), otherwise we get warnings.

Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   | 74 +++---
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 14 ++--
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  8 +--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  4 +-
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.c|  2 +-
 5 files changed, 52 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 4bb43a371292..a102c192328d 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1459,39 +1459,39 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
 {
kernel_fpu_begin();
-   DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %d ns\n"
-   "sr_enter_plus_exit_time: %d ns\n"
-   "urgent_latency: %d ns\n"
-   "write_back_latency: %d ns\n"
-   "percent_of_ideal_drambw_received_after_urg_latency: %d 
%\n"
+   DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
+   "sr_enter_plus_exit_time: %f ns\n"
+   "urgent_latency: %f ns\n"
+   "write_back_latency: %f ns\n"
+   "percent_of_ideal_drambw_received_after_urg_latency: %f 
%%\n"
"max_request_size: %d bytes\n"
-   "dcfclkv_max0p9: %d kHz\n"
-   "dcfclkv_nom0p8: %d kHz\n"
-   "dcfclkv_mid0p72: %d kHz\n"
-   "dcfclkv_min0p65: %d kHz\n"
-   "max_dispclk_vmax0p9: %d kHz\n"
-   "max_dispclk_vnom0p8: %d kHz\n"
-   "max_dispclk_vmid0p72: %d kHz\n"
-   "max_dispclk_vmin0p65: %d kHz\n"
-   "max_dppclk_vmax0p9: %d kHz\n"
-   "max_dppclk_vnom0p8: %d kHz\n"
-   "max_dppclk_vmid0p72: %d kHz\n"
-   "max_dppclk_vmin0p65: %d kHz\n"
-   "socclk: %d kHz\n"
-   "fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
-   "fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
-   "fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
-   "fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
-   "phyclkv_max0p9: %d kHz\n"
-   "phyclkv_nom0p8: %d kHz\n"
-   "phyclkv_mid0p72: %d kHz\n"
-   "phyclkv_min0p65: %d kHz\n"
-   "downspreading: %d %\n"
+   "dcfclkv_max0p9: %f kHz\n"
+   "dcfclkv_nom0p8: %f kHz\n"
+   "dcfclkv_mid0p72: %f kHz\n"
+   "dcfclkv_min0p65: %f kHz\n"
+   "max_dispclk_vmax0p9: %f kHz\n"
+   "max_dispclk_vnom0p8: %f kHz\n"
+   "max_dispclk_vmid0p72: %f kHz\n"
+   "max_dispclk_vmin0p65: %f kHz\n"
+   "max_dppclk_vmax0p9: %f kHz\n"
+   "max_dppclk_vnom0p8: %f kHz\n"
+   "max_dppclk_vmid0p72: %f kHz\n"
+   "max_dppclk_vmin0p65: %f kHz\n"
+   "socclk: %f kHz\n"
+   "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
+   "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
+   "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
+   "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
+   "phyclkv_max0p9: %f kHz\n"
+   "phyclkv_nom0p8: %f kHz\n"
+   "phyclkv_mid0p72: %f kHz\n"
+   "phyclkv_min0p65: %f kHz\n"
+   "downspreading: %f %%\n"
"round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
"urgent_out_of_order_return_per_channel: %d Bytes\n"
"number_of_channels: %d\n"
"vmm_page_size: %d Bytes\n"
-   "dram_clock_change_latency: %d ns\n"
+   "dram_clock_change_latency: %f ns\n"
"return_bus_width: %d Bytes\n",
dc->dcn_soc->sr_exit_time * 1000,
dc->dcn_soc->sr_enter_plus_exit_time * 1000,
@@ -1527,11 +1527,11 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
dc->dcn_soc->vmm_page_size,

[PATCH 05/34] drm/amd/display: We shouldn't set format_default on plane as atomic driver

[Harry Wentland]

This is still a leftover from early atomic brinup days.

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9e2cdc97dc89..896542418330 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3199,8 +3199,6 @@ static int amdgpu_dm_plane_init(struct 
amdgpu_display_manager *dm,
 
switch (aplane->base.type) {
case DRM_PLANE_TYPE_PRIMARY:
-   aplane->base.format_default = true;
-
res = drm_universal_plane_init(
dm->adev->ddev,
>base,
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 30/34] drm/amd/display: Rename encoder_info_packet to dc_info_packet

[Harry Wentland]

From: Anthony Koo 

Move this out of the HW includes to dc_types.h

Signed-off-by: Harry Wentland 
Reviewed-by: Harry Wentland 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 99 +++---
 drivers/gpu/drm/amd/display/dc/dc_types.h  |  9 ++
 .../drm/amd/display/dc/dce/dce_stream_encoder.c|  4 +-
 .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 21 ++---
 4 files changed, 65 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index cae78ee9a6fc..379b05536321 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1811,7 +1811,7 @@ enum dc_status dc_validate_global_state(
 }
 
 static void patch_gamut_packet_checksum(
-   struct encoder_info_packet *gamut_packet)
+   struct dc_info_packet *gamut_packet)
 {
/* For gamut we recalc checksum */
if (gamut_packet->valid) {
@@ -1830,12 +1830,11 @@ static void patch_gamut_packet_checksum(
 }
 
 static void set_avi_info_frame(
-   struct encoder_info_packet *info_packet,
+   struct dc_info_packet *info_packet,
struct pipe_ctx *pipe_ctx)
 {
struct dc_stream_state *stream = pipe_ctx->stream;
enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
-   struct info_frame info_frame = { {0} };
uint32_t pixel_encoding = 0;
enum scanning_type scan_type = SCANNING_TYPE_NODATA;
enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
@@ -1845,7 +1844,7 @@ static void set_avi_info_frame(
unsigned int cn0_cn1_value = 0;
uint8_t *check_sum = NULL;
uint8_t byte_index = 0;
-   union hdmi_info_packet *hdmi_info = 
_frame.avi_info_packet.info_packet_hdmi;
+   union hdmi_info_packet hdmi_info = {0};
union display_content_support support = {0};
unsigned int vic = pipe_ctx->stream->timing.vic;
enum dc_timing_3d_format format;
@@ -1856,11 +1855,11 @@ static void set_avi_info_frame(
COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
 
/* Initialize header */
-   hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
+   hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
* not be used in HDMI 2.0 (Section 10.1) */
-   hdmi_info->bits.header.version = 2;
-   hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
+   hdmi_info.bits.header.version = 2;
+   hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
 
/*
 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
@@ -1886,39 +1885,39 @@ static void set_avi_info_frame(
 
/* Y0_Y1_Y2 : The pixel encoding */
/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
-   hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
+   hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
 
/* A0 = 1 Active Format Information valid */
-   hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
+   hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
 
/* B0, B1 = 3; Bar info data is valid */
-   hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
+   hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
 
-   hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
+   hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
 
/* S0, S1 : Underscan / Overscan */
/* TODO: un-hardcode scan type */
scan_type = SCANNING_TYPE_UNDERSCAN;
-   hdmi_info->bits.S0_S1 = scan_type;
+   hdmi_info.bits.S0_S1 = scan_type;
 
/* C0, C1 : Colorimetry */
if (color_space == COLOR_SPACE_YCBCR709 ||
color_space == COLOR_SPACE_YCBCR709_LIMITED)
-   hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
+   hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
else if (color_space == COLOR_SPACE_YCBCR601 ||
color_space == COLOR_SPACE_YCBCR601_LIMITED)
-   hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
+   hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
else {
-   hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
+   hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
}
if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
color_space == COLOR_SPACE_2020_YCBCR) {
-   hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
-   hdmi_info->bits.C0_C1   = COLORIMETRY_EXTENDED;
+   hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
+   hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
} else if (color_space 

[PATCH 28/34] drm/amd/display: Add double buffer machanism to ICSC

[Harry Wentland]

From: Xingyue Tao 

- Video playback shows tearing when adjusting
brightness through radeon custom settings.
- Now added double buffer mechanism to switch
input CSC from register buffer ICSC and COMA
- Improved tab alignment

Signed-off-by: Xingyue Tao 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 11 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 44 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 31 ++-
 3 files changed, 67 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 17b062a8f88a..b81b2aa3c49f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -108,6 +108,8 @@
SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(CM_DGAM_CONTROL, CM, id), \
+   SRI(CM_TEST_DEBUG_INDEX, CM, id), \
+   SRI(CM_TEST_DEBUG_DATA, CM, id), \
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
@@ -300,6 +302,7 @@
TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
+   TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
@@ -1010,6 +1013,8 @@
type CUR0_EXPANSION_MODE; \
type CUR0_ENABLE; \
type CM_BYPASS; \
+   type CM_TEST_DEBUG_INDEX; \
+   type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
type FORMAT_CONTROL__ALPHA_EN; \
type CUR0_COLOR0; \
type CUR0_COLOR1; \
@@ -1255,6 +1260,8 @@ struct dcn_dpp_mask {
uint32_t CM_IGAM_LUT_RW_CONTROL; \
uint32_t CM_IGAM_LUT_RW_INDEX; \
uint32_t CM_IGAM_LUT_SEQ_COLOR; \
+   uint32_t CM_TEST_DEBUG_INDEX; \
+   uint32_t CM_TEST_DEBUG_DATA; \
uint32_t FORMAT_CONTROL; \
uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
uint32_t CURSOR_CONTROL; \
@@ -1289,8 +1296,8 @@ struct dcn10_dpp {
 
 enum dcn10_input_csc_select {
INPUT_CSC_SELECT_BYPASS = 0,
-   INPUT_CSC_SELECT_ICSC,
-   INPUT_CSC_SELECT_COMA
+   INPUT_CSC_SELECT_ICSC = 1,
+   INPUT_CSC_SELECT_COMA = 2
 };
 
 void dpp1_set_cursor_attributes(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index fb32975e4b67..cc511415caee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -267,6 +267,7 @@ void dpp1_cm_set_output_csc_default(
BREAK_TO_DEBUGGER();
return;
}
+
dpp1_cm_program_color_matrix(dpp, regval);
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 }
@@ -330,6 +331,7 @@ void dpp1_cm_set_output_csc_adjustment(
 {
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
uint32_t ocsc_mode = 4;
+
dpp1_cm_program_color_matrix(dpp, regval);
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 }
@@ -437,17 +439,18 @@ void dpp1_cm_program_regamma_lutb_settings(
 void dpp1_program_input_csc(
struct dpp *dpp_base,
enum dc_color_space color_space,
-   enum dcn10_input_csc_select select,
+   enum dcn10_input_csc_select input_select,
const struct out_csc_color_matrix *tbl_entry)
 {
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
int i;
int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct 
dcn10_input_csc_matrix);
const uint16_t *regval = NULL;
-   uint32_t selection = 1;
+   uint32_t cur_select = 0;
+   enum dcn10_input_csc_select select;
struct color_matrices_reg gam_regs;
 
-   if (select == INPUT_CSC_SELECT_BYPASS) {
+   if (input_select == INPUT_CSC_SELECT_BYPASS) {
REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
return;
}
@@ -467,36 +470,45 @@ void dpp1_program_input_csc(
regval = tbl_entry->regval;
}
 
-   if (select == INPUT_CSC_SELECT_COMA)
-   selection = 2;
-   REG_SET(CM_ICSC_CONTROL, 0,
-   CM_ICSC_MODE, selection);
+   /* determine which CSC matrix (icsc or coma) we are using
+* currently.  select the alternate set to double buffer
+* the CSC update so CSC is updated on frame boundary
+*/
+   REG_SET(CM_TEST_DEBUG_INDEX, 0,
+   

[PATCH 07/34] drm/amd/display: Add one to EDID's audio channel count when passing to DC

[Harry Wentland]

DC takes channel count to mean the actual count. cea_sad's channels
represent it as number of channels - 1.

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 9ab69b22b989..ca0b08bfa2cf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -109,7 +109,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
struct cea_sad *sad = [i];
 
edid_caps->audio_modes[i].format_code = sad->format;
-   edid_caps->audio_modes[i].channel_count = sad->channels;
+   edid_caps->audio_modes[i].channel_count = sad->channels + 1;
edid_caps->audio_modes[i].sample_rate = sad->freq;
edid_caps->audio_modes[i].sample_size = sad->byte2;
}
-- 
2.14.1

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[PATCH 16/34] drm/amd/display: Change wb_h/vratio to double

[Harry Wentland]

From: Eric Bernstein 

Signed-off-by: Eric Bernstein 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 09affa16cc43..e296de6ca502 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -215,8 +215,8 @@ struct writeback_st {
int wb_vtaps_luma;
int wb_htaps_chroma;
int wb_vtaps_chroma;
-   int wb_hratio;
-   int wb_vratio;
+   double wb_hratio;
+   double wb_vratio;
 };
 
 struct _vcs_dpi_display_output_params_st   {
-- 
2.14.1

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[PATCH 06/34] drm/amd/display: Retry when read dpcd caps failed.

[Harry Wentland]

From: Yongqiang Sun 

Some DP panel not detected intermittently due to read dpcd
caps failed when doing hot plug.
[root cause] DC_HPD_CONNECT_INT_DELAY is set to 0, not delay
after HPD toggle and read dpcd data, while some panel need 4ms defer
to read.
[solution] Add a retry when read failed.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 3b5053570229..b86325bb636f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2278,6 +2278,8 @@ static bool retrieve_link_cap(struct dc_link *link)
union edp_configuration_cap edp_config_cap;
union dp_downstream_port_present ds_port = { 0 };
enum dc_status status = DC_ERROR_UNEXPECTED;
+   uint32_t read_dpcd_retry_cnt = 3;
+   int i;
 
memset(dpcd_data, '\0', sizeof(dpcd_data));
memset(_strm_port_count,
@@ -2285,11 +2287,15 @@ static bool retrieve_link_cap(struct dc_link *link)
memset(_config_cap, '\0',
sizeof(union edp_configuration_cap));
 
-   status = core_link_read_dpcd(
-   link,
-   DP_DPCD_REV,
-   dpcd_data,
-   sizeof(dpcd_data));
+   for (i = 0; i < read_dpcd_retry_cnt; i++) {
+   status = core_link_read_dpcd(
+   link,
+   DP_DPCD_REV,
+   dpcd_data,
+   sizeof(dpcd_data));
+   if (status == DC_OK)
+   break;
+   }
 
if (status != DC_OK) {
dm_error("%s: Read dpcd data failed.\n", __func__);
-- 
2.14.1

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[PATCH 21/34] drm/amd/display: add assert in enable FBC

[Harry Wentland]

From: Roman Li 

Adding assert to prevent possible null deref warning.
Only can happen under abnormal circumstances.

Signed-off-by: Roman Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index daa4673675f1..075ab291cdc7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1801,6 +1801,9 @@ static bool should_enable_fbc(struct dc *dc,
}
}
 
+   /* Pipe context should be found */
+   ASSERT(pipe_ctx);
+
/* Only supports eDP */
if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
return false;
-- 
2.14.1

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[PATCH 15/34] drm/amd/display: Adding stutter entry wm to dce bw struct

[Harry Wentland]

From: Mikita Lipski 

Adding the stutter_entry_wm object to dce_bw_output struct
and populating it with bw calculations data

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 111 ++-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h  |   1 +
 2 files changed, 110 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 16dbf86484da..51c565cd7455 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -3091,7 +3091,33 @@ bool bw_calcs(struct dc_context *ctx,
bw_fixed_to_int(bw_mul(data->
stutter_exit_watermark[9], 
bw_int_to_fixed(1000)));
 
-
+   calcs_output->stutter_entry_wm_ns[0].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[4], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[1].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[5], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[2].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[6], 
bw_int_to_fixed(1000)));
+   if (ctx->dc->caps.max_slave_planes) {
+   calcs_output->stutter_entry_wm_ns[3].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[0], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[4].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[1], 
bw_int_to_fixed(1000)));
+   } else {
+   calcs_output->stutter_entry_wm_ns[3].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[7], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[4].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[8], 
bw_int_to_fixed(1000)));
+   }
+   calcs_output->stutter_entry_wm_ns[5].a_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[9], 
bw_int_to_fixed(1000)));
 
calcs_output->urgent_wm_ns[0].a_mark =
bw_fixed_to_int(bw_mul(data->
@@ -3186,7 +3212,33 @@ bool bw_calcs(struct dc_context *ctx,
bw_fixed_to_int(bw_mul(data->
stutter_exit_watermark[9], 
bw_int_to_fixed(1000)));
 
-
+   calcs_output->stutter_entry_wm_ns[0].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[4], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[1].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[5], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[2].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[6], 
bw_int_to_fixed(1000)));
+   if (ctx->dc->caps.max_slave_planes) {
+   calcs_output->stutter_entry_wm_ns[3].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[0], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[4].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[1], 
bw_int_to_fixed(1000)));
+   } else {
+   calcs_output->stutter_entry_wm_ns[3].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[7], 
bw_int_to_fixed(1000)));
+   calcs_output->stutter_entry_wm_ns[4].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[8], 
bw_int_to_fixed(1000)));
+   }
+   calcs_output->stutter_entry_wm_ns[5].b_mark =
+   bw_fixed_to_int(bw_mul(data->
+   stutter_entry_watermark[9], 
bw_int_to_fixed(1000)));
 
calcs_output->urgent_wm_ns[0].b_mark =
bw_fixed_to_int(bw_mul(data->
@@ 

[PATCH 12/34] drm/amd/display: add mpc to dtn log

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Wesley Chalmers 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 31 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 17 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |  5 
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h| 15 +++
 4 files changed, 60 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 8b0f6b8a5627..999190aa8a08 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -121,20 +121,19 @@ void dcn10_log_hw_state(struct dc *dc)
 
dcn10_log_hubbub_state(dc);
 
-   DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
-   "rotation \t mirror \t  sw_mode \t "
-   "dcc_en \t blank_en \t ttu_dis \t underflow \t "
-   "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
-
+   DTN_INFO("HUBP:  format  addr_hi  width  height  "
+   "rotation  mirror  sw_mode  "
+   "dcc_en  blank_en  ttu_dis  underflow  "
+   "min_ttu_vblank  qos_low_wm  qos_high_wm\n");
for (i = 0; i < pool->pipe_count; i++) {
struct hubp *hubp = pool->hubps[i];
struct dcn_hubp_state s;
 
hubp1_read_state(TO_DCN10_HUBP(hubp), );
 
-   DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
-   "%xh \t %xh \t %xh \t "
-   "%d \t %d \t %d \t %xh \t",
+   DTN_INFO("[%-2d]:  %5xh  %6xh  %5d  %6d  "
+   "%7xh  %5xh  %6xh  "
+   "%6d  %8d  %7d  %8xh \t",
hubp->inst,
s.pixel_format,
s.inuse_addr_hi,
@@ -153,6 +152,22 @@ void dcn10_log_hw_state(struct dc *dc)
DTN_INFO("\n");
}
DTN_INFO("\n");
+   for (i = 0; i < pool->pipe_count; i++) {
+   struct output_pixel_processor *opp = pool->opps[i];
+   struct mpcc *mpcc = opp->mpc_tree_params.opp_list;
+   struct mpcc_state s = {0};
+
+   while (mpcc) {
+   ASSERT(opp->mpc_tree_params.opp_id == opp->inst);
+   pool->mpc->funcs->read_mpcc_state(pool->mpc, 
mpcc->mpcc_id, );
+   DTN_INFO("[OPP%d - MPCC%d]: DPP%d MPCCBOT%x MODE:%d 
ALPHA_MODE:%d PREMULT:%d OVERLAP_ONLY:%d\n",
+   s.opp_id, mpcc->mpcc_id, s.dpp_id, 
s.bot_mpcc_id,
+   s.mode, s.alpha_mode, s.pre_multiplied_alpha, 
s.overlap_only);
+   mpcc = mpcc->mpcc_bot;
+   ASSERT(!mpcc || mpcc->mpcc_id == s.bot_mpcc_id);
+   }
+   }
+   DTN_INFO("\n");
 
DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin 
\t "
"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot 
\t underflow\n");
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 179890b1a8c4..29e15a93a7d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -409,7 +409,24 @@ void mpc1_init_mpcc_list_from_hw(
}
 }
 
+void mpc1_read_mpcc_state(
+   struct mpc *mpc,
+   int mpcc_inst,
+   struct mpcc_state *s)
+{
+   struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+
+   REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, >opp_id);
+   REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, >dpp_id);
+   REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, >bot_mpcc_id);
+   REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, >mode,
+   MPCC_ALPHA_BLND_MODE, >alpha_mode,
+   MPCC_ALPHA_MULTIPLIED_MODE, >pre_multiplied_alpha,
+   MPCC_BLND_ACTIVE_OVERLAP_ONLY, 
>pre_multiplied_alpha);
+}
+
 const struct mpc_funcs dcn10_mpc_funcs = {
+   .read_mpcc_state = mpc1_read_mpcc_state,
.insert_plane = mpc1_insert_plane,
.remove_mpcc = mpc1_remove_mpcc,
.mpc_init = mpc1_mpc_init,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index 267a2995ef6e..d3d16c4cbea3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -183,4 +183,9 @@ struct mpcc *mpc1_get_mpcc_for_dpp(
struct mpc_tree *tree,
int dpp_id);
 
+void mpc1_read_mpcc_state(

[PATCH 11/34] drm/amd/display: Don't read EDID in atomic_check

[Harry Wentland]

We shouldn't attempt to read EDID in atomic_check. We really shouldn't
even be modifying the connector object, or any other non-state object,
but this is a start at least.

Moving EDID cleanup to dm_dp_mst_connector_destroy from
dm_dp_destroy_mst_connector to ensure the EDID is still available for
headless mode.

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 32 +++---
 1 file changed, 10 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 8291d74f26bc..305292a9ff80 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -161,6 +161,11 @@ dm_dp_mst_connector_destroy(struct drm_connector 
*connector)
struct amdgpu_dm_connector *amdgpu_dm_connector = 
to_amdgpu_dm_connector(connector);
struct amdgpu_encoder *amdgpu_encoder = 
amdgpu_dm_connector->mst_encoder;
 
+   if (amdgpu_dm_connector->edid) {
+   kfree(amdgpu_dm_connector->edid);
+   amdgpu_dm_connector->edid = NULL;
+   }
+
drm_encoder_cleanup(_encoder->base);
kfree(amdgpu_encoder);
drm_connector_cleanup(connector);
@@ -181,28 +186,22 @@ static const struct drm_connector_funcs 
dm_dp_mst_connector_funcs = {
 void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
 {
struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
-   struct edid *edid;
struct dc_sink *dc_sink;
struct dc_sink_init_data init_params = {
.link = aconnector->dc_link,
.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 
+   /* FIXME none of this is safe. we shouldn't touch aconnector here in
+* atomic_check
+*/
+
/*
 * TODO: Need to further figure out why ddc.algo is NULL while MST port 
exists
 */
if (!aconnector->port || !aconnector->port->aux.ddc.algo)
return;
 
-   edid = drm_dp_mst_get_edid(connector, >mst_port->mst_mgr, 
aconnector->port);
-
-   if (!edid) {
-   drm_mode_connector_update_edid_property(
-   >base,
-   NULL);
-   return;
-   }
-
-   aconnector->edid = edid;
+   ASSERT(aconnector->edid);
 
dc_sink = dc_link_add_remote_sink(
aconnector->dc_link,
@@ -215,9 +214,6 @@ void dm_dp_mst_dc_sink_create(struct drm_connector 
*connector)
 
amdgpu_dm_add_sink_to_freesync_module(
connector, aconnector->edid);
-
-   drm_mode_connector_update_edid_property(
-   >base, aconnector->edid);
 }
 
 static int dm_dp_mst_get_modes(struct drm_connector *connector)
@@ -424,14 +420,6 @@ static void dm_dp_destroy_mst_connector(struct 
drm_dp_mst_topology_mgr *mgr,
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL;
}
-   if (aconnector->edid) {
-   kfree(aconnector->edid);
-   aconnector->edid = NULL;
-   }
-
-   drm_mode_connector_update_edid_property(
-   >base,
-   NULL);
 
aconnector->mst_connected = false;
 }
-- 
2.14.1

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[PATCH 20/34] drm/amd/display: align dtn logs and add mpc idle bit print

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 53 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h|  2 +
 3 files changed, 28 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 999190aa8a08..675a81a87099 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -56,16 +56,17 @@
 #define FN(reg_name, field_name) \
hws->shifts->field_name, hws->masks->field_name
 
+/*print is 17 wide, first two characters are spaces*/
 #define DTN_INFO_MICRO_SEC(ref_cycle) \
print_microsec(dc_ctx, ref_cycle)
 
 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
 {
-   static const uint32_t ref_clk_mhz = 48;
-   static const unsigned int frac = 10;
+   const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 
1000;
+   static const unsigned int frac = 1000;
uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
 
-   DTN_INFO("%d.%d \t ",
+   DTN_INFO("  %11d.%03d",
us_x10 / frac,
us_x10 % frac);
 }
@@ -92,14 +93,14 @@ void dcn10_log_hubbub_state(struct dc *dc)
 
hubbub1_wm_read_state(dc->res_pool->hubbub, );
 
-   DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
-   "sr_enter \t sr_exit \t dram_clk_change \n");
+   DTN_INFO("HUBBUB WM:  data_urgent  pte_meta_urgent"
+   " sr_enter  sr_exit  
dram_clk_change\n");
 
for (i = 0; i < 4; i++) {
struct dcn_hubbub_wm_set *s;
 
s = [i];
-   DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
+   DTN_INFO("WM_Set[%d]:", s->wm_set);
DTN_INFO_MICRO_SEC(s->data_urgent);
DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
DTN_INFO_MICRO_SEC(s->sr_enter);
@@ -121,19 +122,17 @@ void dcn10_log_hw_state(struct dc *dc)
 
dcn10_log_hubbub_state(dc);
 
-   DTN_INFO("HUBP:  format  addr_hi  width  height  "
-   "rotation  mirror  sw_mode  "
-   "dcc_en  blank_en  ttu_dis  underflow  "
-   "min_ttu_vblank  qos_low_wm  qos_high_wm\n");
+   DTN_INFO("HUBP:  format  addr_hi  width  height"
+   "  rot  mir  sw_mode  dcc_en  blank_en  ttu_dis  
underflow"
+   "   min_ttu_vblank   qos_low_wm  
qos_high_wm\n");
for (i = 0; i < pool->pipe_count; i++) {
struct hubp *hubp = pool->hubps[i];
struct dcn_hubp_state s;
 
hubp1_read_state(TO_DCN10_HUBP(hubp), );
 
-   DTN_INFO("[%-2d]:  %5xh  %6xh  %5d  %6d  "
-   "%7xh  %5xh  %6xh  "
-   "%6d  %8d  %7d  %8xh \t",
+   DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
+   "  %6d  %8d  %7d  %8xh",
hubp->inst,
s.pixel_format,
s.inuse_addr_hi,
@@ -152,25 +151,21 @@ void dcn10_log_hw_state(struct dc *dc)
DTN_INFO("\n");
}
DTN_INFO("\n");
+
+   DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  
OVERLAP_ONLY  IDLE\n");
for (i = 0; i < pool->pipe_count; i++) {
-   struct output_pixel_processor *opp = pool->opps[i];
-   struct mpcc *mpcc = opp->mpc_tree_params.opp_list;
struct mpcc_state s = {0};
 
-   while (mpcc) {
-   ASSERT(opp->mpc_tree_params.opp_id == opp->inst);
-   pool->mpc->funcs->read_mpcc_state(pool->mpc, 
mpcc->mpcc_id, );
-   DTN_INFO("[OPP%d - MPCC%d]: DPP%d MPCCBOT%x MODE:%d 
ALPHA_MODE:%d PREMULT:%d OVERLAP_ONLY:%d\n",
-   s.opp_id, mpcc->mpcc_id, s.dpp_id, 
s.bot_mpcc_id,
-   s.mode, s.alpha_mode, s.pre_multiplied_alpha, 
s.overlap_only);
-   mpcc = mpcc->mpcc_bot;
-   ASSERT(!mpcc || mpcc->mpcc_id == s.bot_mpcc_id);
-   }
+   pool->mpc->funcs->read_mpcc_state(pool->mpc, i, );
+   DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  
%4d\n",
+   i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
+   s.mode, s.alpha_mode, s.pre_multiplied_alpha, 
s.overlap_only,
+   s.idle);
}
DTN_INFO("\n");
 
-   

[PATCH 17/34] drm/amd/display: drop dc_validate_guaranteed

[Harry Wentland]

From: Julian Parkin 

Block FP16 scaling in validate_resources codepath.

Signed-off-by: Julian Parkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 32 --
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  8 
 .../drm/amd/display/dc/dce100/dce100_resource.c| 33 ---
 .../drm/amd/display/dc/dce110/dce110_resource.c| 33 ---
 .../drm/amd/display/dc/dce112/dce112_resource.c| 33 ---
 .../drm/amd/display/dc/dce112/dce112_resource.h|  5 ---
 .../drm/amd/display/dc/dce120/dce120_resource.c|  1 -
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  | 49 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |  7 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 31 --
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|  5 ---
 drivers/gpu/drm/amd/display/dc/inc/resource.h  |  4 --
 12 files changed, 7 insertions(+), 234 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ba3487e97361..cae78ee9a6fc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1599,18 +1599,6 @@ enum dc_status dc_remove_stream_from_ctx(
return DC_OK;
 }
 
-static void copy_pipe_ctx(
-   const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
-{
-   struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
-   struct dc_stream_state *stream = to_pipe_ctx->stream;
-
-   *to_pipe_ctx = *from_pipe_ctx;
-   to_pipe_ctx->stream = stream;
-   if (plane_state != NULL)
-   to_pipe_ctx->plane_state = plane_state;
-}
-
 static struct dc_stream_state *find_pll_sharable_stream(
struct dc_stream_state *stream_needs_pll,
struct dc_state *context)
@@ -1752,26 +1740,6 @@ enum dc_status resource_map_pool_resources(
return DC_ERROR_UNEXPECTED;
 }
 
-/* first stream in the context is used to populate the rest */
-void validate_guaranteed_copy_streams(
-   struct dc_state *context,
-   int max_streams)
-{
-   int i;
-
-   for (i = 1; i < max_streams; i++) {
-   context->streams[i] = context->streams[0];
-
-   copy_pipe_ctx(>res_ctx.pipe_ctx[0],
- >res_ctx.pipe_ctx[i]);
-   context->res_ctx.pipe_ctx[i].stream =
-   context->res_ctx.pipe_ctx[0].stream;
-
-   dc_stream_retain(context->streams[i]);
-   context->stream_count++;
-   }
-}
-
 void dc_resource_state_copy_construct_current(
const struct dc *dc,
struct dc_state *dst_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index d017df56b2ba..3a7093ede569 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -208,14 +208,6 @@ bool dc_add_all_planes_for_stream(
 
 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state 
*stream);
 
-/*
- * This function takes a stream and checks if it is guaranteed to be supported.
- * Guaranteed means that MAX_COFUNC similar streams are supported.
- *
- * After this call:
- *   No hardware is programmed for call.  Only validation is done.
- */
-
 /*
  * Set up streams and links associated to drive sinks
  * The streams parameter is an absolute set of all active streams.
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3092f76bdb75..38ec0d609297 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -733,38 +733,6 @@ enum dc_status dce100_add_stream_to_ctx(
return result;
 }
 
-enum dc_status dce100_validate_guaranteed(
-   struct dc  *dc,
-   struct dc_stream_state *dc_stream,
-   struct dc_state *context)
-{
-   enum dc_status result = DC_ERROR_UNEXPECTED;
-
-   context->streams[0] = dc_stream;
-   dc_stream_retain(context->streams[0]);
-   context->stream_count++;
-
-   result = resource_map_pool_resources(dc, context, dc_stream);
-
-   if (result == DC_OK)
-   result = resource_map_clock_resources(dc, context, dc_stream);
-
-   if (result == DC_OK)
-   result = build_mapped_resource(dc, context, dc_stream);
-
-   if (result == DC_OK) {
-   validate_guaranteed_copy_streams(
-   context, dc->caps.max_streams);
-   result = resource_build_scaling_params_for_context(dc, context);
-   }
-
-   if (result == DC_OK)
-   if 

[PATCH 02/34] drm/amd/display: dal 3.1.39

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index fa4b3c8b3bb7..4d9da9d9c731 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.38"
+#define DC_VER "3.1.39"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 19/34] drm/amd/display: dal 3.1.40

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index bdc3cef002d6..63817ed56c11 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.39"
+#define DC_VER "3.1.40"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 25/34] drm/amd/display: Add dc_lut_mode enum

[Harry Wentland]

From: Vitaly Prosyak 

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index b22158190262..015e209e58bc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -191,4 +191,9 @@ enum controller_dp_test_pattern {
CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
 };
 
+enum dc_lut_mode {
+   LUT_BYPASS,
+   LUT_RAM_A,
+   LUT_RAM_B
+};
 #endif /* __DAL_HW_SHARED_H__ */
-- 
2.14.1

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[PATCH 04/34] drm/amd/display: Fix FMT truncation programming

[Harry Wentland]

From: Mikita Lipski 

Switch the order of parameters being set for depth
and mode of truncation, as it previously was not correct

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index f19de13024f8..87093894ea9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -134,9 +134,9 @@ static void set_truncation(
REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
FMT_TRUNCATE_EN, 1,
FMT_TRUNCATE_DEPTH,
-   params->flags.TRUNCATE_MODE,
+   params->flags.TRUNCATE_DEPTH,
FMT_TRUNCATE_MODE,
-   params->flags.TRUNCATE_DEPTH);
+   params->flags.TRUNCATE_MODE);
 }
 
 
-- 
2.14.1

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[PATCH 13/34] drm/amd/display: Add debug prints for bandwidth calculations

[Harry Wentland]

From: Bhawanpreet Lakha 

Using the three functions we can print the dceip, vbios and data struct
for bandwidth calculations. This is useful for debugging bandwidth
calculation issues without a debugger

Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Harry Wentland 
Reviewed-by: Tony Cheng 
---
 .../gpu/drm/amd/display/dc/calcs/calcs_logger.h| 579 +
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c   |   6 +
 drivers/gpu/drm/amd/display/dc/dc.h|   1 +
 3 files changed, 586 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 
b/drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h
new file mode 100644
index ..fc3f98fb09ea
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h
@@ -0,0 +1,579 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _CALCS_CALCS_LOGGER_H_
+#define _CALCS_CALCS_LOGGER_H_
+#define DC_LOGGER \
+   logger
+
+static void print_bw_calcs_dceip(struct dal_logger *logger, const struct 
bw_calcs_dceip *dceip)
+{
+
+   
DC_LOG_BANDWIDTH_CALCS("#");
+   DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_dceip");
+   
DC_LOG_BANDWIDTH_CALCS("#");
+   DC_LOG_BANDWIDTH_CALCS("[enum]   bw_calcs_version version %d", 
dceip->version);
+   DC_LOG_BANDWIDTH_CALCS("[bool] large_cursor: %d", 
dceip->large_cursor);
+   DC_LOG_BANDWIDTH_CALCS("[bool] dmif_pipe_en_fbc_chunk_tracker: 
%d", dceip->dmif_pipe_en_fbc_chunk_tracker);
+   DC_LOG_BANDWIDTH_CALCS("[bool] display_write_back_supported: 
%d", dceip->display_write_back_supported);
+   DC_LOG_BANDWIDTH_CALCS("[bool] argb_compression_support: %d", 
dceip->argb_compression_support);
+   DC_LOG_BANDWIDTH_CALCS("[bool] pre_downscaler_enabled: %d", 
dceip->pre_downscaler_enabled);
+   DC_LOG_BANDWIDTH_CALCS("[bool] 
underlay_downscale_prefetch_enabled: %d",
+   dceip->underlay_downscale_prefetch_enabled);
+   DC_LOG_BANDWIDTH_CALCS("[bool] 
graphics_lb_nodownscaling_multi_line_prefetching: %d",
+   
dceip->graphics_lb_nodownscaling_multi_line_prefetching);
+   DC_LOG_BANDWIDTH_CALCS("[bool] 
limit_excessive_outstanding_dmif_requests: %d",
+   
dceip->limit_excessive_outstanding_dmif_requests);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] 
cursor_max_outstanding_group_num: %d",
+   dceip->cursor_max_outstanding_group_num);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] lines_interleaved_into_lb: 
%d", dceip->lines_interleaved_into_lb);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] low_power_tiling_mode: %d", 
dceip->low_power_tiling_mode);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] chunk_width: %d", 
dceip->chunk_width);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] number_of_graphics_pipes: 
%d", dceip->number_of_graphics_pipes);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] number_of_underlay_pipes: 
%d", dceip->number_of_underlay_pipes);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] max_dmif_buffer_allocated: 
%d", dceip->max_dmif_buffer_allocated);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] graphics_dmif_size: %d", 
dceip->graphics_dmif_size);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] underlay_luma_dmif_size: 
%d", dceip->underlay_luma_dmif_size);
+   DC_LOG_BANDWIDTH_CALCS("[uint32_t] underlay_chroma_dmif_size: 
%d", dceip->underlay_chroma_dmif_size);
+  

[PATCH 08/34] drm/amd/display: Update ASIC header files

[Harry Wentland]

From: Nikola Cornij 

Also separate register address initialization between ASICs for the
registers that were removed in scaled-down variation of the ASIC.

Signed-off-by: Nikola Cornij 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 20 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 32 +++
 2 files changed, 33 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 81b81e6efcd4..4ca9b6e9a824 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -535,11 +535,13 @@ void hubp1_program_deadline(
REG_SET(VBLANK_PARAMETERS_3, 0,
REFCYC_PER_META_CHUNK_VBLANK_L, 
dlg_attr->refcyc_per_meta_chunk_vblank_l);
 
-   REG_SET(NOM_PARAMETERS_0, 0,
-   DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
+   if (REG(NOM_PARAMETERS_0))
+   REG_SET(NOM_PARAMETERS_0, 0,
+   DST_Y_PER_PTE_ROW_NOM_L, 
dlg_attr->dst_y_per_pte_row_nom_l);
 
-   REG_SET(NOM_PARAMETERS_1, 0,
-   REFCYC_PER_PTE_GROUP_NOM_L, 
dlg_attr->refcyc_per_pte_group_nom_l);
+   if (REG(NOM_PARAMETERS_1))
+   REG_SET(NOM_PARAMETERS_1, 0,
+   REFCYC_PER_PTE_GROUP_NOM_L, 
dlg_attr->refcyc_per_pte_group_nom_l);
 
REG_SET(NOM_PARAMETERS_4, 0,
DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
@@ -568,11 +570,13 @@ void hubp1_program_deadline(
REG_SET(VBLANK_PARAMETERS_4, 0,
REFCYC_PER_META_CHUNK_VBLANK_C, 
dlg_attr->refcyc_per_meta_chunk_vblank_c);
 
-   REG_SET(NOM_PARAMETERS_2, 0,
-   DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
+   if (REG(NOM_PARAMETERS_2))
+   REG_SET(NOM_PARAMETERS_2, 0,
+   DST_Y_PER_PTE_ROW_NOM_C, 
dlg_attr->dst_y_per_pte_row_nom_c);
 
-   REG_SET(NOM_PARAMETERS_3, 0,
-   REFCYC_PER_PTE_GROUP_NOM_C, 
dlg_attr->refcyc_per_pte_group_nom_c);
+   if (REG(NOM_PARAMETERS_3))
+   REG_SET(NOM_PARAMETERS_3, 0,
+   REFCYC_PER_PTE_GROUP_NOM_C, 
dlg_attr->refcyc_per_pte_group_nom_c);
 
REG_SET(NOM_PARAMETERS_6, 0,
DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 4a3703e12ea1..c794ce4a8177 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -30,6 +30,7 @@
 #define TO_DCN10_HUBP(hubp)\
container_of(hubp, struct dcn10_hubp, base)
 
+/* Register address initialization macro for all ASICs (including those with 
reduced functionality) */
 #define HUBP_REG_LIST_DCN(id)\
SRI(DCHUBP_CNTL, HUBP, id),\
SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
@@ -78,16 +79,12 @@
SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
@@ -96,11 +93,19 @@
SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
-   SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
SRI(HUBP_CLK_CNTL, HUBP, id)
 
+/* Register address initialization macro for "generic" ASICs with full 
functionality */
+#define HUBP_REG_LIST_DCN_GEN(id)\
+   SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
+   SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
+   SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
+   SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
+   SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
+
 #define HUBP_REG_LIST_DCN10(id)\
HUBP_REG_LIST_DCN(id),\
+   HUBP_REG_LIST_DCN_GEN(id),\
SRI(PREFETCH_SETTINS, HUBPREQ, id),\
SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
@@ -237,6 +242,7 @@
 #define HUBP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
 
+/* Mask/shift struct generation macro for all ASICs (including those with 
reduced 

[PATCH 00/34] DC Patches Mar 20, 2018

[Harry Wentland]

 * Fix multi-channel audio
 * Fix banding on 6 bit eDP panels with Polaris
 * Fix Polaris 12 BW calcs
 * Drop EDID read during atomic_check (for MST)

Anthony Koo (3):
  drm/amd/display: Couple bug fixes in stats module
  drm/amd/display: Rename encoder_info_packet to dc_info_packet
  drm/amd/display: Only program MSA_TIMING_PARAM if it changed

Bhawanpreet Lakha (2):
  drm/amd/display: Add debug prints for bandwidth calculations
  drm/amd/display: Correct print types in DC_LOGS

Dmytro Laktyushkin (4):
  drm/amd/display: fix lexa bw bounding box
  drm/amd/display: add mpc to dtn log
  drm/amd/display: align dtn logs and add mpc idle bit print
  drm/amd/display: hide inconsistent mpcc programming from dtn log

Eric Bernstein (2):
  drm/amd/display: Change wb_h/vratio to double
  drm/amd/display: Add num_active_wb to DML

Eric Yang (1):
  drm/amd/display: Only update mpc blend config if not full update

Harry Wentland (4):
  drm/amd/display: We shouldn't set format_default on plane as atomic
driver
  drm/amd/display: Add one to EDID's audio channel count when passing to
DC
  drm/amd/display: Don't read EDID in atomic_check
  drm/amd/display: Move commit_planes_to_stream to amdgpu_dm

Julian Parkin (1):
  drm/amd/display: drop dc_validate_guaranteed

Martin Tsai (1):
  drm/amd/display: correct the condition in setting cursor not visible
beyond left edge

Mikita Lipski (6):
  drm/amd/display: Allow truncation to 10 bits
  drm/amd/display: Fix FMT truncation programming
  drm/amd/display: Don't call amdgpu_dm_display_resume as it doesn't
exist
  drm/amd/display: Adding stutter entry wm to dce bw struct
  drm/amd/display: Implementing new bandwidth registers for DCE120
  drm/amd/display: Separate mem input constuctors for dce 112 and 120

Nikola Cornij (2):
  drm/amd/display: Update ASIC header files
  drm/amd/display: Rename feature-specific register address init macro

Roman Li (1):
  drm/amd/display: add assert in enable FBC

SivapiriyanKumarasamy (1):
  drm/amd/display: Add vline IRQ programming for DCN

Tony Cheng (2):
  drm/amd/display: dal 3.1.39
  drm/amd/display: dal 3.1.40

Vitaly Prosyak (1):
  drm/amd/display: Add dc_lut_mode enum

Xingyue Tao (2):
  drm/amd/display: Add double buffer machanism to ICSC
  drm/amd/display: Add double buffer machanism to OCSC

Yongqiang Sun (1):
  drm/amd/display: Retry when read dpcd caps failed.

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 111 +++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c|  32 +-
 .../gpu/drm/amd/display/dc/calcs/calcs_logger.h| 579 +
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c   | 238 -
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  74 +--
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  95 +---
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c |  14 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  23 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  16 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 131 ++---
 drivers/gpu/drm/amd/display/dc/dc.h|   3 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  19 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h  |   9 +
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 103 +++-
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  17 +
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c   |   9 +-
 .../drm/amd/display/dc/dce/dce_stream_encoder.c|   4 +-
 .../drm/amd/display/dc/dce100/dce100_resource.c|  33 --
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  10 +-
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c |   1 +
 .../drm/amd/display/dc/dce110/dce110_resource.c|  33 --
 .../drm/amd/display/dc/dce112/dce112_resource.c|  33 --
 .../drm/amd/display/dc/dce112/dce112_resource.h|   5 -
 .../drm/amd/display/dc/dce120/dce120_resource.c|   3 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |  49 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |   9 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  47 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c|  90 ++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  |  22 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h  |  32 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  58 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  24 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   5 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c  |  76 +++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  |  14 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  36 +-
 .../drm/amd/display/dc/dml/display_mode_structs.h  |   5 +-
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.c|   2 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   6 +-
 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h  |   5 +
 

Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Christian König]

I don't think that is a good idea.

Ideally GTT should now have the same performance as VRAM on APUs and we 
should use VRAM only for things where we absolutely have to and to 
actually use up the otherwise unused VRAM.


Can you run some tests with all BOs forced to GTT and see if there is 
any performance regression?


Christian.

Am 20.03.2018 um 15:51 schrieb Marek Olšák:
On Tue, Mar 20, 2018 at 9:55 AM, Christian König 
> wrote:


Yes, exactly. And if I remember correctly Mesa used to always set
GTT as fallback on APUs, correct?


"used to" is the key part. Mesa doesn't force GTT on APUs anymore. It 
expects that the combination of BO priorities and BO move throttling 
will result in optimal BO placements over time.


Marek


The problem seems to be that this fallback isn't set for
displayable BOs.

So what needs to be done is to just enable this fallback for
displayable BOs as well if the kernel can handle it.

Christian.


Am 20.03.2018 um 00:01 schrieb Marek Olšák:

In theory, Mesa doesn't have to do anything. It can continue
setting VRAM and if the kernel has to put a display buffer into
GTT, it doesn't matter (for Mesa). Whether the VRAM placement is
really used is largely determined by BO priorities.

The way I understand scather/gather is that it only allows the
GTT placement. It doesn't force the GTT placement. Mesa also
doesn't force the GTT placement.

Marek

On Mon, Mar 19, 2018 at 5:12 PM, Alex Deucher
> wrote:

On Mon, Mar 19, 2018 at 4:29 PM, Li, Samuel
> wrote:
>>to my earlier point, there may be cases where it is
advantageous to put
>> display buffers in vram even if s/g display is supported
>
> Agreed. That is also why the patch has the options to let
user select where
> to put display buffers.
>
> As whether to put the option in Mesa or kernel, it seems
the difference is
> not much. Also, since amdgpufb can request even without
mesa, kernel might
> be a better choice. In addition, putting in the kernel can
save client’s
> duplicate work(mesa, ogl, vulkan, 2d, kernel…)

Why do we even expose different memory pools to the UMDs in
the first
place ;)  Each pool has performance characteristics that may be
relevant for a particular work load.  Only the UMDs really
know the
finer points of those workloads. In general, you don't want
the kernel
dictating policy if you can avoid it.  The kernel exposes
functionality and userspace sets the policy.  With the
location set in
userspace, each app/user can have whatever policy makes sense for
their use case all at the same time without needing to tweak
their
kernel for every use case.

Alex



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Re: [Linaro-mm-sig] [PATCH 1/5] dma-buf: add optional invalidate_mappings callback v2

[Christian König]

Am 20.03.2018 um 15:08 schrieb Daniel Vetter:

[SNIP]
For the in-driver reservation path (CS) having a slow-path that grabs a
temporary reference, drops the vram lock and then locks the reservation
normally (using the acquire context used already for the entire CS) is a
bit tricky, but totally feasible. Ttm doesn't do that though.


That is exactly what we do in amdgpu as well, it's just not very 
efficient nor reliable to retry getting the right pages for a submission 
over and over again.



[SNIP]
Note that there are 2 paths for i915 userptr. One is the mmu notifier, the
other one is the root-only hack we have for dubious reasons (or that I
really don't see the point in myself).


Well I'm referring to i915_gem_userptr.c, if that isn't what you are 
exposing then just feel free to ignore this whole discussion.



For coherent usage you need to install some lock to prevent concurrent
get_user_pages(), command submission and
invalidate_range_start/invalidate_range_end from the MMU notifier.

Otherwise you can't guarantee that you are actually accessing the right page
in the case of a fork() or mprotect().

Yeah doing that with a full lock will create endless amounts of issues,
but I don't see why we need that. Userspace racing stuff with itself gets
to keep all the pieces. This is like racing DIRECT_IO against mprotect and
fork.


First of all I strongly disagree on that. A thread calling fork() 
because it wants to run a command is not something we can forbid just 
because we have a gfx stack loaded. That the video driver is not capable 
of handling that correct is certainly not the problem of userspace.


Second it's not only userspace racing here, you can get into this kind 
of issues just because of transparent huge page support where the 
background daemon tries to reallocate the page tables into bigger chunks.


And if I'm not completely mistaken you can also open up quite a bunch of 
security problems if you suddenly access the wrong page.



Leaking the IOMMU mappings otoh means rogue userspace could do a bunch of
stray writes (I don't see anywhere code in amdgpu_mn.c to unmap at least
the gpu side PTEs to make stuff inaccessible) and wreak the core kernel's
book-keeping.

In i915 we guarantee that we call set_page_dirty/mark_page_accessed only
after all the mappings are really gone (both GPU PTEs and sg mapping),
guaranteeing that any stray writes from either the GPU or IOMMU will
result in faults (except bugs in the IOMMU, but can't have it all, "IOMMU
actually works" is an assumption behind device isolation).
Well exactly that's the point, the handling in i915 looks incorrect to 
me. You need to call set_page_dirty/mark_page_accessed way before the 
mapping is destroyed.


To be more precise for userptrs it must be called from the 
invalidate_range_start, but i915 seems to delegate everything into a 
background worker to avoid the locking problems.



Felix and I hammered for quite some time on amdgpu until all of this was
handled correctly, see drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c.

Maybe we should have more shared code in this, it seems to be a source of
endless amounts of fun ...


I can try to gather the lockdep splat from my mail history, but it
essentially took us multiple years to get rid of all of them.

I'm very much interested in specifically the splat that makes it
impossible for you folks to remove the sg mappings. That one sounds bad.
And would essentially make mmu_notifiers useless for their primary use
case, which is handling virtual machines where you really have to make
sure the IOMMU mapping is gone before you claim it's gone, because there's
no 2nd level of device checks (like GPU PTEs, or command checker) catching
stray writes.


Well to be more precise the problem is not that we can't destroy the sg 
table, but rather that we can't grab the locks to do so.


See when you need to destroy the sg table you usually need to grab the 
same lock you grabbed when you created it.


And all locks taken while in an MMU notifier can only depend on memory 
allocation with GFP_NOIO, which is not really feasible for gfx drivers.


Regards,
Christian.
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RE: [PATCH umr] Fix PBA addressing on APUs with a non-zero FB_OFFSET

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, March 20, 2018 12:24 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom 
> Subject: [PATCH umr] Fix PBA addressing on APUs with a non-zero
> FB_OFFSET
> 
> Tested with my Carrizo and Polaris10.
> 
> Signed-off-by: Tom St Denis 

Reviewed-by: Alex Deucher 

> ---
>  src/lib/read_vram.c | 17 +
>  1 file changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c index
> 86864c6076bd..de9b6497f419 100644
> --- a/src/lib/read_vram.c
> +++ b/src/lib/read_vram.c
> @@ -118,7 +118,7 @@ static int umr_access_vram_vi(struct umr_asic *asic,
> uint32_t vmid,  {
>   uint64_t start_addr, page_table_start_addr, page_table_base_addr,
>page_table_size, pte_idx, pde_idx, pte_entry, pde_entry,
> -  vm_fb_base, pde_mask, pte_mask;
> +  vm_fb_base, vm_fb_offset, pde_mask, pte_mask;
>   uint32_t chunk_size, tmp;
>   int page_table_depth;
>   struct {
> @@ -139,7 +139,8 @@ static int umr_access_vram_vi(struct umr_asic *asic,
> uint32_t vmid,
>   mmVM_CONTEXTx_PAGE_TABLE_START_ADDR,
>   mmVM_CONTEXTx_CNTL,
>   mmVM_CONTEXTx_PAGE_TABLE_BASE_ADDR,
> - mmMC_VM_FB_LOCATION;
> + mmMC_VM_FB_LOCATION,
> + mmMC_VM_FB_OFFSET;
>   } registers;
>   char buf[64];
>   unsigned char *pdst = dst;
> @@ -185,20 +186,24 @@ static int umr_access_vram_vi(struct umr_asic
> *asic, uint32_t vmid,
>   registers.mmMC_VM_FB_LOCATION =
> umr_read_reg_by_name(asic, "mmMC_VM_FB_LOCATION");
>   vm_fb_base  = ((uint64_t)registers.mmMC_VM_FB_LOCATION &
> 0x) << 24;
> 
> + registers.mmMC_VM_FB_OFFSET = umr_read_reg_by_name(asic,
> "mmMC_VM_FB_OFFSET");
> + vm_fb_offset  = ((uint64_t)registers.mmMC_VM_FB_OFFSET &
> 0x) <<
> +22;
> 
>   if (asic->options.verbose)
>   fprintf(stderr,
>   "[VERBOSE]:
> mmVM_CONTEXT%d_PAGE_TABLE_START_ADDR=0x%llx\n"
>   "[VERBOSE]:
> mmVM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%llx\n"
>   "[VERBOSE]:
> mmVM_CONTEXT%d_CNTL=0x%llx\n"
> - "[VERBOSE]:
> mmMC_VM_FB_LOCATION=0x%llx\n",
> + "[VERBOSE]:
> mmMC_VM_FB_LOCATION=0x%llx\n"
> + "[VERBOSE]:
> mmMC_VM_FB_OFFSET=0x%llx\n",
>   (int)vmid ? 1 : 0,
>   (unsigned long
> long)registers.mmVM_CONTEXTx_PAGE_TABLE_START_ADDR,
>   (int)vmid ? 1 : 0,
>   (unsigned long
> long)registers.mmVM_CONTEXTx_PAGE_TABLE_BASE_ADDR,
>   (int)vmid ? 1 : 0,
>   (unsigned long
> long)registers.mmVM_CONTEXTx_CNTL,
> - (unsigned long
> long)registers.mmMC_VM_FB_LOCATION);
> + (unsigned long
> long)registers.mmMC_VM_FB_LOCATION,
> + (unsigned long
> long)registers.mmMC_VM_FB_OFFSET);
> 
>   address -= page_table_start_addr;
> 
> @@ -262,6 +267,10 @@ static int umr_access_vram_vi(struct umr_asic *asic,
> uint32_t vmid,
> 
>   // compute starting address
>   start_addr = dma_to_phys(asic,
> pte_fields.page_base_addr) + (address & 0xFFF);
> +
> + if (!pte_fields.system)
> + start_addr = start_addr - vm_fb_offset;
> +
>   } else {
>   // depth == 0 == PTE only
>   pte_idx = (address >> 12);
> --
> 2.14.3
> 
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[PATCH umr] Fix PBA addressing on APUs with a non-zero FB_OFFSET

[Tom St Denis]

Tested with my Carrizo and Polaris10.

Signed-off-by: Tom St Denis 
---
 src/lib/read_vram.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index 86864c6076bd..de9b6497f419 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/read_vram.c
@@ -118,7 +118,7 @@ static int umr_access_vram_vi(struct umr_asic *asic, 
uint32_t vmid,
 {
uint64_t start_addr, page_table_start_addr, page_table_base_addr,
 page_table_size, pte_idx, pde_idx, pte_entry, pde_entry,
-vm_fb_base, pde_mask, pte_mask;
+vm_fb_base, vm_fb_offset, pde_mask, pte_mask;
uint32_t chunk_size, tmp;
int page_table_depth;
struct {
@@ -139,7 +139,8 @@ static int umr_access_vram_vi(struct umr_asic *asic, 
uint32_t vmid,
mmVM_CONTEXTx_PAGE_TABLE_START_ADDR,
mmVM_CONTEXTx_CNTL,
mmVM_CONTEXTx_PAGE_TABLE_BASE_ADDR,
-   mmMC_VM_FB_LOCATION;
+   mmMC_VM_FB_LOCATION,
+   mmMC_VM_FB_OFFSET;
} registers;
char buf[64];
unsigned char *pdst = dst;
@@ -185,20 +186,24 @@ static int umr_access_vram_vi(struct umr_asic *asic, 
uint32_t vmid,
registers.mmMC_VM_FB_LOCATION = umr_read_reg_by_name(asic, 
"mmMC_VM_FB_LOCATION");
vm_fb_base  = ((uint64_t)registers.mmMC_VM_FB_LOCATION & 0x) << 24;
 
+   registers.mmMC_VM_FB_OFFSET = umr_read_reg_by_name(asic, 
"mmMC_VM_FB_OFFSET");
+   vm_fb_offset  = ((uint64_t)registers.mmMC_VM_FB_OFFSET & 0x) << 22;
 
if (asic->options.verbose)
fprintf(stderr,
"[VERBOSE]: 
mmVM_CONTEXT%d_PAGE_TABLE_START_ADDR=0x%llx\n"
"[VERBOSE]: 
mmVM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%llx\n"
"[VERBOSE]: mmVM_CONTEXT%d_CNTL=0x%llx\n"
-   "[VERBOSE]: mmMC_VM_FB_LOCATION=0x%llx\n",
+   "[VERBOSE]: mmMC_VM_FB_LOCATION=0x%llx\n"
+   "[VERBOSE]: mmMC_VM_FB_OFFSET=0x%llx\n",
(int)vmid ? 1 : 0,
(unsigned long 
long)registers.mmVM_CONTEXTx_PAGE_TABLE_START_ADDR,
(int)vmid ? 1 : 0,
(unsigned long 
long)registers.mmVM_CONTEXTx_PAGE_TABLE_BASE_ADDR,
(int)vmid ? 1 : 0,
(unsigned long long)registers.mmVM_CONTEXTx_CNTL,
-   (unsigned long long)registers.mmMC_VM_FB_LOCATION);
+   (unsigned long long)registers.mmMC_VM_FB_LOCATION,
+   (unsigned long long)registers.mmMC_VM_FB_OFFSET);
 
address -= page_table_start_addr;
 
@@ -262,6 +267,10 @@ static int umr_access_vram_vi(struct umr_asic *asic, 
uint32_t vmid,
 
// compute starting address
start_addr = dma_to_phys(asic, 
pte_fields.page_base_addr) + (address & 0xFFF);
+
+   if (!pte_fields.system)
+   start_addr = start_addr - vm_fb_offset;
+
} else {
// depth == 0 == PTE only
pte_idx = (address >> 12);
-- 
2.14.3

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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Marek Olšák]

On Tue, Mar 20, 2018 at 9:55 AM, Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:

> Yes, exactly. And if I remember correctly Mesa used to always set GTT as
> fallback on APUs, correct?
>

"used to" is the key part. Mesa doesn't force GTT on APUs anymore. It
expects that the combination of BO priorities and BO move throttling will
result in optimal BO placements over time.

Marek


>
> The problem seems to be that this fallback isn't set for displayable BOs.
>
> So what needs to be done is to just enable this fallback for displayable
> BOs as well if the kernel can handle it.
>
> Christian.
>
>
> Am 20.03.2018 um 00:01 schrieb Marek Olšák:
>
> In theory, Mesa doesn't have to do anything. It can continue setting VRAM
> and if the kernel has to put a display buffer into GTT, it doesn't matter
> (for Mesa). Whether the VRAM placement is really used is largely determined
> by BO priorities.
>
> The way I understand scather/gather is that it only allows the GTT
> placement. It doesn't force the GTT placement. Mesa also doesn't force the
> GTT placement.
>
> Marek
>
> On Mon, Mar 19, 2018 at 5:12 PM, Alex Deucher 
> wrote:
>
>> On Mon, Mar 19, 2018 at 4:29 PM, Li, Samuel  wrote:
>> >>to my earlier point, there may be cases where it is advantageous to put
>> >> display buffers in vram even if s/g display is supported
>> >
>> > Agreed. That is also why the patch has the options to let user select
>> where
>> > to put display buffers.
>> >
>> > As whether to put the option in Mesa or kernel, it seems the difference
>> is
>> > not much. Also, since amdgpufb can request even without mesa, kernel
>> might
>> > be a better choice. In addition, putting in the kernel can save client’s
>> > duplicate work(mesa, ogl, vulkan, 2d, kernel…)
>>
>> Why do we even expose different memory pools to the UMDs in the first
>> place ;)  Each pool has performance characteristics that may be
>> relevant for a particular work load.  Only the UMDs really know the
>> finer points of those workloads. In general, you don't want the kernel
>> dictating policy if you can avoid it.  The kernel exposes
>> functionality and userspace sets the policy.  With the location set in
>> userspace, each app/user can have whatever policy makes sense for
>> their use case all at the same time without needing to tweak their
>> kernel for every use case.
>>
>> Alex
>>
>
>
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>
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Re: [PATCH] drm/amdgpu: disable job timeout on GPU reset disabled

[Christian König]

That's a good point as well, maybe we should have separate timeouts for 
gfx and compute?


Something like 5 seconds for gfx and 1 minute (or even longer) for compute?

Anyway I agree that we can worry about that later on, patch is 
Reviewed-by: Christian König  for now.


Regards,
Christian.

Am 20.03.2018 um 15:16 schrieb Deucher, Alexander:


My concern was that compute will always have the timeout disabled with 
no way to override it even if you enable GPU reset.  I guess we can 
address that down the road.



Acked-by: Alex Deucher 


*From:* Koenig, Christian
*Sent:* Tuesday, March 20, 2018 6:14:29 AM
*To:* Quan, Evan; amd-gfx@lists.freedesktop.org
*Cc:* Deucher, Alexander
*Subject:* Re: [PATCH] drm/amdgpu: disable job timeout on GPU reset 
disabled

Hi Evan,

that one is perfect if you ask me. Just reading up on the history of
that patch, Alex what was your concern with that?

Regarding printing this as error, that's a really good point as well. We
should probably reduce it to a warning or even info severity.

Regards,
Christian.

Am 20.03.2018 um 03:11 schrieb Quan, Evan:
> Hi Christian,
>
> The messages prompted on timeout are Errors not just Warnings 
although we did not see any real problem(for the dgemm special case). 
That's why we say it confusing.

> And i suppose you want a fix like my previous patch(see attachment).
>
> Regards,
> Evan
>> -Original Message-
>> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
>> Sent: Monday, March 19, 2018 5:42 PM
>> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander 
>> Subject: Re: [PATCH] drm/amdgpu: disable job timeout on GPU reset
>> disabled
>>
>> Am 19.03.2018 um 07:08 schrieb Evan Quan:
>>> Since under some heavy computing environment(dgemm test), it takes the
>>> asic over 10+ seconds to finish the dispatched single job which will
>>> trigger the timeout. It's quite confusing although it does not seem to
>>> bring any real problems.
>>> As a quick workround, we choose to disable timeout when GPU reset is
>>> disabled.
>> NAK, I enabled those warning intentionally even when the GPU 
recovery is

>> disabled to have a hint in the logs what goes wrong.
>>
>> Please only increase the timeout for the compute queue and/or add a
>> separate timeout for them.
>>
>> Regards,
>> Christian.
>>
>>
>>> Change-Id: I3a95d856ba4993094dc7b6269649e470c5b053d2
>>> Signed-off-by: Evan Quan 
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
>>>    1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index 8bd9c3f..9d6a775 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -861,6 +861,13 @@ static void
>> amdgpu_device_check_arguments(struct amdgpu_device *adev)
>>>  amdgpu_lockup_timeout = 1;
>>>  }
>>>
>>> +   /*
>>> +    * Disable timeout when GPU reset is disabled to avoid confusing
>>> +    * timeout messages in the kernel log.
>>> +    */
>>> +   if (amdgpu_gpu_recovery == 0 || amdgpu_gpu_recovery == -1)
>>> +   amdgpu_lockup_timeout = INT_MAX;
>>> +
>>>  adev->firmware.load_type = amdgpu_ucode_get_load_type(adev,
>> amdgpu_fw_load_type);
>>>    }
>>>



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Re: [PATCH] drm/amd/pp: Fix gfx ring test failed on Fiji without hw avfs support

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Tuesday, March 20, 2018 5:05:23 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Fix gfx ring test failed on Fiji without hw avfs 
support

caused by
'commit ca82cec868d1 ("drm/amd/pp: Simplified the avfs btc state on smu7")'

Change-Id: Ice0012e74ec3ef25cc561f8515ea6a553567d8a6
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  | 3 +++
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 6 --
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 43432e4..faef783 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -263,6 +263,9 @@ static int fiji_setup_graphics_level_structure(struct 
pp_hwmgr *hwmgr)

 static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr)
 {
+   if (!hwmgr->avfs_supported)
+   return 0;
+
 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
 "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics 
Level"
 " table over to SMU",
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index f6b1298..997a777 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -172,11 +172,13 @@ static int 
polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
 }


-static int
-polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
+static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
 {
 struct smu7_smumgr *smu_data = (struct smu7_smumgr 
*)(hwmgr->smu_backend);

+   if (!hwmgr->avfs_supported)
+   return 0;
+
 PP_ASSERT_WITH_CODE(0 == 
polaris10_setup_graphics_level_structure(hwmgr),
 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level 
table over to SMU",
 return -EINVAL);
--
1.9.1

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Re: [PATCH 2/2] drm/amdgpu: Fix kernel NULL pointer dereference in dpm functions

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Tuesday, March 20, 2018 4:37:11 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 2/2] drm/amdgpu: Fix kernel NULL pointer dereference in dpm 
functions

caused by
'commit 83e3c4615872 ("drm/amdgpu: Remove wrapper layer of smu ip functions")'

BUG: unable to handle kernel NULL pointer dereference at 05d8
[  313.241459] IP: ci_dpm_read_sensor+0x37/0xf0 [amdgpu]

Change-Id: Iac0cf26264ccbc60181ccd9bba79fe3c4e420456
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 1 +
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 98d1dd2..47ef3e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6244,6 +6244,7 @@ static int ci_dpm_early_init(void *handle)
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

 adev->powerplay.pp_funcs = _dpm_funcs;
+   adev->powerplay.pp_handle = adev;
 ci_dpm_set_irq_funcs(adev);

 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 81babe0..26ba984 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2963,6 +2963,7 @@ static int kv_dpm_early_init(void *handle)
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

 adev->powerplay.pp_funcs = _dpm_funcs;
+   adev->powerplay.pp_handle = adev;
 kv_dpm_set_irq_funcs(adev);

 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 3bfcf0d..672eaff 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7917,6 +7917,7 @@ static int si_dpm_early_init(void *handle)
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

 adev->powerplay.pp_funcs = _dpm_funcs;
+   adev->powerplay.pp_handle = adev;
 si_dpm_set_irq_funcs(adev);
 return 0;
 }
--
1.9.1

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Re: [Linaro-mm-sig] [PATCH 1/5] dma-buf: add optional invalidate_mappings callback v2

[Daniel Vetter]

On Tue, Mar 20, 2018 at 11:54:18AM +0100, Christian König wrote:
> Am 20.03.2018 um 08:44 schrieb Daniel Vetter:
> > On Mon, Mar 19, 2018 at 5:23 PM, Christian König
> >  wrote:
> > > Am 19.03.2018 um 16:53 schrieb Chris Wilson:
> > > > Quoting Christian König (2018-03-16 14:22:32)
> > > > [snip, probably lost too must context]
> > > > > This allows for full grown pipelining, e.g. the exporter can say I 
> > > > > need
> > > > > to move the buffer for some operation. Then let the move operation 
> > > > > wait
> > > > > for all existing fences in the reservation object and install the 
> > > > > fence
> > > > > of the move operation as exclusive fence.
> > > > Ok, the situation I have in mind is the non-pipelined case: revoking
> > > > dma-buf for mmu_invalidate_range or shrink_slab. I would need a
> > > > completion event that can be waited on the cpu for all the invalidate
> > > > callbacks. (Essentially an atomic_t counter plus struct completion; a
> > > > lighter version of dma_fence, I wonder where I've seen that before ;)
> > > 
> > > Actually that is harmless.
> > > 
> > > When you need to unmap a DMA-buf because of mmu_invalidate_range or
> > > shrink_slab you need to wait for it's reservation object anyway.
> > reservation_object only prevents adding new fences, you still have to
> > wait for all the current ones to signal. Also, we have dma-access
> > without fences in i915. "I hold the reservation_object" does not imply
> > you can just go and nuke the backing storage.
> 
> I was not talking about taking the lock, but rather using
> reservation_object_wait_timeout_rcu().
> 
> To be more precise you actually can't take the reservation object lock in an
> mmu_invalidate_range callback and you can only trylock it in a shrink_slab
> callback.

Ah ok, and yes agreed. Kinda. See below.

> > > This needs to be done to make sure that the backing memory is now idle, it
> > > doesn't matter if the jobs where submitted by DMA-buf importers or your 
> > > own
> > > driver.
> > > 
> > > The sg tables pointing to the now released memory might live a bit longer,
> > > but that is unproblematic and actually intended.
> > I think that's very problematic. One reason for an IOMMU is that you
> > have device access isolation, and a broken device can't access memory
> > it shouldn't be able to access. From that security-in-depth point of
> > view it's not cool that there's some sg tables hanging around still
> > that a broken GPU could use. And let's not pretend hw is perfect,
> > especially GPUs :-)
> 
> I completely agree on that, but there is unfortunately no other way.
> 
> See you simply can't take a reservation object lock in an mmu or slab
> callback, you can only trylock them.
> 
> For example it would require changing all allocations done while holding any
> reservation lock to GFP_NOIO.

Yeah mmu and slab can only trylock, and they need to skip to the next
object when the trylock fails. But once you have the lock you imo should
be able to clean up the entire mess still. We definitely do that for the
i915 shrinkers, and I don't see how going to importers through the
->invalidate_mapping callback changes anything with that.

For the in-driver reservation path (CS) having a slow-path that grabs a
temporary reference, drops the vram lock and then locks the reservation
normally (using the acquire context used already for the entire CS) is a
bit tricky, but totally feasible. Ttm doesn't do that though.

So there's completely feasible ways to make sure the sg list is all
properly released, all DMA gone and the IOMMU mappings torn down. Anything
else is just a bit shoddy device driver programming imo.

> > > When we would try to destroy the sg tables in an mmu_invalidate_range or
> > > shrink_slab callback we would run into a lockdep horror.
> > So I'm no expert on this, but I think this is exactly what we're doing
> > in i915. Kinda no other way to actually free the memory without
> > throwing all the nice isolation aspects of an IOMMU into the wind. Can
> > you please paste the lockdeps you've seen with amdgpu when trying to
> > do that?
> 
> Taking a quick look at i915 I can definitely say that this is actually quite
> buggy what you guys do here.

Note that there are 2 paths for i915 userptr. One is the mmu notifier, the
other one is the root-only hack we have for dubious reasons (or that I
really don't see the point in myself).

> For coherent usage you need to install some lock to prevent concurrent
> get_user_pages(), command submission and
> invalidate_range_start/invalidate_range_end from the MMU notifier.
> 
> Otherwise you can't guarantee that you are actually accessing the right page
> in the case of a fork() or mprotect().

Yeah doing that with a full lock will create endless amounts of issues,
but I don't see why we need that. Userspace racing stuff with itself gets
to keep all the pieces. This is like racing DIRECT_IO against mprotect and
fork.

Leaking the IOMMU 

Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Christian König]

Yes, exactly. And if I remember correctly Mesa used to always set GTT as 
fallback on APUs, correct?


The problem seems to be that this fallback isn't set for displayable BOs.

So what needs to be done is to just enable this fallback for displayable 
BOs as well if the kernel can handle it.


Christian.

Am 20.03.2018 um 00:01 schrieb Marek Olšák:
In theory, Mesa doesn't have to do anything. It can continue setting 
VRAM and if the kernel has to put a display buffer into GTT, it 
doesn't matter (for Mesa). Whether the VRAM placement is really used 
is largely determined by BO priorities.


The way I understand scather/gather is that it only allows the GTT 
placement. It doesn't force the GTT placement. Mesa also doesn't force 
the GTT placement.


Marek

On Mon, Mar 19, 2018 at 5:12 PM, Alex Deucher > wrote:


On Mon, Mar 19, 2018 at 4:29 PM, Li, Samuel > wrote:
>>to my earlier point, there may be cases where it is advantageous
to put
>> display buffers in vram even if s/g display is supported
>
> Agreed. That is also why the patch has the options to let user
select where
> to put display buffers.
>
> As whether to put the option in Mesa or kernel, it seems the
difference is
> not much. Also, since amdgpufb can request even without mesa,
kernel might
> be a better choice. In addition, putting in the kernel can save
client’s
> duplicate work(mesa, ogl, vulkan, 2d, kernel…)

Why do we even expose different memory pools to the UMDs in the first
place ;)  Each pool has performance characteristics that may be
relevant for a particular work load.  Only the UMDs really know the
finer points of those workloads. In general, you don't want the kernel
dictating policy if you can avoid it.  The kernel exposes
functionality and userspace sets the policy.  With the location set in
userspace, each app/user can have whatever policy makes sense for
their use case all at the same time without needing to tweak their
kernel for every use case.

Alex



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Re: [PATCH] drm/amd/amdgpu: fix offset into page with amdgpu_iomem debugfs file

[Christian König]

Am 20.03.2018 um 14:16 schrieb Tom St Denis:

The offset inside the page wasn't included in the copy call meaning
the start of the page was being read/written instead.

Reported-by: Jay Cornwall 
Signed-off-by: Tom St Denis 


Good catch, patch is Reviewed-by: Christian König 
.


Regards,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 291dd3d600cd..d2ab40494a4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1996,7 +1996,7 @@ static ssize_t amdgpu_iomem_read(struct file *f, char 
__user *buf,
return -EPERM;
  
  		ptr = kmap(p);

-   r = copy_to_user(buf, ptr, bytes);
+   r = copy_to_user(buf, ptr + off, bytes);
kunmap(p);
if (r)
return -EFAULT;
@@ -2040,7 +2040,7 @@ static ssize_t amdgpu_iomem_write(struct file *f, const 
char __user *buf,
return -EPERM;
  
  		ptr = kmap(p);

-   r = copy_from_user(ptr, buf, bytes);
+   r = copy_from_user(ptr + off, buf, bytes);
kunmap(p);
if (r)
return -EFAULT;


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Re: [PATCH] drm/amdgpu: Remove wrapper layer of cgs irq handling

[Christian König]

Am 20.03.2018 um 12:25 schrieb Rex Zhu:

1. remove struct cgs_os_ops
2. delete cgs_linux.h
3. refine the irq code for vega10

Change-Id: I1b1b56c38596e632fe627c436a5072ae5b359b8c
Signed-off-by: Rex Zhu 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/acp/include/acp_gfx_if.h   |   1 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 111 ---
  drivers/gpu/drm/amd/display/dc/os_types.h  |   2 +-
  drivers/gpu/drm/amd/include/cgs_common.h   |   1 -
  drivers/gpu/drm/amd/include/cgs_linux.h| 119 -
  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c|  46 +---
  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c   |  28 +
  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h   |   5 +
  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  36 ---
  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |   5 -
  10 files changed, 56 insertions(+), 298 deletions(-)
  delete mode 100644 drivers/gpu/drm/amd/include/cgs_linux.h

diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h 
b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
index a72ddb2f..feab8eb 100644
--- a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
+++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
@@ -25,7 +25,6 @@
  #define _ACP_GFX_IF_H
  
  #include 

-#include "cgs_linux.h"
  #include "cgs_common.h"
  
  int amd_acp_hw_init(struct cgs_device *cgs_device,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 5b37c1a..0f2b376 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -28,7 +28,6 @@
  #include 
  #include 
  #include "amdgpu.h"
-#include "cgs_linux.h"
  #include "atom.h"
  #include "amdgpu_ucode.h"
  
@@ -182,109 +181,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne

adev->mode_info.atom_context, table, args);
  }
  
-struct cgs_irq_params {

-   unsigned src_id;
-   cgs_irq_source_set_func_t set;
-   cgs_irq_handler_func_t handler;
-   void *private_data;
-};
-
-static int cgs_set_irq_state(struct amdgpu_device *adev,
-struct amdgpu_irq_src *src,
-unsigned type,
-enum amdgpu_interrupt_state state)
-{
-   struct cgs_irq_params *irq_params =
-   (struct cgs_irq_params *)src->data;
-   if (!irq_params)
-   return -EINVAL;
-   if (!irq_params->set)
-   return -EINVAL;
-   return irq_params->set(irq_params->private_data,
-  irq_params->src_id,
-  type,
-  (int)state);
-}
-
-static int cgs_process_irq(struct amdgpu_device *adev,
-  struct amdgpu_irq_src *source,
-  struct amdgpu_iv_entry *entry)
-{
-   struct cgs_irq_params *irq_params =
-   (struct cgs_irq_params *)source->data;
-   if (!irq_params)
-   return -EINVAL;
-   if (!irq_params->handler)
-   return -EINVAL;
-   return irq_params->handler(irq_params->private_data,
-  irq_params->src_id,
-  entry->iv_entry);
-}
-
-static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
-   .set = cgs_set_irq_state,
-   .process = cgs_process_irq,
-};
-
-static int amdgpu_cgs_add_irq_source(void *cgs_device,
-unsigned client_id,
-unsigned src_id,
-unsigned num_types,
-cgs_irq_source_set_func_t set,
-cgs_irq_handler_func_t handler,
-void *private_data)
-{
-   CGS_FUNC_ADEV;
-   int ret = 0;
-   struct cgs_irq_params *irq_params;
-   struct amdgpu_irq_src *source =
-   kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
-   if (!source)
-   return -ENOMEM;
-   irq_params =
-   kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
-   if (!irq_params) {
-   kfree(source);
-   return -ENOMEM;
-   }
-   source->num_types = num_types;
-   source->funcs = _irq_funcs;
-   irq_params->src_id = src_id;
-   irq_params->set = set;
-   irq_params->handler = handler;
-   irq_params->private_data = private_data;
-   source->data = (void *)irq_params;
-   ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
-   if (ret) {
-   kfree(irq_params);
-   kfree(source);
-   }
-
-   return ret;
-}
-
-static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
- unsigned src_id, unsigned type)
-{
-   CGS_FUNC_ADEV;
-
-   if 

[PATCH] drm/amd/amdgpu: fix offset into page with amdgpu_iomem debugfs file

[Tom St Denis]

The offset inside the page wasn't included in the copy call meaning
the start of the page was being read/written instead.

Reported-by: Jay Cornwall 
Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 291dd3d600cd..d2ab40494a4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1996,7 +1996,7 @@ static ssize_t amdgpu_iomem_read(struct file *f, char 
__user *buf,
return -EPERM;
 
ptr = kmap(p);
-   r = copy_to_user(buf, ptr, bytes);
+   r = copy_to_user(buf, ptr + off, bytes);
kunmap(p);
if (r)
return -EFAULT;
@@ -2040,7 +2040,7 @@ static ssize_t amdgpu_iomem_write(struct file *f, const 
char __user *buf,
return -EPERM;
 
ptr = kmap(p);
-   r = copy_from_user(ptr, buf, bytes);
+   r = copy_from_user(ptr + off, buf, bytes);
kunmap(p);
if (r)
return -EFAULT;
-- 
2.14.3

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[PATCH] drm/amdgpu: Remove wrapper layer of cgs irq handling

[Rex Zhu]

1. remove struct cgs_os_ops
2. delete cgs_linux.h
3. refine the irq code for vega10

Change-Id: I1b1b56c38596e632fe627c436a5072ae5b359b8c
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/acp/include/acp_gfx_if.h   |   1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 111 ---
 drivers/gpu/drm/amd/display/dc/os_types.h  |   2 +-
 drivers/gpu/drm/amd/include/cgs_common.h   |   1 -
 drivers/gpu/drm/amd/include/cgs_linux.h| 119 -
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c|  46 +---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c   |  28 +
 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h   |   5 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  36 ---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |   5 -
 10 files changed, 56 insertions(+), 298 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/include/cgs_linux.h

diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h 
b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
index a72ddb2f..feab8eb 100644
--- a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
+++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
@@ -25,7 +25,6 @@
 #define _ACP_GFX_IF_H
 
 #include 
-#include "cgs_linux.h"
 #include "cgs_common.h"
 
 int amd_acp_hw_init(struct cgs_device *cgs_device,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 5b37c1a..0f2b376 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -28,7 +28,6 @@
 #include 
 #include 
 #include "amdgpu.h"
-#include "cgs_linux.h"
 #include "atom.h"
 #include "amdgpu_ucode.h"
 
@@ -182,109 +181,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct 
cgs_device *cgs_device, unsigne
adev->mode_info.atom_context, table, args);
 }
 
-struct cgs_irq_params {
-   unsigned src_id;
-   cgs_irq_source_set_func_t set;
-   cgs_irq_handler_func_t handler;
-   void *private_data;
-};
-
-static int cgs_set_irq_state(struct amdgpu_device *adev,
-struct amdgpu_irq_src *src,
-unsigned type,
-enum amdgpu_interrupt_state state)
-{
-   struct cgs_irq_params *irq_params =
-   (struct cgs_irq_params *)src->data;
-   if (!irq_params)
-   return -EINVAL;
-   if (!irq_params->set)
-   return -EINVAL;
-   return irq_params->set(irq_params->private_data,
-  irq_params->src_id,
-  type,
-  (int)state);
-}
-
-static int cgs_process_irq(struct amdgpu_device *adev,
-  struct amdgpu_irq_src *source,
-  struct amdgpu_iv_entry *entry)
-{
-   struct cgs_irq_params *irq_params =
-   (struct cgs_irq_params *)source->data;
-   if (!irq_params)
-   return -EINVAL;
-   if (!irq_params->handler)
-   return -EINVAL;
-   return irq_params->handler(irq_params->private_data,
-  irq_params->src_id,
-  entry->iv_entry);
-}
-
-static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
-   .set = cgs_set_irq_state,
-   .process = cgs_process_irq,
-};
-
-static int amdgpu_cgs_add_irq_source(void *cgs_device,
-unsigned client_id,
-unsigned src_id,
-unsigned num_types,
-cgs_irq_source_set_func_t set,
-cgs_irq_handler_func_t handler,
-void *private_data)
-{
-   CGS_FUNC_ADEV;
-   int ret = 0;
-   struct cgs_irq_params *irq_params;
-   struct amdgpu_irq_src *source =
-   kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
-   if (!source)
-   return -ENOMEM;
-   irq_params =
-   kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
-   if (!irq_params) {
-   kfree(source);
-   return -ENOMEM;
-   }
-   source->num_types = num_types;
-   source->funcs = _irq_funcs;
-   irq_params->src_id = src_id;
-   irq_params->set = set;
-   irq_params->handler = handler;
-   irq_params->private_data = private_data;
-   source->data = (void *)irq_params;
-   ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
-   if (ret) {
-   kfree(irq_params);
-   kfree(source);
-   }
-
-   return ret;
-}
-
-static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
- unsigned src_id, unsigned type)
-{
-   CGS_FUNC_ADEV;
-
-   if (!adev->irq.client[client_id].sources)
-   return -EINVAL;
-
-   return amdgpu_irq_get(adev, 

Re: [Linaro-mm-sig] [PATCH 1/5] dma-buf: add optional invalidate_mappings callback v2

[Christian König]

Am 20.03.2018 um 08:44 schrieb Daniel Vetter:

On Mon, Mar 19, 2018 at 5:23 PM, Christian König
 wrote:

Am 19.03.2018 um 16:53 schrieb Chris Wilson:

Quoting Christian König (2018-03-16 14:22:32)
[snip, probably lost too must context]

This allows for full grown pipelining, e.g. the exporter can say I need
to move the buffer for some operation. Then let the move operation wait
for all existing fences in the reservation object and install the fence
of the move operation as exclusive fence.

Ok, the situation I have in mind is the non-pipelined case: revoking
dma-buf for mmu_invalidate_range or shrink_slab. I would need a
completion event that can be waited on the cpu for all the invalidate
callbacks. (Essentially an atomic_t counter plus struct completion; a
lighter version of dma_fence, I wonder where I've seen that before ;)


Actually that is harmless.

When you need to unmap a DMA-buf because of mmu_invalidate_range or
shrink_slab you need to wait for it's reservation object anyway.

reservation_object only prevents adding new fences, you still have to
wait for all the current ones to signal. Also, we have dma-access
without fences in i915. "I hold the reservation_object" does not imply
you can just go and nuke the backing storage.


I was not talking about taking the lock, but rather using 
reservation_object_wait_timeout_rcu().


To be more precise you actually can't take the reservation object lock 
in an mmu_invalidate_range callback and you can only trylock it in a 
shrink_slab callback.



This needs to be done to make sure that the backing memory is now idle, it
doesn't matter if the jobs where submitted by DMA-buf importers or your own
driver.

The sg tables pointing to the now released memory might live a bit longer,
but that is unproblematic and actually intended.

I think that's very problematic. One reason for an IOMMU is that you
have device access isolation, and a broken device can't access memory
it shouldn't be able to access. From that security-in-depth point of
view it's not cool that there's some sg tables hanging around still
that a broken GPU could use. And let's not pretend hw is perfect,
especially GPUs :-)


I completely agree on that, but there is unfortunately no other way.

See you simply can't take a reservation object lock in an mmu or slab 
callback, you can only trylock them.


For example it would require changing all allocations done while holding 
any reservation lock to GFP_NOIO.



When we would try to destroy the sg tables in an mmu_invalidate_range or
shrink_slab callback we would run into a lockdep horror.

So I'm no expert on this, but I think this is exactly what we're doing
in i915. Kinda no other way to actually free the memory without
throwing all the nice isolation aspects of an IOMMU into the wind. Can
you please paste the lockdeps you've seen with amdgpu when trying to
do that?


Taking a quick look at i915 I can definitely say that this is actually 
quite buggy what you guys do here.


For coherent usage you need to install some lock to prevent concurrent 
get_user_pages(), command submission and 
invalidate_range_start/invalidate_range_end from the MMU notifier.


Otherwise you can't guarantee that you are actually accessing the right 
page in the case of a fork() or mprotect().


Felix and I hammered for quite some time on amdgpu until all of this was 
handled correctly, see drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c.


I can try to gather the lockdep splat from my mail history, but it 
essentially took us multiple years to get rid of all of them.


Regards,
Christian.


-Daniel


Regards,
Christian.


Even so, it basically means passing a fence object down to the async
callbacks for them to signal when they are complete. Just to handle the
non-pipelined version. :|
-Chris
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Re: [PATCH] drm/amdgpu: give more chance for tlb flush if failed

[Christian König]

Am 20.03.2018 um 07:29 schrieb Emily Deng:

under SR-IOV sometimes CPU based tlb flush would timeout
within the given 100ms period, instead let it fail and
continue we can give it more chance to repeat the
tlb flush on the failed VMHUB

this could fix the massive "Timeout waiting for VM flush ACK"
error during vk_encoder test.


Well that one is a big NAK since it once more just hides the real 
problem that we sometimes drop register writes.


What we did during debugging to avoid the problem is the following:
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index a70cbc45c4c1..3536d50375fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -338,6 +338,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct 
amdgpu_device *adev,

    u32 tmp = gmc_v9_0_get_invalidate_req(vmid);

    WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+   while (RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng) != tmp) {
+   DRM_ERROR("Need one more try to write the 
VMHUB flush request!");

+   WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+   }

    /* Busy wait for ACK.*/
    for (j = 0; j < 100; j++) {


But that can only be a temporary workaround as well.

The question is rather can you reliable reproduce this issue with the 
vk_encoder test?


Thanks,
Christian.



Signed-off-by: Monk Liu 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 24 +++-
  1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a70cbc4..517712b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -329,13 +329,18 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev,
  {
/* Use register 17 for GART */
const unsigned eng = 17;
-   unsigned i, j;
+   unsigned i, j, loop = 0;
+   unsigned flush_done = 0;
+
+retry:
  
  	spin_lock(>gmc.invalidate_lock);
  
  	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {

struct amdgpu_vmhub *hub = >vmhub[i];
u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
+   if (flush_done & (1 << i)) /* this vmhub flushed */
+   continue;
  
  		WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
  
@@ -347,8 +352,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,

break;
cpu_relax();
}
-   if (j < 100)
+   if (j < 100) {
+   flush_done |= (1 << i);
continue;
+   }
  
  		/* Wait for ACK with a delay.*/

for (j = 0; j < adev->usec_timeout; j++) {
@@ -358,15 +365,22 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev,
break;
udelay(1);
}
-   if (j < adev->usec_timeout)
+   if (j < adev->usec_timeout) {
+   flush_done |= (1 << i);
continue;
-
-   DRM_ERROR("Timeout waiting for VM flush ACK!\n");
+   }
}
  
  	spin_unlock(>gmc.invalidate_lock);

+   if (flush_done != 3) {
+   if (loop++ < 3)
+   goto retry;
+   else
+   DRM_ERROR("Timeout waiting for VM flush ACK!\n");
+   }
  }
  
+

  static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
  {


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Re: [PATCH] drm/amdgpu: disable job timeout on GPU reset disabled

[Christian König]

Hi Evan,

that one is perfect if you ask me. Just reading up on the history of 
that patch, Alex what was your concern with that?


Regarding printing this as error, that's a really good point as well. We 
should probably reduce it to a warning or even info severity.


Regards,
Christian.

Am 20.03.2018 um 03:11 schrieb Quan, Evan:

Hi Christian,

The messages prompted on timeout are Errors not just Warnings although we did 
not see any real problem(for the dgemm special case). That's why we say it 
confusing.
And i suppose you want a fix like my previous patch(see attachment).

Regards,
Evan

-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Monday, March 19, 2018 5:42 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: Re: [PATCH] drm/amdgpu: disable job timeout on GPU reset
disabled

Am 19.03.2018 um 07:08 schrieb Evan Quan:

Since under some heavy computing environment(dgemm test), it takes the
asic over 10+ seconds to finish the dispatched single job which will
trigger the timeout. It's quite confusing although it does not seem to
bring any real problems.
As a quick workround, we choose to disable timeout when GPU reset is
disabled.

NAK, I enabled those warning intentionally even when the GPU recovery is
disabled to have a hint in the logs what goes wrong.

Please only increase the timeout for the compute queue and/or add a
separate timeout for them.

Regards,
Christian.



Change-Id: I3a95d856ba4993094dc7b6269649e470c5b053d2
Signed-off-by: Evan Quan 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
   1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8bd9c3f..9d6a775 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -861,6 +861,13 @@ static void

amdgpu_device_check_arguments(struct amdgpu_device *adev)

amdgpu_lockup_timeout = 1;
}

+   /*
+* Disable timeout when GPU reset is disabled to avoid confusing
+* timeout messages in the kernel log.
+*/
+   if (amdgpu_gpu_recovery == 0 || amdgpu_gpu_recovery == -1)
+   amdgpu_lockup_timeout = INT_MAX;
+
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev,

amdgpu_fw_load_type);

   }



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[PATCH] drm/amd/pp: Fix gfx ring test failed on Fiji without hw avfs support

[Rex Zhu]

caused by
'commit ca82cec868d1 ("drm/amd/pp: Simplified the avfs btc state on smu7")'

Change-Id: Ice0012e74ec3ef25cc561f8515ea6a553567d8a6
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  | 3 +++
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 6 --
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 43432e4..faef783 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -263,6 +263,9 @@ static int fiji_setup_graphics_level_structure(struct 
pp_hwmgr *hwmgr)
 
 static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr)
 {
+   if (!hwmgr->avfs_supported)
+   return 0;
+
PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics 
Level"
" table over to SMU",
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index f6b1298..997a777 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -172,11 +172,13 @@ static int 
polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
 }
 
 
-static int
-polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
+static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
 {
struct smu7_smumgr *smu_data = (struct smu7_smumgr 
*)(hwmgr->smu_backend);
 
+   if (!hwmgr->avfs_supported)
+   return 0;
+
PP_ASSERT_WITH_CODE(0 == 
polaris10_setup_graphics_level_structure(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level 
table over to SMU",
return -EINVAL);
-- 
1.9.1

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Re: [PATCH] drm/amdgpu: re-validate per VM BOs if required

[zhoucm1]

On 2018年03月20日 15:49, zhoucm1 wrote:



On 2018年03月19日 18:50, Christian König wrote:

If a per VM BO ends up in a allowed domain it never moves back into the
prefered domain.

Signed-off-by: Christian König 
Yeah, it's better than mine, Reviewed-by: Chunming Zhou 



the left problem is BOs validation order.
For old bo list usage, it has fixed order for BOs in bo list,
but for per-vm-bo feature, the order isn't fixed, which will result in 
the performance is undulate.
e.g. steam game F1 generally is 40fps when using old bo list, it's 
very stable, but when enabling per-vm-bo feature, the fps is between 
37~40fps.

even worse, sometime, fps could drop to 18fps.
the root cause is some *KEY* BOs are randomly placed to allowed domain 
without fixed validation order.
For old bo list case, its later BOs can be evictable, so the front BOs 
are validated with preferred domain first, that is also why the 
performance is stable to 40fps when using old bo list.


Some more thinking:
Could user space pass validation order for per-vm BOs? or set BOs index 
for every per-vm BO?


Any comment?


Regards,
David Zhou



Any thought?

Regards,
David Zhou


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +--
  1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 24474294c92a..e8b515dd032c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1770,14 +1770,16 @@ int amdgpu_vm_handle_moved(struct 
amdgpu_device *adev,

    spin_lock(>status_lock);
  while (!list_empty(>moved)) {
-    struct amdgpu_bo_va *bo_va;
  struct reservation_object *resv;
+    struct amdgpu_bo_va *bo_va;
+    struct amdgpu_bo *bo;
    bo_va = list_first_entry(>moved,
  struct amdgpu_bo_va, base.vm_status);
  spin_unlock(>status_lock);
  -    resv = bo_va->base.bo->tbo.resv;
+    bo = bo_va->base.bo;
+    resv = bo->tbo.resv;
    /* Per VM BOs never need to bo cleared in the page tables */
  if (resv == vm->root.base.bo->tbo.resv)
@@ -1797,6 +1799,15 @@ int amdgpu_vm_handle_moved(struct 
amdgpu_device *adev,

  reservation_object_unlock(resv);
    spin_lock(>status_lock);
+
+    /* If the BO prefers to be in VRAM, but currently isn't add it
+ * back to the evicted list so that it gets validated again on
+ * the next command submission.
+ */
+    if (resv == vm->root.base.bo->tbo.resv &&
+    bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM &&
+    bo->tbo.mem.mem_type != TTM_PL_VRAM)
+    list_add_tail(_va->base.vm_status, >evicted);
  }
  spin_unlock(>status_lock);




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[PATCH 2/2] drm/amdgpu: Fix kernel NULL pointer dereference in dpm functions

[Rex Zhu]

caused by
'commit 83e3c4615872 ("drm/amdgpu: Remove wrapper layer of smu ip functions")'

BUG: unable to handle kernel NULL pointer dereference at 05d8
[  313.241459] IP: ci_dpm_read_sensor+0x37/0xf0 [amdgpu]

Change-Id: Iac0cf26264ccbc60181ccd9bba79fe3c4e420456
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 1 +
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 98d1dd2..47ef3e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6244,6 +6244,7 @@ static int ci_dpm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
adev->powerplay.pp_funcs = _dpm_funcs;
+   adev->powerplay.pp_handle = adev;
ci_dpm_set_irq_funcs(adev);
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 81babe0..26ba984 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2963,6 +2963,7 @@ static int kv_dpm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
adev->powerplay.pp_funcs = _dpm_funcs;
+   adev->powerplay.pp_handle = adev;
kv_dpm_set_irq_funcs(adev);
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 3bfcf0d..672eaff 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7917,6 +7917,7 @@ static int si_dpm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
adev->powerplay.pp_funcs = _dpm_funcs;
+   adev->powerplay.pp_handle = adev;
si_dpm_set_irq_funcs(adev);
return 0;
 }
-- 
1.9.1

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[PATCH 1/2] drm/amdgpu: Fix kernel NULL pointer dereference when amdgpu fini

[Rex Zhu]

Change-Id: Ibef63da7a4725651065fd316385c8521ec31897b
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5bb88aa..f105116 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1493,7 +1493,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
continue;
 
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
-   adev->ip_blocks[i].version->type != 
AMD_IP_BLOCK_TYPE_VCE) {
+   adev->ip_blocks[i].version->type != 
AMD_IP_BLOCK_TYPE_VCE &&
+   
adev->ip_blocks[i].version->funcs->set_clockgating_state) {
/* ungate blocks before hw fini so that we can shutdown 
the blocks safely */
r = 
adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,

 AMD_CG_STATE_UNGATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 11dfe57..3a5ca46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -259,6 +259,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
}
}
kfree(adev->irq.client[i].sources);
+   adev->irq.client[i].sources = NULL;
}
 }
 
-- 
1.9.1

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[PATCH] drm/amdgpu: Don't change preferred domian when fallback GTT v4

[Chunming Zhou]

v2: add sanity checking
v3: make code open
v4: also handle visible to invisible fallback

Change-Id: I2cf672ad36b8b4cc1a6b2e704f786bf6a155d9ce
Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 16 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 19 ---
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 6e6570ff9f8b..8328684aee06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -76,23 +76,11 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
unsigned long size,
}
}
 
-retry:
r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
 flags, NULL, resv, );
if (r) {
-   if (r != -ERESTARTSYS) {
-   if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
-   flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-   goto retry;
-   }
-
-   if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
-   initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
-   goto retry;
-   }
-   DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, 
%d)\n",
- size, initial_domain, alignment, r);
-   }
+   DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
+ size, initial_domain, alignment, r);
return r;
}
*obj = >gem_base;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index b3310219e0ac..84c5e9db1b39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -440,12 +440,25 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 #endif
 
bo->tbo.bdev = >mman.bdev;
-   amdgpu_ttm_placement_from_domain(bo, domain);
-
+retry:
+   amdgpu_ttm_placement_from_domain(bo, bo->preferred_domains);
r = ttm_bo_init_reserved(>mman.bdev, >tbo, size, type,
 >placement, page_align, , acc_size,
 sg, resv, _ttm_bo_destroy);
-   if (unlikely(r != 0))
+
+   if (unlikely(r && r != -ERESTARTSYS)) {
+   if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
+   bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   goto retry;
+   } else if (bo->allowed_domains != bo->preferred_domains) {
+   amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
+   r = ttm_bo_init_reserved(>mman.bdev, >tbo, size,
+type, >placement, page_align,
+, acc_size, sg, resv,
+_ttm_bo_destroy);
+   }
+   }
+   if (unlikely(r))
return r;
 
if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
-- 
2.14.1

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Re: [PATCH] drm/amdgpu: re-validate per VM BOs if required

[zhoucm1]

On 2018年03月19日 18:50, Christian König wrote:

If a per VM BO ends up in a allowed domain it never moves back into the
prefered domain.

Signed-off-by: Christian König 
Yeah, it's better than mine, Reviewed-by: Chunming Zhou 



the left problem is BOs validation order.
For old bo list usage, it has fixed order for BOs in bo list,
but for per-vm-bo feature, the order isn't fixed, which will result in 
the performance is undulate.
e.g. steam game F1 generally is 40fps when using old bo list, it's very 
stable, but when enabling per-vm-bo feature, the fps is between 37~40fps.


Any thought?

Regards,
David Zhou


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +--
  1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 24474294c92a..e8b515dd032c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1770,14 +1770,16 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
  
  	spin_lock(>status_lock);

while (!list_empty(>moved)) {
-   struct amdgpu_bo_va *bo_va;
struct reservation_object *resv;
+   struct amdgpu_bo_va *bo_va;
+   struct amdgpu_bo *bo;
  
  		bo_va = list_first_entry(>moved,

struct amdgpu_bo_va, base.vm_status);
spin_unlock(>status_lock);
  
-		resv = bo_va->base.bo->tbo.resv;

+   bo = bo_va->base.bo;
+   resv = bo->tbo.resv;
  
  		/* Per VM BOs never need to bo cleared in the page tables */

if (resv == vm->root.base.bo->tbo.resv)
@@ -1797,6 +1799,15 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
reservation_object_unlock(resv);
  
  		spin_lock(>status_lock);

+
+   /* If the BO prefers to be in VRAM, but currently isn't add it
+* back to the evicted list so that it gets validated again on
+* the next command submission.
+*/
+   if (resv == vm->root.base.bo->tbo.resv &&
+   bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM &&
+   bo->tbo.mem.mem_type != TTM_PL_VRAM)
+   list_add_tail(_va->base.vm_status, >evicted);
}
spin_unlock(>status_lock);
  


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Re: [Linaro-mm-sig] [PATCH 1/5] dma-buf: add optional invalidate_mappings callback v2

[Daniel Vetter]

On Mon, Mar 19, 2018 at 5:23 PM, Christian König
 wrote:
> Am 19.03.2018 um 16:53 schrieb Chris Wilson:
>>
>> Quoting Christian König (2018-03-16 14:22:32)
>> [snip, probably lost too must context]
>>>
>>> This allows for full grown pipelining, e.g. the exporter can say I need
>>> to move the buffer for some operation. Then let the move operation wait
>>> for all existing fences in the reservation object and install the fence
>>> of the move operation as exclusive fence.
>>
>> Ok, the situation I have in mind is the non-pipelined case: revoking
>> dma-buf for mmu_invalidate_range or shrink_slab. I would need a
>> completion event that can be waited on the cpu for all the invalidate
>> callbacks. (Essentially an atomic_t counter plus struct completion; a
>> lighter version of dma_fence, I wonder where I've seen that before ;)
>
>
> Actually that is harmless.
>
> When you need to unmap a DMA-buf because of mmu_invalidate_range or
> shrink_slab you need to wait for it's reservation object anyway.

reservation_object only prevents adding new fences, you still have to
wait for all the current ones to signal. Also, we have dma-access
without fences in i915. "I hold the reservation_object" does not imply
you can just go and nuke the backing storage.

> This needs to be done to make sure that the backing memory is now idle, it
> doesn't matter if the jobs where submitted by DMA-buf importers or your own
> driver.
>
> The sg tables pointing to the now released memory might live a bit longer,
> but that is unproblematic and actually intended.

I think that's very problematic. One reason for an IOMMU is that you
have device access isolation, and a broken device can't access memory
it shouldn't be able to access. From that security-in-depth point of
view it's not cool that there's some sg tables hanging around still
that a broken GPU could use. And let's not pretend hw is perfect,
especially GPUs :-)

> When we would try to destroy the sg tables in an mmu_invalidate_range or
> shrink_slab callback we would run into a lockdep horror.

So I'm no expert on this, but I think this is exactly what we're doing
in i915. Kinda no other way to actually free the memory without
throwing all the nice isolation aspects of an IOMMU into the wind. Can
you please paste the lockdeps you've seen with amdgpu when trying to
do that?
-Daniel

>
> Regards,
> Christian.
>
>>
>> Even so, it basically means passing a fence object down to the async
>> callbacks for them to signal when they are complete. Just to handle the
>> non-pipelined version. :|
>> -Chris
>> ___
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>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
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-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH] drm/amd/amdgpu: passing i2s instance value as platform data

[Vijendar Mukunda]

i2s instance value is passed as platform data to dwc driver.
this parameter will be useful to distinguish current i2s
instance value when multiple i2s controller instances are created.

Signed-off-by: Vijendar Mukunda 
Reviewed-by: Alex Deucher 
---
v1->v2: moved I2S instance macro definitions to designware header file
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 6cca4d1..b80c43f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -347,6 +347,7 @@ static int acp_hw_init(void *handle)
i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
+   i2s_pdata[0].i2s_instance = I2S_SP_INSTANCE;
switch (adev->asic_type) {
case CHIP_STONEY:
i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
@@ -362,6 +363,7 @@ static int acp_hw_init(void *handle)
i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
+   i2s_pdata[1].i2s_instance = I2S_SP_INSTANCE;
 
i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
switch (adev->asic_type) {
@@ -376,6 +378,7 @@ static int acp_hw_init(void *handle)
i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
+   i2s_pdata[2].i2s_instance = I2S_BT_INSTANCE;
 
adev->acp.acp_res[0].name = "acp2x_dma";
adev->acp.acp_res[0].flags = IORESOURCE_MEM;
-- 
2.7.4

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[PATCH] drm/amdgpu: fix a kcq hang issue for SRIOV

[Emily Deng]

issue:
the vmflush in KCQ could be preempted (not like GFX ring
which doesn't allow preemption in ring buffer) and this lead
to vm flush fail when there is a world switch during
the vm flush procedure (between write invalidate request
and query invalidate ack)

fix:
separate vm flush for gfx and compute ring, and use
the new format command in compute's vm flush which
use only one package so no preemption could allowed

Signed-off-by: Monk Liu 
Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 10 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 14 +-
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a7e2229..986659f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1790,6 +1790,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), 
(d), (v), (m))
+#define amdgpu_ring_emit_reg_wait1(r, d0, d1, v, m) 
(r)->funcs->emit_reg_wait1((r), (d0), (d1), (v), (m))
 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 1d0d250..d85df5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -152,6 +152,8 @@ struct amdgpu_ring_funcs {
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
  uint32_t val, uint32_t mask);
+   void (*emit_reg_wait1)(struct amdgpu_ring *ring, uint32_t reg0,
+   uint32_t reg1, uint32_t val, uint32_t mask);
void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
/* priority functions */
void (*set_priority) (struct amdgpu_ring *ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d1d2c27..d36b29e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4014,6 +4014,13 @@ static void gfx_v9_0_ring_emit_reg_wait(struct 
amdgpu_ring *ring, uint32_t reg,
gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
 }
 
+static void gfx_v9_0_ring_emit_reg_wait_compute(struct amdgpu_ring *ring,
+   uint32_t reg0, uint32_t reg1,
+   uint32_t val, uint32_t mask)
+{
+   gfx_v9_0_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, val, mask, 0x20);
+}
+
 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
 enum amdgpu_interrupt_state 
state)
 {
@@ -4351,7 +4358,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* hdp invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-   SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
+   (SOC15_FLUSH_GPU_TLB_NUM_WREG - 1) * 5 +
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
2 + /* gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm 
fence */
@@ -4369,6 +4376,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
.set_priority = gfx_v9_0_ring_set_priority_compute,
.emit_wreg = gfx_v9_0_ring_emit_wreg,
.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
+   .emit_reg_wait1 = gfx_v9_0_ring_emit_reg_wait_compute,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 517712b..60be1a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -380,7 +380,6 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev,
}
 }
 
-
 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
 {
@@ -399,11 +398,16 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
  upper_32_bits(pd_addr));
 
-   amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
 
-   /* wait for the invalidate to complete 

[PATCH] drm/amdgpu: give more chance for tlb flush if failed

[Emily Deng]

under SR-IOV sometimes CPU based tlb flush would timeout
within the given 100ms period, instead let it fail and
continue we can give it more chance to repeat the
tlb flush on the failed VMHUB

this could fix the massive "Timeout waiting for VM flush ACK"
error during vk_encoder test.

Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 24 +++-
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a70cbc4..517712b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -329,13 +329,18 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev,
 {
/* Use register 17 for GART */
const unsigned eng = 17;
-   unsigned i, j;
+   unsigned i, j, loop = 0;
+   unsigned flush_done = 0;
+
+retry:
 
spin_lock(>gmc.invalidate_lock);
 
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vmhub *hub = >vmhub[i];
u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
+   if (flush_done & (1 << i)) /* this vmhub flushed */
+   continue;
 
WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 
@@ -347,8 +352,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev,
break;
cpu_relax();
}
-   if (j < 100)
+   if (j < 100) {
+   flush_done |= (1 << i);
continue;
+   }
 
/* Wait for ACK with a delay.*/
for (j = 0; j < adev->usec_timeout; j++) {
@@ -358,15 +365,22 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev,
break;
udelay(1);
}
-   if (j < adev->usec_timeout)
+   if (j < adev->usec_timeout) {
+   flush_done |= (1 << i);
continue;
-
-   DRM_ERROR("Timeout waiting for VM flush ACK!\n");
+   }
}
 
spin_unlock(>gmc.invalidate_lock);
+   if (flush_done != 3) {
+   if (loop++ < 3)
+   goto retry;
+   else
+   DRM_ERROR("Timeout waiting for VM flush ACK!\n");
+   }
 }
 
+
 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
 {
-- 
2.7.4

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[PATCH libdrm] headers: sync up amdgpu_drm.h with drm-next

[Qiang Yu]

From: Rex Zhu 

Add sensor_info type
AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK
AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK

Reviewed-by: Evan Quan 
Signed-off-by: Rex Zhu 
---
 include/drm/amdgpu_drm.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index f9d81bf..c519776 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -723,6 +723,10 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_SENSOR_VDDNB0x6
/* Subquery id: Query graphics voltage */
#define AMDGPU_INFO_SENSOR_VDDGFX   0x7
+   /* Subquery id: Query GPU stable pstate shader clock */
+   #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK   0x8
+   /* Subquery id: Query GPU stable pstate memory clock */
+   #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK   0x9
 /* Number of VRAM page faults on CPU access. */
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS   0x1E
 #define AMDGPU_INFO_VRAM_LOST_COUNTER  0x1F
-- 
1.9.1

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