[PATCH] drm/amd/display: disable FBC on underlay pipe

[Shirish S]

FBC is not applicable for the underlay pipe,
hence disallow enabling and disabling of the same.

This also fixes the BUG hit of calling sleep in
atomic context.

Signed-off-by: Shirish S 
Reviewed-by: Roman Li 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5dbd433..64d0bca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2765,6 +2765,9 @@ static void dce110_program_front_end_for_pipe(
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
+#if defined(CONFIG_DRM_AMD_DC_FBC)
+   unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
+#endif
unsigned int i;
DC_LOGGER_INIT();
memset(_entry, 0, sizeof(tbl_entry));
@@ -2806,7 +2809,9 @@ static void dce110_program_front_end_for_pipe(
program_scaler(dc, pipe_ctx);
 
 #if defined(CONFIG_DRM_AMD_DC_FBC)
-   if (dc->fbc_compressor && old_pipe->stream) {
+   /* fbc not applicable on Underlay pipe */
+   if (dc->fbc_compressor && old_pipe->stream &&
+   pipe_ctx->pipe_idx != underlay_idx) {
if (plane_state->tiling_info.gfx8.array_mode == 
DC_ARRAY_LINEAR_GENERAL)

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
else
-- 
2.7.4

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Re: [PATCH xf86-video-amdgpu 2/2] Wait for pending flips in drmmode_output_set_tear_free

[Michel Dänzer]

On 2018-04-26 08:48 PM, Samuel Li wrote:
> On 2018-04-26 11:58 AM, Michel Dänzer wrote:
>> From: Michel Dänzer 
>>
>> This prevents a nested call to drmHandleEvent, which would hang.
>>
>> Fixes hangs when disabling TearFree on a CRTC while a DRI3 client is
>> page flipping.
>>
>> Signed-off-by: Michel Dänzer 
>> ---
>>  src/drmmode_display.c | 9 +
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
>> index cf1e5d1f1..4fac645b9 100644
>> --- a/src/drmmode_display.c
>> +++ b/src/drmmode_display.c
>> @@ -1750,6 +1750,15 @@ drmmode_output_set_tear_free(AMDGPUEntPtr pAMDGPUEnt,
>>  drmmode_output->tear_free = tear_free;
>>  
>>  if (crtc) {
>> +drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
>> +
>> +/* Wait for pending flips before drmmode_set_mode_major calls 
> Trailing white space.
> Otherwise the two patches are 
>   Reviewed-by: Samuel Li  

Thanks Sam! I removed the trailing white space before pushing.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[PATCH libdrm] amdgpu: Deinitialize vamgr_high{,_32}

[Michel Dänzer]

From: Michel Dänzer 

Fixes memory leaks.

Signed-off-by: Michel Dänzer 
---
 amdgpu/amdgpu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index d81efcf8..983b19ab 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -128,6 +128,8 @@ static void 
amdgpu_device_free_internal(amdgpu_device_handle dev)
 {
amdgpu_vamgr_deinit(>vamgr_32);
amdgpu_vamgr_deinit(>vamgr);
+   amdgpu_vamgr_deinit(>vamgr_high_32);
+   amdgpu_vamgr_deinit(>vamgr_high);
util_hash_table_destroy(dev->bo_flink_names);
util_hash_table_destroy(dev->bo_handles);
pthread_mutex_destroy(>bo_table_mutex);
-- 
2.17.0

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[PATCH umr] Capture COMPUTE shaders in ring decoding as well.

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 src/lib/ring_decode.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index 42265e0a74c9..7e3218a46145 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -774,9 +774,9 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
struct umr_ring_decoder
{
char *tmp = umr_reg_name(asic, 
decoder->pm4.next_write_mem.addr_lo);
printf("%s <= %s0x%08lx%s", 
tmp, YELLOW, (unsigned long)ib, RST);
-   if (strstr(tmp, 
"SPI_SHADER_PGM_LO_")) {
+   if (strstr(tmp, 
"SPI_SHADER_PGM_LO_") || strstr(tmp, "COMPUTE_PGM_LO")) {

decoder->pm4.next_ib_state.ib_addr_lo = ib;
-   } else if (strstr(tmp, 
"SPI_SHADER_PGM_HI_")) {
+   } else if (strstr(tmp, 
"SPI_SHADER_PGM_HI_") || strstr(tmp, "COMPUTE_PGM_HI")) {

decoder->pm4.next_ib_state.ib_addr_hi = ib;

decoder->pm4.next_ib_state.ib_vmid = decoder->next_ib_info.vmid;
add_shader(asic, 
decoder);
-- 
2.14.3

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[PATCH v2 1/2] drm/ttm: Only allocate huge pages with new flag TTM_PAGE_FLAG_TRANSHUGE

[Michel Dänzer]

From: Michel Dänzer 

Previously, TTM would always (with CONFIG_TRANSPARENT_HUGEPAGE enabled)
try to allocate huge pages. However, not all drivers can take advantage
of huge pages, but they would incur the overhead for allocating and
freeing them anyway.

Now, drivers which can take advantage of huge pages need to set the new
flag TTM_PAGE_FLAG_TRANSHUGE to get them. Drivers not setting this flag
no longer incur any overhead for allocating or freeing huge pages.

v2:
* Also guard swapping of consecutive pages in ttm_get_pages
* Reword commit log, hopefully clearer now

Cc: sta...@vger.kernel.org
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  2 +-
 drivers/gpu/drm/ttm/ttm_page_alloc.c | 35 +---
 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c |  8 --
 include/drm/ttm/ttm_tt.h |  1 +
 4 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index dfd22db13fb1..e03e9e361e2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -988,7 +988,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct 
ttm_buffer_object *bo,
return NULL;
}
gtt->ttm.ttm.func = _backend_func;
-   if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
+   if (ttm_sg_tt_init(>ttm, bo, page_flags | 
TTM_PAGE_FLAG_TRANSHUGE)) {
kfree(gtt);
return NULL;
}
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index f0481b7b60c5..476d668e1cbd 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -760,7 +760,7 @@ static void ttm_put_pages(struct page **pages, unsigned 
npages, int flags,
 {
struct ttm_page_pool *pool = ttm_get_pool(flags, false, cstate);
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-   struct ttm_page_pool *huge = ttm_get_pool(flags, true, cstate);
+   struct ttm_page_pool *huge = NULL;
 #endif
unsigned long irq_flags;
unsigned i;
@@ -780,7 +780,8 @@ static void ttm_put_pages(struct page **pages, unsigned 
npages, int flags,
}
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-   if (!(flags & TTM_PAGE_FLAG_DMA32)) {
+   if ((flags & (TTM_PAGE_FLAG_DMA32 | 
TTM_PAGE_FLAG_TRANSHUGE)) ==
+   TTM_PAGE_FLAG_TRANSHUGE) {
for (j = 0; j < HPAGE_PMD_NR; ++j)
if (p++ != pages[i + j])
break;
@@ -805,6 +806,8 @@ static void ttm_put_pages(struct page **pages, unsigned 
npages, int flags,
 
i = 0;
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
+   if (flags & TTM_PAGE_FLAG_TRANSHUGE)
+   huge = ttm_get_pool(flags, true, cstate);
if (huge) {
unsigned max_size, n2free;
 
@@ -877,7 +880,7 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
 {
struct ttm_page_pool *pool = ttm_get_pool(flags, false, cstate);
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-   struct ttm_page_pool *huge = ttm_get_pool(flags, true, cstate);
+   struct ttm_page_pool *huge = NULL;
 #endif
struct list_head plist;
struct page *p = NULL;
@@ -906,7 +909,8 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
 
i = 0;
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-   if (!(gfp_flags & GFP_DMA32)) {
+   if ((flags & (TTM_PAGE_FLAG_DMA32 | TTM_PAGE_FLAG_TRANSHUGE)) ==
+   TTM_PAGE_FLAG_TRANSHUGE) {
while (npages >= HPAGE_PMD_NR) {
gfp_t huge_flags = gfp_flags;
 
@@ -933,9 +937,13 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
return -ENOMEM;
}
 
-   /* Swap the pages if we detect consecutive order */
-   if (i > first && pages[i - 1] == p - 1)
-   swap(p, pages[i - 1]);
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+   if (flags & TTM_PAGE_FLAG_TRANSHUGE) {
+   /* Swap the pages if we detect consecutive 
order */
+   if (i > first && pages[i - 1] == p - 1)
+   swap(p, pages[i - 1]);
+   }
+#endif
 
pages[i++] = p;
--npages;
@@ -946,6 +954,8 @@ static int ttm_get_pages(struct page **pages, unsigned 
npages, int flags,
count = 0;
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
+   if (flags & TTM_PAGE_FLAG_TRANSHUGE)
+   huge = ttm_get_pool(flags, true, cstate);
if (huge && npages >= HPAGE_PMD_NR) {

amdgpu 0000:01:00.0: IH ring buffer overflow (0x00000010, 0x00000000, 0x00000020)

[Paul Menzel]

Dear Linux AMD folks,


I get the overrun message below.


$ more /proc/version
Linux version 4.14.30.mx64.211 (r...@holidayincambodia.molgen.mpg.de) (gcc 
version 7.3.0 (GCC)) #1 SMP Tue Mar 27 12:40:07 CEST 2018
$ lspci -s 01:00.0
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] 
Bonaire [FirePro W5100]
$ dmesg | grep amdgpu
[   12.382379] [drm] amdgpu kernel modesetting enabled.
[   12.419916] amdgpu :01:00.0: VRAM: 4096M 0x00F4 - 
0x00F4 (4096M used)
[   12.420681] amdgpu :01:00.0: GTT: 1024M 0x - 
0x3FFF
[   12.424246] [drm] amdgpu: 4096M of VRAM memory ready
[   12.424682] [drm] amdgpu: 4096M of GTT memory ready.
[   12.427912] amdgpu :01:00.0: amdgpu: using MSI.
[   12.428389] [drm] amdgpu: irq initialized.
[   12.439899] [drm] amdgpu: dpm initialized
[   12.501392] amdgpu :01:00.0: fence driver on ring 0 use gpu addr 
0x00400080, cpu addr 0xc90002c25080
[   12.502433] amdgpu :01:00.0: fence driver on ring 1 use gpu addr 
0x00400100, cpu addr 0xc90002c25100
[   12.503412] amdgpu :01:00.0: fence driver on ring 2 use gpu addr 
0x00400180, cpu addr 0xc90002c25180
[   12.504440] amdgpu :01:00.0: fence driver on ring 3 use gpu addr 
0x00400200, cpu addr 0xc90002c25200
[   12.505378] amdgpu :01:00.0: fence driver on ring 4 use gpu addr 
0x00400280, cpu addr 0xc90002c25280
[   12.506438] amdgpu :01:00.0: fence driver on ring 5 use gpu addr 
0x00400300, cpu addr 0xc90002c25300
[   12.507474] amdgpu :01:00.0: fence driver on ring 6 use gpu addr 
0x00400380, cpu addr 0xc90002c25380
[   12.508579] amdgpu :01:00.0: fence driver on ring 7 use gpu addr 
0x00400400, cpu addr 0xc90002c25400
[   12.509629] amdgpu :01:00.0: fence driver on ring 8 use gpu addr 
0x00400480, cpu addr 0xc90002c25480
[   12.511172] amdgpu :01:00.0: fence driver on ring 9 use gpu addr 
0x00400500, cpu addr 0xc90002c25500
[   12.512211] amdgpu :01:00.0: fence driver on ring 10 use gpu addr 
0x00400580, cpu addr 0xc90002c25580
[   12.521048] amdgpu :01:00.0: fence driver on ring 11 use gpu addr 
0x00f40028bd30, cpu addr 0xc90003638d30
[   12.523287] amdgpu :01:00.0: fence driver on ring 12 use gpu addr 
0x00400680, cpu addr 0xc90002c25680
[   12.524345] amdgpu :01:00.0: fence driver on ring 13 use gpu addr 
0x00400700, cpu addr 0xc90002c25700
[   12.823525] fbcon: amdgpudrmfb (fb0) is primary device
[   13.089730] amdgpu :01:00.0: fb0: amdgpudrmfb frame buffer device
[   13.097141] [drm] Initialized amdgpu 3.19.0 20150101 for :01:00.0 on 
minor 1
[90612.637194] amdgpu :01:00.0: IH ring buffer overflow (0x0010, 
0x, 0x0020)


Should this be reported and fixed? How can this be debugged? 
(`drm.debug=0xe`?). We do not know how to reproduce it yet.



Kind regards,

Paul



smime.p7s
Description: S/MIME Cryptographic Signature
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[PATCH] drm/amd/display: disable FBC on underlay pipe

[Shirish S]

FBC is not applicable for the underlay pipe,
hence disallow enabling and disabling of the same.

This also fixes the BUG hit of calling sleep in
atomic context.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5dbd433..64d0bca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2765,6 +2765,9 @@ static void dce110_program_front_end_for_pipe(
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
+#if defined(CONFIG_DRM_AMD_DC_FBC)
+   unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
+#endif
unsigned int i;
DC_LOGGER_INIT();
memset(_entry, 0, sizeof(tbl_entry));
@@ -2806,7 +2809,9 @@ static void dce110_program_front_end_for_pipe(
program_scaler(dc, pipe_ctx);
 
 #if defined(CONFIG_DRM_AMD_DC_FBC)
-   if (dc->fbc_compressor && old_pipe->stream) {
+   /* fbc not applicable on Unerlay pipe */
+   if (dc->fbc_compressor && old_pipe->stream &&
+   pipe_ctx->pipe_idx != underlay_idx) {
if (plane_state->tiling_info.gfx8.array_mode == 
DC_ARRAY_LINEAR_GENERAL)

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
else
-- 
2.7.4

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[PATCH] drm/amd/display: remove need of modeset flag for overlay planes

[Shirish S]

This patch is in continuation to the
"843e3c7 drm/amd/display: defer modeset check in dm_update_planes_state"
where we started to eliminate the dependency on
DRM_MODE_ATOMIC_ALLOW_MODESET to be set by the user space,
which as such is not mandatory.

After deferring, this patch eliminates the dependency on the flag
for overlay planes.

This has to be done in stages as its a pretty complex and requires thorough
testing before we free primary planes as well from dependency on modeset
flag.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1a63c04..87b661d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4174,7 +4174,7 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
}
spin_unlock_irqrestore(>dev->event_lock, flags);
 
-   if (!pflip_needed) {
+   if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
WARN_ON(!dm_new_plane_state->dc_state);
 
plane_states_constructed[planes_count] = 
dm_new_plane_state->dc_state;
@@ -4884,7 +4884,8 @@ static int dm_update_planes_state(struct dc *dc,
 
/* Remove any changed/removed planes */
if (!enable) {
-   if (pflip_needed)
+   if (pflip_needed &&
+   plane && plane->type != DRM_PLANE_TYPE_OVERLAY)
continue;
 
if (!old_plane_crtc)
@@ -4931,7 +4932,8 @@ static int dm_update_planes_state(struct dc *dc,
if (!dm_new_crtc_state->stream)
continue;
 
-   if (pflip_needed)
+   if (pflip_needed &&
+   plane && plane->type != DRM_PLANE_TYPE_OVERLAY)
continue;
 
WARN_ON(dm_new_plane_state->dc_state);
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: Fix display corruption on CI with dpm enabled

[Huang Rui]

On Fri, Apr 27, 2018 at 02:18:40PM +0800, Rex Zhu wrote:
> with dpm enabled, need to get active crtcs in dc/no-dc mode.
> 
> caused by
> 'commit ebb649667a31 ("drm/amdgpu: Set pm_display_cfg in non-dc mode")'
> 
> Signed-off-by: Rex Zhu 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 32 
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 2c82126..b455da4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1878,26 +1878,26 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device 
> *adev)
>   amdgpu_fence_wait_empty(ring);
>   }
>  
> - if (!amdgpu_device_has_dc_support(adev)) {
> - mutex_lock(>pm.mutex);
> - amdgpu_dpm_get_active_displays(adev);
> - adev->pm.pm_display_cfg.num_display = 
> adev->pm.dpm.new_active_crtcs;
> - adev->pm.pm_display_cfg.vrefresh = 
> amdgpu_dpm_get_vrefresh(adev);
> - adev->pm.pm_display_cfg.min_vblank_time = 
> amdgpu_dpm_get_vblank_time(adev);
> - /* we have issues with mclk switching with refresh rates over 
> 120 hz on the non-DC code. */
> - if (adev->pm.pm_display_cfg.vrefresh > 120)
> - adev->pm.pm_display_cfg.min_vblank_time = 0;
> - if (adev->powerplay.pp_funcs->display_configuration_change)
> - adev->powerplay.pp_funcs->display_configuration_change(
> - 
> adev->powerplay.pp_handle,
> - 
> >pm.pm_display_cfg);
> - mutex_unlock(>pm.mutex);
> - }
> -
>   if (adev->powerplay.pp_funcs->dispatch_tasks) {
> + if (!amdgpu_device_has_dc_support(adev)) {
> + mutex_lock(>pm.mutex);
> + amdgpu_dpm_get_active_displays(adev);
> + adev->pm.pm_display_cfg.num_display = 
> adev->pm.dpm.new_active_crtcs;
> + adev->pm.pm_display_cfg.vrefresh = 
> amdgpu_dpm_get_vrefresh(adev);
> + adev->pm.pm_display_cfg.min_vblank_time = 
> amdgpu_dpm_get_vblank_time(adev);
> + /* we have issues with mclk switching with refresh 
> rates over 120 hz on the non-DC code. */
> + if (adev->pm.pm_display_cfg.vrefresh > 120)
> + adev->pm.pm_display_cfg.min_vblank_time = 0;
> + if 
> (adev->powerplay.pp_funcs->display_configuration_change)
> + 
> adev->powerplay.pp_funcs->display_configuration_change(
> + 
> adev->powerplay.pp_handle,
> + 
> >pm.pm_display_cfg);
> + mutex_unlock(>pm.mutex);
> + }
>   amdgpu_dpm_dispatch_task(adev, 
> AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
>   } else {
>   mutex_lock(>pm.mutex);
> + amdgpu_dpm_get_active_displays(adev);
>   /* update battery/ac status */
>   if (power_supply_is_system_supplied() > 0)
>   adev->pm.dpm.ac_power = true;
> -- 
> 1.9.1
> 
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RE: [PATCH] drm/amd/display: Don't return ddc result and read_bytes in same return value

[S, Shirish]

Thanks Harry, it works.

Patch is Reviewed-by: Shirish S 

Regards,
Shirish S

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Harry 
Wentland
Sent: Tuesday, April 24, 2018 8:57 PM
To: amd-gfx@lists.freedesktop.org; S, Shirish ; Deucher, 
Alexander ; S, Shirish 
Cc: Wentland, Harry 
Subject: [PATCH] drm/amd/display: Don't return ddc result and read_bytes in 
same return value

The two ranges overlap.

Signed-off-by: Harry Wentland 
---

Thinking of something like this if this works for you.

Harry

 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 20 +++
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 10 +++---
 .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |  5 +++--
 3 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index c3f3028253c3..b8dd7496b7bc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -83,21 +83,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
I2C_MOT_TRUE : I2C_MOT_FALSE;
enum ddc_result res;
-   ssize_t read_bytes;
+   uint32_t read_bytes = msg->size;
 
if (WARN_ON(msg->size > 16))
return -E2BIG;
 
switch (msg->request & ~DP_AUX_I2C_MOT) {
case DP_AUX_NATIVE_READ:
-   read_bytes = dal_ddc_service_read_dpcd_data(
+   res = dal_ddc_service_read_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
false,
I2C_MOT_UNDEF,
msg->address,
msg->buffer,
-   msg->size);
-   return read_bytes;
+   msg->size,
+   _bytes);
+   break;
case DP_AUX_NATIVE_WRITE:
res = dal_ddc_service_write_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
@@ -108,14 +109,15 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
msg->size);
break;
case DP_AUX_I2C_READ:
-   read_bytes = dal_ddc_service_read_dpcd_data(
+   res = dal_ddc_service_read_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
true,
mot,
msg->address,
msg->buffer,
-   msg->size);
-   return read_bytes;
+   msg->size,
+   _bytes);
+   break;
case DP_AUX_I2C_WRITE:
res = dal_ddc_service_write_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
@@ -137,7 +139,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
 r == DDC_RESULT_SUCESSFULL);
 #endif
 
-   return msg->size;
+   if (res != DDC_RESULT_SUCESSFULL)
+   return -EIO;
+   return read_bytes;
 }
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 49c2face1e7a..ae48d603ebd6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data(
return ret;
 }
 
-ssize_t dal_ddc_service_read_dpcd_data(
+enum ddc_result dal_ddc_service_read_dpcd_data(
struct ddc_service *ddc,
bool i2c,
enum i2c_mot_mode mot,
uint32_t address,
uint8_t *data,
-   uint32_t len)
+   uint32_t len,
+   uint32_t *read)
 {
struct aux_payload read_payload = {
.i2c_over_aux = i2c,
@@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
.mot = mot
};
 
+   *read = 0;
+
if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
BREAK_TO_DEBUGGER();
return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
ddc->ctx->i2caux,
ddc->ddc_pin,
)) {
-   return (ssize_t)command.payloads->length;
+   *read = command.payloads->length;
+   return DDC_RESULT_SUCESSFULL;
}
 
return DDC_RESULT_FAILED_OPERATION;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h 
b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 

Re: [PATCH 1/2] drm/ttm: Add TTM_PAGE_FLAG_TRANSHUGE

[Michel Dänzer]

[ Dropping Roger He, his e-mail address seems to bounce ]

On 2018-04-27 04:51 AM, zhoucm1 wrote:
> On 2018年04月26日 23:06, Michel Dänzer wrote:
>> From: Michel Dänzer 
>>
>> When it's set, TTM tries to allocate huge pages if possible.
> Do you mean original driver doesn't do this?
> From the code, driver always try huge pages if
> CONFIG_TRANSPARENT_HUGEPAGE is enabled.

Right, before this change, TTM would do this unconditionally for all
drivers. The point of this change is not to incur any huge page related
overhead for drivers which can't take advantage of huge pages anyway.
I'll try changing the commit log to make this clearer in v2.


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Re: [PATCH] drm/amdgpu/sriov: reject kms open if TDR not finished or failed

[Michel Dänzer]

On 2018-04-27 10:15 AM, Deng, Emily wrote:
> No, I mean during GPU reset, the app will fail, it is reasonable.

I understand, but I don't agree that it's reasonable. :)


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RE: [PATCH] drm/amdgpu/sriov: reject kms open if TDR not finished or failed

[Deng, Emily]

No, I mean during GPU reset, the app will fail, it is reasonable. The flag 
in_gpu_reset indicates the GPU is in reset state, after reset, we will set the 
flag back.

Best Wishes,
Emily Deng

> -Original Message-
> From: Michel Dänzer [mailto:mic...@daenzer.net]
> Sent: Friday, April 27, 2018 3:52 PM
> To: Deng, Emily ; Liu, Monk 
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu/sriov: reject kms open if TDR not finished
> or failed
> 
> On 2018-04-27 07:29 AM, Deng, Emily wrote:
> > Sorry, I don't get your point, when the GPU is doing a reset, even let
> > the dkms open, the userspace will still fail, so during the reset, any
> > driver open kms is meaningless.
> 
> That needs to be fixed, then. If the GPU reset succeeds, userspace shouldn't
> have to fail.
> 
> 
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> Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amd/pp: Skip fan attributes if fan not present

[Huang Rui]

On Fri, Apr 27, 2018 at 01:52:47PM +0800, Rex Zhu wrote:
> With powerplay enabled, also need to skip fan attributes
> if no fan present.
> 
> Signed-off-by: Rex Zhu 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c  | 21 -
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c |  3 +++
>  2 files changed, 11 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index d9802d9..2c82126 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1364,19 +1364,14 @@ static umode_t hwmon_attributes_visible(struct 
> kobject *kobj,
>   struct amdgpu_device *adev = dev_get_drvdata(dev);
>   umode_t effective_mode = attr->mode;
>  
> - /* handle non-powerplay limitations */
> - if (!adev->powerplay.pp_handle) {
> - /* Skip fan attributes if fan is not present */
> - if (adev->pm.no_fan &&
> - (attr == _dev_attr_pwm1.dev_attr.attr ||
> -  attr == _dev_attr_pwm1_enable.dev_attr.attr ||
> -  attr == _dev_attr_pwm1_max.dev_attr.attr ||
> -  attr == _dev_attr_pwm1_min.dev_attr.attr))
> - return 0;
> - /* requires powerplay */
> - if (attr == _dev_attr_fan1_input.dev_attr.attr)
> - return 0;
> - }
> +
> + /* Skip fan attributes if fan is not present */
> + if (adev->pm.no_fan && (attr == _dev_attr_pwm1.dev_attr.attr ||
> + attr == _dev_attr_pwm1_enable.dev_attr.attr ||
> + attr == _dev_attr_pwm1_max.dev_attr.attr ||
> + attr == _dev_attr_pwm1_min.dev_attr.attr ||
> + attr == _dev_attr_fan1_input.dev_attr.attr))
> + return 0;
>  
>   /* Skip limit attributes if DPM is not enabled */
>   if (!adev->pm.dpm_enabled &&
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index d1052b5..43f0ea8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -223,6 +223,9 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
>   if (ret)
>   goto err;
>  
> + ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
> + hwmgr->thermal_controller.fanInfo.bNoFan;
> +
>   ret = hwmgr->hwmgr_func->backend_init(hwmgr);
>   if (ret)
>   goto err1;
> -- 
> 1.9.1
> 
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Re: [PATCH] drm/amdgpu/sriov: reject kms open if TDR not finished or failed

[Michel Dänzer]

On 2018-04-27 07:29 AM, Deng, Emily wrote:
> Sorry, I don't get your point, when the GPU is doing a reset, even
> let the dkms open, the userspace will still fail, so during the
> reset, any driver open kms is meaningless.

That needs to be fixed, then. If the GPU reset succeeds, userspace
shouldn't have to fail.


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Re: [PATCH] drm/amdgpu/uvd7: add emit_reg_write_reg_wait ring callback

[Huang Rui]

On Thu, Apr 26, 2018 at 07:12:07PM +0800, Xiaojie Yuan wrote:
> Fix the NULL pointer dereference while running amdgpu_test:
> 
> [   54.972246] BUG: unable to handle kernel NULL pointer dereference at 
> 
> [   54.972265] IP:   (null)
> [   54.972273] PGD 0 P4D 0
> [   54.972280] Oops: 0010 [#1] SMP PTI
> [   54.972288] Modules linked in: amdkfd amd_iommu_v2 amdgpu(OE) chash 
> gpu_sched ttm drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea 
> sysfillrect sysimgblt snd_hda_codec_realtek snd_hda_codec_generic 
> snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep 
> intel_rapl snd_pcm snd_seq_midi snd_seq_midi_event snd_rawmidi 
> x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel snd_seq 
> snd_seq_device kvm irqbypass snd_timer crct10dif_pclmul crc32_pclmul 
> ghash_clmulni_intel pcbc snd soundcore joydev input_leds aesni_intel 
> aes_x86_64 crypto_simd glue_helper cryptd idma64 virt_dma mei_me 
> intel_lpss_pci serio_raw intel_cstate intel_rapl_perf shpchp 
> intel_pch_thermal mei mac_hid intel_lpss acpi_pad parport_pc ppdev nfsd lp 
> auth_rpcgss nfs_acl lockd grace sunrpc parport autofs4 hid_generic
> [   54.972434]  usbhid mxm_wmi e1000e psmouse ahci hid libahci wmi 
> pinctrl_sunrisepoint video pinctrl_intel
> [   54.972457] CPU: 6 PID: 1393 Comm: uvd Tainted: G   OE
> 4.16.0-rc7-27fb84fda777 #1
> [   54.972473] Hardware name: MSI MS-7984/Z170 KRAIT GAMING (MS-7984), BIOS 
> B.80 05/11/2016
> [   54.972489] RIP: 0010:  (null)
> [   54.972497] RSP: 0018:aea002c8bcc0 EFLAGS: 00010202
> [   54.972508] RAX:  RBX: 9d30d3c56f60 RCX: 
> 007c0002
> [   54.972522] RDX: 0001a6fb RSI: 0001a6e9 RDI: 
> 9d30d3c56f60
> [   54.972536] RBP: aea002c8bd10 R08: 0002 R09: 
> c06977d0
> [   54.972550] R10: 0040 R11:  R12: 
> 0002
> [   54.972564] R13: 9d30d3c5001c R14: 9d30d3c5 R15: 
> 0006
> [   54.972579] FS:  () GS:9d30eed8() 
> knlGS:
> [   54.972594] CS:  0010 DS:  ES:  CR0: 80050033
> [   54.972606] CR2:  CR3: 0002dbc0a001 CR4: 
> 003606e0
> [   54.972620] DR0:  DR1:  DR2: 
> 
> [   54.972634] DR3:  DR6: fffe0ff0 DR7: 
> 0400
> [   54.972648] Call Trace:
> [   54.972685]  ? gmc_v9_0_emit_flush_gpu_tlb+0x111/0x140 [amdgpu]
> [   54.972721]  uvd_v7_0_ring_emit_vm_flush+0x31/0x70 [amdgpu]
> [   54.972751]  amdgpu_vm_flush+0x5dc/0x6c0 [amdgpu]
> [   54.972787]  ? pp_dpm_powergate_uvd+0x50/0x80 [amdgpu]
> [   54.972816]  amdgpu_ib_schedule+0x120/0x4e0 [amdgpu]
> [   54.972850]  amdgpu_job_run+0x17b/0x1c0 [amdgpu]
> [   54.972861]  drm_sched_main+0x2cc/0x490 [gpu_sched]
> [   54.972873]  ? wait_woken+0x80/0x80
> [   54.972882]  kthread+0x121/0x140
> [   54.972891]  ? drm_sched_job_finish+0xf0/0xf0 [gpu_sched]
> [   54.972902]  ? kthread_create_worker_on_cpu+0x70/0x70
> [   54.972914]  ret_from_fork+0x35/0x40
> [   54.972922] Code:  Bad RIP value.
> [   54.972932] RIP:   (null) RSP: aea002c8bcc0
> [   54.972943] CR2: 
> [   54.972951] ---[ end trace 5feb349263bbf633 ]---
> 
> Change-Id: I0bb6daf47b6946785e7cefec5d05d09a42ca9a3c
> Signed-off-by: Xiaojie Yuan 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 280c0826e183..2251db4048f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1671,6 +1671,7 @@ static const struct amdgpu_ring_funcs 
> uvd_v7_0_ring_vm_funcs = {
>   .end_use = amdgpu_uvd_ring_end_use,
>   .emit_wreg = uvd_v7_0_ring_emit_wreg,
>   .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
> + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
>  };
>  
>  static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
> -- 
> 2.17.0
> 
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Re: [PATCH 2/3] drm/scheduler: Don't call wait_event_killable for signaled process.

[Eric W. Biederman]

Andrey Grodzovsky  writes:

> On 04/26/2018 08:34 AM, Andrey Grodzovsky wrote:
>>
>>
>> On 04/25/2018 08:01 PM, Eric W. Biederman wrote:
>>> Andrey Grodzovsky  writes:
>>>
 On 04/25/2018 01:17 PM, Oleg Nesterov wrote:
> On 04/25, Andrey Grodzovsky wrote:
>> here (drm_sched_entity_fini) is also a bad idea, but we still want to be
>> able to exit immediately
>> and not wait for GPU jobs completion when the reason for reaching this
>> code
>> is because of KILL
>> signal to the user process who opened the device file.
> Can you hook f_op->flush method?
 But this one is called for each task releasing a reference to the the file,
 so
 not sure I see how this solves the problem.
>>> The big question is why do you need to wait during the final closing a
>>> file?
>>>
>>> The wait can be terminated so the wait does not appear to be simply a
>>> matter of correctness.
>>
>> Well, as I understand it, it just means that you don't want to abruptly
>> terminate GPU work in progress without a good
>> reason (such as KILL signal). When we exit we are going to release various
>> resources GPU is still using so we either
>> wait for it to complete or terminate the remaining jobs.

At the point of do_exit you might as well be a KILL signal however you
got there.

> Looked more into code, some correction, drm_sched_entity_fini means the SW job
> queue itself is about to die, so we must
> either wait for completion or terminate any outstanding jobs that are still in
> the SW queue. Anything which already in flight in HW
> will still complete.

It sounds like we don't care if we block the process that had the file
descriptor open, this is just book keeping.  Which allows having a piece
of code that cleans up resources when the GPU is done with the queue but
does not make userspace wait.  (option 1)

For it to make sense that we let the process run there has to be
something that cares about the results being completed.  If all of the
file descriptors are closed and the process is killed I can't see who
will care that the software queue will continue to be processed.  So it
may be reasonable to simply kill the queue (option 2).

If userspace really needs the wait it is probably better done in
f_op->flush so that every close of the file descriptor blocks
until the queue is flushed (option 3).

Do you know if userspace cares about the gpu operations completing?

My skim of the code suggests that nothing actually cares about those
operations, but I really don't know the gpu well.

Eric
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[PATCH] drm/amdgpu: Fix display corruption on CI with dpm enabled

[Rex Zhu]

with dpm enabled, need to get active crtcs in dc/no-dc mode.

caused by
'commit ebb649667a31 ("drm/amdgpu: Set pm_display_cfg in non-dc mode")'

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2c82126..b455da4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1878,26 +1878,26 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device 
*adev)
amdgpu_fence_wait_empty(ring);
}
 
-   if (!amdgpu_device_has_dc_support(adev)) {
-   mutex_lock(>pm.mutex);
-   amdgpu_dpm_get_active_displays(adev);
-   adev->pm.pm_display_cfg.num_display = 
adev->pm.dpm.new_active_crtcs;
-   adev->pm.pm_display_cfg.vrefresh = 
amdgpu_dpm_get_vrefresh(adev);
-   adev->pm.pm_display_cfg.min_vblank_time = 
amdgpu_dpm_get_vblank_time(adev);
-   /* we have issues with mclk switching with refresh rates over 
120 hz on the non-DC code. */
-   if (adev->pm.pm_display_cfg.vrefresh > 120)
-   adev->pm.pm_display_cfg.min_vblank_time = 0;
-   if (adev->powerplay.pp_funcs->display_configuration_change)
-   adev->powerplay.pp_funcs->display_configuration_change(
-   
adev->powerplay.pp_handle,
-   
>pm.pm_display_cfg);
-   mutex_unlock(>pm.mutex);
-   }
-
if (adev->powerplay.pp_funcs->dispatch_tasks) {
+   if (!amdgpu_device_has_dc_support(adev)) {
+   mutex_lock(>pm.mutex);
+   amdgpu_dpm_get_active_displays(adev);
+   adev->pm.pm_display_cfg.num_display = 
adev->pm.dpm.new_active_crtcs;
+   adev->pm.pm_display_cfg.vrefresh = 
amdgpu_dpm_get_vrefresh(adev);
+   adev->pm.pm_display_cfg.min_vblank_time = 
amdgpu_dpm_get_vblank_time(adev);
+   /* we have issues with mclk switching with refresh 
rates over 120 hz on the non-DC code. */
+   if (adev->pm.pm_display_cfg.vrefresh > 120)
+   adev->pm.pm_display_cfg.min_vblank_time = 0;
+   if 
(adev->powerplay.pp_funcs->display_configuration_change)
+   
adev->powerplay.pp_funcs->display_configuration_change(
+   
adev->powerplay.pp_handle,
+   
>pm.pm_display_cfg);
+   mutex_unlock(>pm.mutex);
+   }
amdgpu_dpm_dispatch_task(adev, 
AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
} else {
mutex_lock(>pm.mutex);
+   amdgpu_dpm_get_active_displays(adev);
/* update battery/ac status */
if (power_supply_is_system_supplied() > 0)
adev->pm.dpm.ac_power = true;
-- 
1.9.1

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[PATCH 13/17] drm/radeon: Remove custom dma_fence_ops->wait implementation

[Daniel Vetter]

It's a copy of dma_fence_default_wait, written slightly differently.

Signed-off-by: Daniel Vetter 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "David (ChunMing) Zhou" 
Cc: amd-gfx@lists.freedesktop.org
---
 drivers/gpu/drm/radeon/radeon_fence.c | 63 ---
 1 file changed, 63 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_fence.c 
b/drivers/gpu/drm/radeon/radeon_fence.c
index e86f2bd38410..32690a525bfc 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -1051,72 +1051,9 @@ static const char *radeon_fence_get_timeline_name(struct 
dma_fence *f)
}
 }
 
-static inline bool radeon_test_signaled(struct radeon_fence *fence)
-{
-   return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >base.flags);
-}
-
-struct radeon_wait_cb {
-   struct dma_fence_cb base;
-   struct task_struct *task;
-};
-
-static void
-radeon_fence_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
-{
-   struct radeon_wait_cb *wait =
-   container_of(cb, struct radeon_wait_cb, base);
-
-   wake_up_process(wait->task);
-}
-
-static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,
-signed long t)
-{
-   struct radeon_fence *fence = to_radeon_fence(f);
-   struct radeon_device *rdev = fence->rdev;
-   struct radeon_wait_cb cb;
-
-   cb.task = current;
-
-   if (dma_fence_add_callback(f, , radeon_fence_wait_cb))
-   return t;
-
-   while (t > 0) {
-   if (intr)
-   set_current_state(TASK_INTERRUPTIBLE);
-   else
-   set_current_state(TASK_UNINTERRUPTIBLE);
-
-   /*
-* radeon_test_signaled must be called after
-* set_current_state to prevent a race with wake_up_process
-*/
-   if (radeon_test_signaled(fence))
-   break;
-
-   if (rdev->needs_reset) {
-   t = -EDEADLK;
-   break;
-   }
-
-   t = schedule_timeout(t);
-
-   if (t > 0 && intr && signal_pending(current))
-   t = -ERESTARTSYS;
-   }
-
-   __set_current_state(TASK_RUNNING);
-   dma_fence_remove_callback(f, );
-
-   return t;
-}
-
 const struct dma_fence_ops radeon_fence_ops = {
.get_driver_name = radeon_fence_get_driver_name,
.get_timeline_name = radeon_fence_get_timeline_name,
.enable_signaling = radeon_fence_enable_signaling,
.signaled = radeon_fence_is_signaled,
-   .wait = radeon_fence_default_wait,
-   .release = NULL,
 };
-- 
2.17.0

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[PATCH] drm/amd/pp: Skip fan attributes if fan not present

[Rex Zhu]

With powerplay enabled, also need to skip fan attributes
if no fan present.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c  | 21 -
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c |  3 +++
 2 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d9802d9..2c82126 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1364,19 +1364,14 @@ static umode_t hwmon_attributes_visible(struct kobject 
*kobj,
struct amdgpu_device *adev = dev_get_drvdata(dev);
umode_t effective_mode = attr->mode;
 
-   /* handle non-powerplay limitations */
-   if (!adev->powerplay.pp_handle) {
-   /* Skip fan attributes if fan is not present */
-   if (adev->pm.no_fan &&
-   (attr == _dev_attr_pwm1.dev_attr.attr ||
-attr == _dev_attr_pwm1_enable.dev_attr.attr ||
-attr == _dev_attr_pwm1_max.dev_attr.attr ||
-attr == _dev_attr_pwm1_min.dev_attr.attr))
-   return 0;
-   /* requires powerplay */
-   if (attr == _dev_attr_fan1_input.dev_attr.attr)
-   return 0;
-   }
+
+   /* Skip fan attributes if fan is not present */
+   if (adev->pm.no_fan && (attr == _dev_attr_pwm1.dev_attr.attr ||
+   attr == _dev_attr_pwm1_enable.dev_attr.attr ||
+   attr == _dev_attr_pwm1_max.dev_attr.attr ||
+   attr == _dev_attr_pwm1_min.dev_attr.attr ||
+   attr == _dev_attr_fan1_input.dev_attr.attr))
+   return 0;
 
/* Skip limit attributes if DPM is not enabled */
if (!adev->pm.dpm_enabled &&
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index d1052b5..43f0ea8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -223,6 +223,9 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
if (ret)
goto err;
 
+   ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
+   hwmgr->thermal_controller.fanInfo.bNoFan;
+
ret = hwmgr->hwmgr_func->backend_init(hwmgr);
if (ret)
goto err1;
-- 
1.9.1

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