Re: [PATCH] drm/amdgpu/pp: switch the default dpm implementation for CI

[Zhu, Rex]

Reviewed-by: Rex Zhu



Best Regards

Rex



From: amd-gfx  on behalf of Alex Deucher 

Sent: Friday, June 1, 2018 1:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/pp: switch the default dpm implementation for CI

Switch hawaii and bonaire to use powerplay rather than the old
dpm implementation.  Powerplay supports more features and is
better maintained.  Ultimately, we can drop the older dpm
implementation like we did for other older asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/cik.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 8ff4c60d1b59..702e257a483f 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2003,9 +2003,9 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
 amdgpu_device_ip_block_add(adev, _ih_ip_block);
 if (amdgpu_dpm == -1)
-   amdgpu_device_ip_block_add(adev, _smu_ip_block);
-   else
 amdgpu_device_ip_block_add(adev, _smu_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, _smu_ip_block);
 if (adev->enable_virtual_display)
 amdgpu_device_ip_block_add(adev, 
_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
@@ -2024,9 +2024,9 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
 amdgpu_device_ip_block_add(adev, _ih_ip_block);
 if (amdgpu_dpm == -1)
-   amdgpu_device_ip_block_add(adev, _smu_ip_block);
-   else
 amdgpu_device_ip_block_add(adev, _smu_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, _smu_ip_block);
 if (adev->enable_virtual_display)
 amdgpu_device_ip_block_add(adev, 
_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
--
2.13.6

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Re: [PATCH 1/3] Revert "drm/amdgpu: Add an ATPX quirk for hybrid laptop"

[Huang Rui]

On Thu, May 24, 2018 at 02:46:34PM -0500, Alex Deucher wrote:
> This reverts commit 13b40935cf64f59b93cf1c716a2033488e5a228c.
> 
> This was a workaround for a bug in the HDA driver that prevented
> the HDA audio chip from going into runtime pm which prevented
> the GPU from going into runtime pm.
> 
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106597
> Signed-off-by: Alex Deucher 

For series are,
Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> index 1bcb2b247335..daa06e7c5bb7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> @@ -569,7 +569,6 @@ static const struct amdgpu_px_quirk 
> amdgpu_px_quirk_list[] = {
>   { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
>   { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
>   { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
> - { 0x1002, 0x67DF, 0x1028, 0x0774, AMDGPU_PX_QUIRK_FORCE_ATPX },
>   { 0, 0, 0, 0, 0 },
>  };
>  
> -- 
> 2.13.6
> 
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Re: [PATCH] drm/amdgpu/pp: switch the default dpm implementation for CI

[Huang Rui]

On Thu, May 31, 2018 at 12:48:19PM -0500, Alex Deucher wrote:
> Switch hawaii and bonaire to use powerplay rather than the old
> dpm implementation.  Powerplay supports more features and is
> better maintained.  Ultimately, we can drop the older dpm
> implementation like we did for other older asics.
> 
> Signed-off-by: Alex Deucher 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/cik.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c 
> b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 8ff4c60d1b59..702e257a483f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -2003,9 +2003,9 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
>   amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
>   amdgpu_device_ip_block_add(adev, _ih_ip_block);
>   if (amdgpu_dpm == -1)
> - amdgpu_device_ip_block_add(adev, _smu_ip_block);
> - else
>   amdgpu_device_ip_block_add(adev, _smu_ip_block);
> + else
> + amdgpu_device_ip_block_add(adev, _smu_ip_block);
>   if (adev->enable_virtual_display)
>   amdgpu_device_ip_block_add(adev, _virtual_ip_block);
>  #if defined(CONFIG_DRM_AMD_DC)
> @@ -2024,9 +2024,9 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
>   amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
>   amdgpu_device_ip_block_add(adev, _ih_ip_block);
>   if (amdgpu_dpm == -1)
> - amdgpu_device_ip_block_add(adev, _smu_ip_block);
> - else
>   amdgpu_device_ip_block_add(adev, _smu_ip_block);
> + else
> + amdgpu_device_ip_block_add(adev, _smu_ip_block);
>   if (adev->enable_virtual_display)
>   amdgpu_device_ip_block_add(adev, _virtual_ip_block);
>  #if defined(CONFIG_DRM_AMD_DC)
> -- 
> 2.13.6
> 
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Re: [PATCH][next] drm/amdgpu/df: fix potential array out-of-bounds read

[Alex Deucher]

On Wed, May 30, 2018 at 12:41 PM, Colin King  wrote:
> From: Colin Ian King 
>
> The comparison with the number of elements in array df_v3_7_channel_number
> is off-by-one and can produce an array out-of-bounds read if
> fb_channel_number is equal to the number of elements of the array. Fix
> this by changing the comparison to >= instead of >.
>
> Detected by CoverityScan, CID#1469489 ("Out-of-bounds read")
>
> Fixes: 13b581502d51 ("drm/amdgpu/df: implement df v3_6 callback functions 
> (v2)")
> Signed-off-by: Colin Ian King 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c 
> b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> index 60608b3df881..d5ebe566809b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> @@ -64,7 +64,7 @@ static u32 df_v3_6_get_hbm_channel_number(struct 
> amdgpu_device *adev)
> int fb_channel_number;
>
> fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
> -   if (fb_channel_number > ARRAY_SIZE(df_v3_6_channel_number))
> +   if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
> fb_channel_number = 0;
>
> return df_v3_6_channel_number[fb_channel_number];
> --
> 2.17.0
>
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[pull] amdgpu and scheduler drm-next-4.18

[Alex Deucher]

Hi Dave,

Fixes for 4.18. Highlights:
- Improve DC/powerplay interface to allow additional power savings on vega
- DP 1.4 compliance fixes
- Various vega20 fixes
- Fix for DC scale ratios
- Per vm bo fixes
- Scheduler dependency corner case fix
- Misc bug fixes

The following changes since commit dd41fb8547c2422f3a3a75e7226525e8bba9381c:

  Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux 
into drm-next (2018-05-25 10:28:33 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.18

for you to fetch changes up to 7ba01f9e12bb3f088f617cf69b589ea37bd5d6ed:

  drm/amdgpu: Fix NULL pointer when load kfd driver with PP block is disabled 
(2018-05-31 14:08:54 -0500)


Alex Deucher (1):
  drm/amdgpu/display: check if ppfuncs exists before using it

Charlene Liu (1):
  drm/amd/display: add register offset != 0 check.

Chunming Zhou (1):
  drm/amdgpu: gds bo must not be per-vm-bo

Deepak Sharma (2):
  drm/amdgpu: Use GTT for dumb buffer if sg display enabled (v2)
  drm/amdgpu: Add helper function to get buffer domain

Dmytro Laktyushkin (1):
  drm/amd/display: fix dscl_manual_ratio_init

Emily Deng (1):
  drm/amdgpu: To get gds, gws and oa from adev->gds (v2)

Eric Bernstein (2):
  drm/amd/display: DP component depth 16 bpc
  drm/amd/display: Set TMZ and DCC for secondary surface

Evan Quan (3):
  drm/amdgpu: correct SMU11 SYSPLL0 clock id values
  drm/amd/powerplay: bug fixs for getsmuclockinfo
  drm/amdgpu: typo fix for vega20 cg flags

Feifei Xu (1):
  drm/gfx9: Update gc goldensetting for vega20.

Harry Wentland (2):
  drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency
  drm/amd/display: Fix wrong latency assignment for VEGA clock levels

Leo (Sunpeng) Li (2):
  drm/amd/display: Destroy connector state on reset
  drm/amd/display: Fix BUG_ON during CRTC atomic check update

Leo Liu (1):
  drm/amdgpu: remove unnecessary scheduler entity for VCN

Mikita Lipski (5):
  drm/amd/pp: Add cases for getting phys and disp clks for SMU10
  drm/amd/display: Do not limit color depth to 8bpc
  drm/amd/display: Release fake sink
  drm/amd/display: Do not program interrupt status on disabled crtc
  drm/amd/pp: Connect display_clock_voltage_request to a function pointer

Nayan Deshmukh (1):
  drm/scheduler: fix a corner case in dependency optimization

Nikola Cornij (2):
  drm/amd/display: Read DPCD link caps up to and including DP_ADAPTER_CAP
  drm/amd/display: Read DP_SINK_COUNT_ESI range on HPD for DP 1.4

Rex Zhu (1):
  drm/amd/pp: Allow underclocking when od table is empty in vbios

Roman Li (2):
  drm/amd/display: replace msleep with udelay in fbc path
  drm/amd/display: check if audio clk enable is applicable

Shaoyun Liu (1):
  drm/amdgpu: Fix NULL pointer when load kfd driver with PP block is 
disabled

kbuild test robot (1):
  drm/amdgpu: vcn_v1_0_is_idle() can be static

 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 18 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 38 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 15 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 17 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c| 51 
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|  2 -
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c |  1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |  4 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 56 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c  |  3 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 45 +-
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c |  5 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 37 ++--
 .../drm/amd/display/dc/dce/dce_stream_encoder.c|  6 +-
 .../drm/amd/display/dc/dce110/dce110_compressor.c  |  8 +--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |  3 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  6 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |  8 +--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  | 14 +++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h  |  8 +++
 .../amd/display/dc/dcn10/dcn10_stream_encoder.c|  4 ++
 drivers/gpu/drm/amd/display/include/fixed31_32.h   |  2 +
 drivers/gpu/drm/amd/include/atomfirmware.h | 12 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c |  4 +-
 .../amd/powerplay/hwmgr/process_pptables_v1_0.c|  6 --
 .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  6 --
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 70 --
 

[pull] amdgpu drm-fixes-4.17

[Alex Deucher]

Hi Dave,

Two last minute DC fixes for 4.17.  A fix for underscan on fiji and
a fix for gamma settings getting after dpms.

The following changes since commit 0e333751cff1dd7383be15372960a1be6e2b4e47:

  Merge tag 'drm-misc-fixes-2018-05-30' of 
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2018-05-31 08:35:47 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.17

for you to fetch changes up to bc13f2f88eae63af943ab967cb14bb602f8f2eeb:

  drm/amd/display: Update color props when modeset is required (2018-05-31 
13:08:26 -0500)


David Francis (1):
  drm/amd/display: Make atomic-check validate underscan changes

Leo (Sunpeng) Li (1):
  drm/amd/display: Update color props when modeset is required

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ---
 1 file changed, 22 insertions(+), 9 deletions(-)
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Re: [PATCH] drm/amd/display: avoid sleeping in atomic context while creating new context or state

[Christian König]

Am 30.05.2018 um 18:03 schrieb Harry Wentland:

On 2018-05-30 06:17 AM, Shirish S wrote:

This patch fixes the warning messages that are caused due to calling
sleep in atomic context as below:

BUG: sleeping function called from invalid context at mm/slab.h:419
in_atomic(): 1, irqs_disabled(): 1, pid: 5, name: kworker/u4:0
CPU: 1 PID: 5 Comm: kworker/u4:0 Tainted: GW   4.14.35 #941
Workqueue: events_unbound commit_work
Call Trace:
  dump_stack+0x4d/0x63
  ___might_sleep+0x11f/0x12e
  kmem_cache_alloc_trace+0x41/0xea
  dc_create_state+0x1f/0x30
  dc_commit_updates_for_stream+0x73/0x4cf
  ? amdgpu_get_crtc_scanoutpos+0x82/0x16b
  amdgpu_dm_do_flip+0x239/0x298
  amdgpu_dm_commit_planes.isra.23+0x379/0x54b
  ? dc_commit_state+0x3da/0x404
  amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
  ? wait_for_common+0x5b/0x69
  commit_tail+0x42/0x64
  process_one_work+0x1b0/0x314
  worker_thread+0x1cb/0x2c1
  ? create_worker+0x1da/0x1da
  kthread+0x156/0x15e
  ? kthread_flush_work+0xea/0xea
  ret_from_fork+0x22/0x40

Signed-off-by: Shirish S 
---
  drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 33149ed..d62206f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -588,7 +588,7 @@ static void disable_dangling_plane(struct dc *dc, struct 
dc_state *context)
  
  struct dc *dc_create(const struct dc_init_data *init_params)

   {
-   struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
+   struct dc *dc = kzalloc(sizeof(*dc), GFP_ATOMIC);

Are you sure this one can be called in atomic_context?

If so then everything in consstruct() would also need GFP_ATOMIC.


Well the backtrace is quite obvious, but I agree that change still looks 
fishy to me as well.


Using GFP_ATOMIC should only be a last resort when nothing else helps, 
but here it looks more like we misuse a spinlock where a mutex or 
semaphore would be more appropriate.


Where exactly becomes the context atomic in the call trace?

Christian.



Harry


unsigned int full_pipe_count;
  
  	if (NULL == dc)

@@ -937,7 +937,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
  struct dc_state *dc_create_state(void)
  {
struct dc_state *context = kzalloc(sizeof(struct dc_state),
-  GFP_KERNEL);
+  GFP_ATOMIC);
  
  	if (!context)

return NULL;


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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Leo Liu]

On 05/31/2018 01:04 PM, Michel Dänzer wrote:

On 2018-05-31 06:49 PM, Leo Liu wrote:

On 05/31/2018 12:47 PM, Michel Dänzer wrote:

On 2018-05-31 06:39 PM, Leo Liu wrote:

On 05/31/2018 12:30 PM, Michel Dänzer wrote:

On 2018-05-30 08:42 PM, Leo Liu wrote:

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 12f0d18c6ee8..343ff115cff1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct
amdgpu_cs_parser *p,
    return 0;
    }
    +/**
+ * DOC:  amdgpu_cs_ioctl

DOC comments shouldn't be used for functions, see
Documentation/output/doc-guide/kernel-doc.html#function-documentation


This doc is not for the functions, it's like something in commit message
about the details of in/out data, and what is the functionality for this
ioctl.

Data structures should be documented in comments directly above their
definitions, per
Documentation/output/doc-guide/kernel-doc.html#structure-union-and-enumeration-documentation

. What an ioctl does should be described in the function documentation
comment above its implementation, as described above.

Then what do you think the kernel doc for ioctl should do?

The data structure should be documented in a comment above its
definition, and what the ioctl does should be documented in a comment
above the function implementing it. The source files need to be hooked
up to the amdgpu.rst file.

Does that answer your question?
Sort of. It tells me what should not be in the kernel DOC. I will put 
those details about data and functionalities where they should be.

And focus on what the ioctl is used for for the kernel DOC section.

Thanks Michel, the information is helpful.

Leo






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Re: [PATCH 2/2] drm/amdgpu/display: enable CONFIG_DRM_AMD_DC_DCN1_0 by default

[Harry Wentland]

On 2018-05-31 10:33 AM, Alex Deucher wrote:
> It's required for displays on Raven.  The DCN bandwidth calcs use
> floating point, but DCN is APU only and it already depends on
> X86.
> 
> Signed-off-by: Alex Deucher 

Series is
Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/Kconfig 
> b/drivers/gpu/drm/amd/display/Kconfig
> index 9d56889279b3..4c35625eb2c7 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -12,6 +12,7 @@ config DRM_AMD_DC
>  config DRM_AMD_DC_DCN1_0
>   bool "DCN 1.0 Raven family"
>   depends on DRM_AMD_DC && X86
> + default y
>   help
> Choose this option if you want to have
> RV family for display engine
> 
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Re: [PATCH 2/2] drm/amdgpu/display: enable CONFIG_DRM_AMD_DC_DCN1_0 by default

[Harry Wentland]

On 2018-05-31 12:08 PM, Michel Dänzer wrote:
> On 2018-05-31 04:33 PM, Alex Deucher wrote:
>> It's required for displays on Raven.  The DCN bandwidth calcs use
>> floating point, but DCN is APU only and it already depends on
>> X86.
>>
>> Signed-off-by: Alex Deucher 
>> ---
>>  drivers/gpu/drm/amd/display/Kconfig | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Kconfig 
>> b/drivers/gpu/drm/amd/display/Kconfig
>> index 9d56889279b3..4c35625eb2c7 100644
>> --- a/drivers/gpu/drm/amd/display/Kconfig
>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>> @@ -12,6 +12,7 @@ config DRM_AMD_DC
>>  config DRM_AMD_DC_DCN1_0
>>  bool "DCN 1.0 Raven family"
>>  depends on DRM_AMD_DC && X86
>> +default y
>>  help
>>Choose this option if you want to have
>>RV family for display engine
>>
> 
> Can CONFIG_DRM_AMD_DC_DCN1_0 just be replaced by (something like)
> CONFIG_X86 altogether?
> 
> 


Good idea.

Will have to check with some of the DC guys but it seems like a better option 
than the DCN1 one.

Harry
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[PATCH v2] drm/amd/display: Make atomic-check validate underscan changes

[sunpeng.li]

From: David Francis 

When the underscan state was changed, atomic-check was triggering a
validation but passing the old underscan values.  This change adds a
somewhat hacky check in dm_update_crtcs_state that will update the
stream if old and newunderscan values are different.
This was causing 4k on Fiji to allow underscan when it wasn't permitted.

Signed-off-by: David Francis 
Reviewed-by: David Francis 
Acked-by: Harry Wentland 
Cc: sta...@vger.kernel.org
---

v2: Make it apply cleanly on drm-fixes-4.17.

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ---
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ad1ad33..1a7e96e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4555,8 +4555,8 @@ static int dm_update_crtcs_state(struct dc *dc,
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
struct amdgpu_crtc *acrtc = NULL;
struct amdgpu_dm_connector *aconnector = NULL;
-   struct drm_connector_state *new_con_state = NULL;
-   struct dm_connector_state *dm_conn_state = NULL;
+   struct drm_connector_state *drm_new_conn_state = NULL, 
*drm_old_conn_state = NULL;
+   struct dm_connector_state *dm_new_conn_state = NULL, 
*dm_old_conn_state = NULL;
struct drm_plane_state *new_plane_state = NULL;
 
new_stream = NULL;
@@ -4577,19 +4577,23 @@ static int dm_update_crtcs_state(struct dc *dc,
/* TODO This hack should go away */
if (aconnector && enable) {
// Make sure fake sink is created in plug-in scenario
-   new_con_state = drm_atomic_get_connector_state(state,
+   drm_new_conn_state = 
drm_atomic_get_new_connector_state(state,

>base);
+   drm_old_conn_state = 
drm_atomic_get_old_connector_state(state,
+   
>base);
 
-   if (IS_ERR(new_con_state)) {
-   ret = PTR_ERR_OR_ZERO(new_con_state);
+
+   if (IS_ERR(drm_new_conn_state)) {
+   ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
break;
}
 
-   dm_conn_state = to_dm_connector_state(new_con_state);
+   dm_new_conn_state = 
to_dm_connector_state(drm_new_conn_state);
+   dm_old_conn_state = 
to_dm_connector_state(drm_old_conn_state);
 
new_stream = create_stream_for_sink(aconnector,
 
_crtc_state->mode,
-   dm_conn_state);
+   dm_new_conn_state);
 
/*
 * we can have no stream on ACTION_SET if a display
@@ -4708,6 +4712,11 @@ static int dm_update_crtcs_state(struct dc *dc,
 */
BUG_ON(dm_new_crtc_state->stream == NULL);
 
+   /* Scaling or underscan settings */
+   if (is_scaling_state_different(dm_old_conn_state, 
dm_new_conn_state))
+   update_stream_scaling_settings(
+   _crtc_state->mode, dm_new_conn_state, 
dm_new_crtc_state->stream);
+
/* Color managment settings */
if (dm_new_crtc_state->base.color_mgmt_changed) {
ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
-- 
2.7.4

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[PATCH] drm/amdgpu/pp: switch the default dpm implementation for CI

[Alex Deucher]

Switch hawaii and bonaire to use powerplay rather than the old
dpm implementation.  Powerplay supports more features and is
better maintained.  Ultimately, we can drop the older dpm
implementation like we did for other older asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/cik.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 8ff4c60d1b59..702e257a483f 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2003,9 +2003,9 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (amdgpu_dpm == -1)
-   amdgpu_device_ip_block_add(adev, _smu_ip_block);
-   else
amdgpu_device_ip_block_add(adev, _smu_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
@@ -2024,9 +2024,9 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (amdgpu_dpm == -1)
-   amdgpu_device_ip_block_add(adev, _smu_ip_block);
-   else
amdgpu_device_ip_block_add(adev, _smu_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
-- 
2.13.6

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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Michel Dänzer]

On 2018-05-31 06:49 PM, Leo Liu wrote:
> On 05/31/2018 12:47 PM, Michel Dänzer wrote:
>> On 2018-05-31 06:39 PM, Leo Liu wrote:
>>> On 05/31/2018 12:30 PM, Michel Dänzer wrote:
 On 2018-05-30 08:42 PM, Leo Liu wrote:
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 12f0d18c6ee8..343ff115cff1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct
> amdgpu_cs_parser *p,
>    return 0;
>    }
>    +/**
> + * DOC:  amdgpu_cs_ioctl
 DOC comments shouldn't be used for functions, see
 Documentation/output/doc-guide/kernel-doc.html#function-documentation

>>> This doc is not for the functions, it's like something in commit message
>>> about the details of in/out data, and what is the functionality for this
>>> ioctl.
>> Data structures should be documented in comments directly above their
>> definitions, per
>> Documentation/output/doc-guide/kernel-doc.html#structure-union-and-enumeration-documentation
>>
>> . What an ioctl does should be described in the function documentation
>> comment above its implementation, as described above.
> Then what do you think the kernel doc for ioctl should do?

The data structure should be documented in a comment above its
definition, and what the ioctl does should be documented in a comment
above the function implementing it. The source files need to be hooked
up to the amdgpu.rst file.

Does that answer your question?


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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Leo Liu]

On 05/31/2018 12:47 PM, Michel Dänzer wrote:

On 2018-05-31 06:39 PM, Leo Liu wrote:

On 05/31/2018 12:30 PM, Michel Dänzer wrote:

On 2018-05-30 08:42 PM, Leo Liu wrote:

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 12f0d18c6ee8..343ff115cff1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct
amdgpu_cs_parser *p,
   return 0;
   }
   +/**
+ * DOC:  amdgpu_cs_ioctl

DOC comments shouldn't be used for functions, see
Documentation/output/doc-guide/kernel-doc.html#function-documentation


This doc is not for the functions, it's like something in commit message
about the details of in/out data, and what is the functionality for this
ioctl.

Data structures should be documented in comments directly above their
definitions, per
Documentation/output/doc-guide/kernel-doc.html#structure-union-and-enumeration-documentation
. What an ioctl does should be described in the function documentation
comment above its implementation, as described above.

Then what do you think the kernel doc for ioctl should do?

Leo






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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Leo Liu]

On 05/31/2018 12:39 PM, Leo Liu wrote:



On 05/31/2018 12:30 PM, Michel Dänzer wrote:

On 2018-05-30 08:42 PM, Leo Liu wrote:

There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.

Signed-off-by: Leo Liu 

This isn't enough to actually make this part of the generated
documentation. It needs to be hooked up to a *.rst file for that.

I'm adding an amdgpu.rst file in
https://patchwork.freedesktop.org/series/44035/ , where you could hook
it up accordingly.

Please check that generating the documentation (e.g. with make htmldocs)
doesn't produce any warnings about amdgpu_cs.c, and that the result
looks good in Documentation/output/gpu/amdgpu.html . The documentation
format itself is documented in 
Documentation/output/doc-guide/index.html .



I will take a look this.

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

index 12f0d18c6ee8..343ff115cff1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct 
amdgpu_cs_parser *p,

  return 0;
  }
  +/**
+ * DOC:  amdgpu_cs_ioctl

DOC comments shouldn't be used for functions, see
Documentation/output/doc-guide/kernel-doc.html#function-documentation

This doc is not for the functions, it's like something in commit 
message about the details of in/out data, and what is the 
functionality for this ioctl.



@@ -1524,6 +1630,42 @@ static int amdgpu_cs_wait_any_fence(struct 
amdgpu_device *adev,

  return r;
  }
  +/**
+ * DOC:  amdgpu_cs_wait_fences_ioctl
+ *
+ * This ioctl checks either all fences or any fence from multiple 
fences
+ * to be signaled or waits to be signaled till timeout. So it's 
used to

+ * check and wait multiple CS to be completed.
+ *
+ * In data structure:
+ *
+ * __u64 fences
+ * Point to the multiple fences
+ *
+ * __u32 fence_count
+ * number of fences
+ *
+ * __u32 wait_all
+ * ways to wait either wait_all or wait_any
+ *
+ * __u64 timeout_ns
+ * Absolute timeout to wait
+ *
+ * The function will extract user space fences based on pointer and 
counts,
+ * then mapping them amdgpu fences and check if they are signaled 
or wait

+ * to timeout.
+ *
+ * Out data:
+ *
+ *__u32 status
+ * 0 CS completed
+ * 1 CS busy
+ *
+ *__u32 first_signaled;
+ * First signaled fence index
+ *
+ */
+
  /**
   * amdgpu_cs_wait_fences_ioctl - wait for multiple command 
submissions to finish

   *

Any reason for not adding the above to the existing function
documentation comment here?
The existing is the function document, I am adding kernel doc for this 
ioctl.


Leo

Yes. It's used by close source Vulkan, where it might be lack of BO 
fence dependencies implementations like we do in Mesa.


Leo






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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Michel Dänzer]

On 2018-05-31 06:39 PM, Leo Liu wrote:
> On 05/31/2018 12:30 PM, Michel Dänzer wrote:
>> On 2018-05-30 08:42 PM, Leo Liu wrote:
> 
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>>> index 12f0d18c6ee8..343ff115cff1 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>>> @@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct
>>> amdgpu_cs_parser *p,
>>>   return 0;
>>>   }
>>>   +/**
>>> + * DOC:  amdgpu_cs_ioctl
>> DOC comments shouldn't be used for functions, see
>> Documentation/output/doc-guide/kernel-doc.html#function-documentation
>>
> This doc is not for the functions, it's like something in commit message
> about the details of in/out data, and what is the functionality for this
> ioctl.

Data structures should be documented in comments directly above their
definitions, per
Documentation/output/doc-guide/kernel-doc.html#structure-union-and-enumeration-documentation
. What an ioctl does should be described in the function documentation
comment above its implementation, as described above.


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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Leo Liu]

On 05/31/2018 12:30 PM, Michel Dänzer wrote:

On 2018-05-30 08:42 PM, Leo Liu wrote:

There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.

Signed-off-by: Leo Liu 

This isn't enough to actually make this part of the generated
documentation. It needs to be hooked up to a *.rst file for that.

I'm adding an amdgpu.rst file in
https://patchwork.freedesktop.org/series/44035/ , where you could hook
it up accordingly.

Please check that generating the documentation (e.g. with make htmldocs)
doesn't produce any warnings about amdgpu_cs.c, and that the result
looks good in Documentation/output/gpu/amdgpu.html . The documentation
format itself is documented in Documentation/output/doc-guide/index.html .


I will take a look this.


diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 12f0d18c6ee8..343ff115cff1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
return 0;
  }
  
+/**

+ * DOC:  amdgpu_cs_ioctl

DOC comments shouldn't be used for functions, see
Documentation/output/doc-guide/kernel-doc.html#function-documentation

This doc is not for the functions, it's like something in commit message 
about the details of in/out data, and what is the functionality for this 
ioctl.




@@ -1524,6 +1630,42 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device 
*adev,
return r;
  }
  
+/**

+ * DOC:  amdgpu_cs_wait_fences_ioctl
+ *
+ * This ioctl checks either all fences or any fence from multiple fences
+ * to be signaled or waits to be signaled till timeout. So it's used to
+ * check and wait multiple CS to be completed.
+ *
+ * In data structure:
+ *
+ * __u64 fences
+ * Point to the multiple fences
+ *
+ * __u32 fence_count
+ * number of fences
+ *
+ * __u32 wait_all
+ * ways to wait either wait_all or wait_any
+ *
+ * __u64 timeout_ns
+ * Absolute timeout to wait
+ *
+ * The function will extract user space fences based on pointer and counts,
+ * then mapping them amdgpu fences and check if they are signaled or wait
+ * to timeout.
+ *
+ * Out data:
+ *
+ *__u32 status
+ * 0 CS completed
+ * 1 CS busy
+ *
+ *__u32 first_signaled;
+ * First signaled fence index
+ *
+ */
+
  /**
   * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to 
finish
   *

Any reason for not adding the above to the existing function
documentation comment here?
Yes. It's used by close source Vulkan, where it might be lack of BO 
fence dependencies implementations like we do in Mesa.


Leo






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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Michel Dänzer]

On 2018-05-30 08:42 PM, Leo Liu wrote:
> There are four ioctls in this files, and DOC gives details of
> data structures for each of ioctls, and their functionalities.
> 
> Signed-off-by: Leo Liu 

This isn't enough to actually make this part of the generated
documentation. It needs to be hooked up to a *.rst file for that.

I'm adding an amdgpu.rst file in
https://patchwork.freedesktop.org/series/44035/ , where you could hook
it up accordingly.

Please check that generating the documentation (e.g. with make htmldocs)
doesn't produce any warnings about amdgpu_cs.c, and that the result
looks good in Documentation/output/gpu/amdgpu.html . The documentation
format itself is documented in Documentation/output/doc-guide/index.html .


> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 12f0d18c6ee8..343ff115cff1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
>   return 0;
>  }
>  
> +/**
> + * DOC:  amdgpu_cs_ioctl

DOC comments shouldn't be used for functions, see
Documentation/output/doc-guide/kernel-doc.html#function-documentation


> @@ -1524,6 +1630,42 @@ static int amdgpu_cs_wait_any_fence(struct 
> amdgpu_device *adev,
>   return r;
>  }
>  
> +/**
> + * DOC:  amdgpu_cs_wait_fences_ioctl
> + *
> + * This ioctl checks either all fences or any fence from multiple fences
> + * to be signaled or waits to be signaled till timeout. So it's used to
> + * check and wait multiple CS to be completed.
> + *
> + * In data structure:
> + *
> + * __u64 fences
> + * Point to the multiple fences
> + *
> + * __u32 fence_count
> + * number of fences
> + *
> + * __u32 wait_all
> + * ways to wait either wait_all or wait_any
> + *
> + * __u64 timeout_ns
> + * Absolute timeout to wait
> + *
> + * The function will extract user space fences based on pointer and counts,
> + * then mapping them amdgpu fences and check if they are signaled or wait
> + * to timeout.
> + *
> + * Out data:
> + *
> + *__u32 status
> + * 0 CS completed
> + * 1 CS busy
> + *
> + *__u32 first_signaled;
> + * First signaled fence index
> + *
> + */
> +
>  /**
>   * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to 
> finish
>   *

Any reason for not adding the above to the existing function
documentation comment here?


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[PATCH 2/3] drm/doc: Add initial amdgpu driver documentation

[Michel Dänzer]

From: Michel Dänzer 

Signed-off-by: Michel Dänzer 
---
 Documentation/gpu/amdgpu.rst  | 6 ++
 Documentation/gpu/drivers.rst | 1 +
 2 files changed, 7 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu.rst

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
new file mode 100644
index ..41a14e4aa4ac
--- /dev/null
+++ b/Documentation/gpu/amdgpu.rst
@@ -0,0 +1,6 @@
+=
+ drm/amdgpu AMDgpu driver
+=
+
+The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
+Next (GCN) architecture.
diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
index e8c84419a2a1..604b6d6975af 100644
--- a/Documentation/gpu/drivers.rst
+++ b/Documentation/gpu/drivers.rst
@@ -4,6 +4,7 @@ GPU Driver Documentation
 
 .. toctree::
 
+   amdgpu
i915
meson
pl111
-- 
2.17.0

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[PATCH 3/3] drm/amdgpu: Add documentation for PRIME related code

[Michel Dänzer]

From: Michel Dänzer 

Signed-off-by: Michel Dänzer 
---
 Documentation/gpu/amdgpu.rst  |  14 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 119 ++
 2 files changed, 133 insertions(+)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 41a14e4aa4ac..f557866f6788 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -4,3 +4,17 @@
 
 The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
 Next (GCN) architecture.
+
+Core Driver Infrastructure
+==
+
+This section covers core driver infrastructure.
+
+PRIME Buffer Sharing
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+   :doc: PRIME Buffer Sharing
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+   :internal:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 4683626b065f..d1f05489595b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -23,6 +23,14 @@
  *
  * Authors: Alex Deucher
  */
+
+/**
+ * DOC: PRIME Buffer Sharing
+ *
+ * The following callback implementations are used for :ref:`sharing GEM buffer
+ * objects between different devices via PRIME `.
+ */
+
 #include 
 
 #include "amdgpu.h"
@@ -32,6 +40,14 @@
 
 static const struct dma_buf_ops amdgpu_dmabuf_ops;
 
+/**
+ * amdgpu_gem_prime_get_sg_table - _driver.gem_prime_get_sg_table
+ * implementation
+ * @obj: GEM buffer object
+ *
+ * Returns:
+ * A scatter/gather table for the pinned pages of the buffer object's memory.
+ */
 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
 {
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
@@ -40,6 +56,15 @@ struct sg_table *amdgpu_gem_prime_get_sg_table(struct 
drm_gem_object *obj)
return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
 }
 
+/**
+ * amdgpu_gem_prime_vmap - _buf_ops.vmap implementation
+ * @obj: GEM buffer object
+ *
+ * Sets up an in-kernel virtual mapping of the buffer object's memory.
+ *
+ * Returns:
+ * The virtual address of the mapping or an error pointer.
+ */
 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
 {
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
@@ -53,6 +78,13 @@ void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
return bo->dma_buf_vmap.virtual;
 }
 
+/**
+ * amdgpu_gem_prime_vunmap - _buf_ops.vunmap implementation
+ * @obj: GEM buffer object
+ * @vaddr: virtual address (unused)
+ *
+ * Tears down the in-kernel virtual mapping of the buffer object's memory.
+ */
 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
 {
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
@@ -60,6 +92,17 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, 
void *vaddr)
ttm_bo_kunmap(>dma_buf_vmap);
 }
 
+/**
+ * amdgpu_gem_prime_mmap - _driver.gem_prime_mmap implementation
+ * @obj: GEM buffer object
+ * @vma: virtual memory area
+ *
+ * Sets up a userspace mapping of the buffer object's memory in the given
+ * virtual memory area.
+ *
+ * Returns:
+ * 0 on success or negative error code.
+ */
 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct 
*vma)
 {
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
@@ -94,6 +137,19 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, 
struct vm_area_struct *vma
return ret;
 }
 
+/**
+ * amdgpu_gem_prime_import_sg_table - _driver.gem_prime_import_sg_table
+ * implementation
+ * @dev: DRM device
+ * @attach: DMA-buf attachment
+ * @sg: Scatter/gather table
+ *
+ * Import shared DMA buffer memory exported by another device.
+ *
+ * Returns:
+ * A new GEM buffer object of the given DRM device, representing the memory
+ * described by the given DMA-buf attachment and scatter/gather table.
+ */
 struct drm_gem_object *
 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
 struct dma_buf_attachment *attach,
@@ -132,6 +188,19 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
return ERR_PTR(ret);
 }
 
+/**
+ * amdgpu_gem_map_attach - _buf_ops.attach implementation
+ * @dma_buf: shared DMA buffer
+ * @target_dev: target device
+ * @attach: DMA-buf attachment
+ *
+ * Makes sure that the shared DMA buffer can be accessed by the target device.
+ * For now, simply pins it to the GTT domain, where it should be accessible by
+ * all DMA devices.
+ *
+ * Returns:
+ * 0 on success or negative error code.
+ */
 static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
 struct device *target_dev,
 struct dma_buf_attachment *attach)
@@ -181,6 +250,14 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
return r;
 }
 
+/**
+ * amdgpu_gem_map_detach - _buf_ops.detach implementation
+ * @dma_buf: shared DMA buffer
+ * @attach: DMA-buf attachment
+ *
+ * This is called 

[PATCH 1/3] drm/doc: Add a label for the PRIME Buffer Sharing chapter

[Michel Dänzer]

From: Michel Dänzer 

So that it can be referenced from e.g. DOC comments.

Signed-off-by: Michel Dänzer 
---
 Documentation/gpu/drm-mm.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index 96ebcc2a7b41..21b6b72a9ba8 100644
--- a/Documentation/gpu/drm-mm.rst
+++ b/Documentation/gpu/drm-mm.rst
@@ -395,6 +395,8 @@ VMA Offset Manager
 .. kernel-doc:: drivers/gpu/drm/drm_vma_manager.c
:export:
 
+.. _prime_buffer_sharing:
+
 PRIME Buffer Sharing
 
 
-- 
2.17.0

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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Leo Liu]

On 05/31/2018 11:43 AM, Alex Deucher wrote:

On Wed, May 30, 2018 at 2:42 PM, Leo Liu  wrote:

There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.

Signed-off-by: Leo Liu 

A few comments below about readability.  With those fixed:
Reviewed-by: Alex Deucher 


Thanks for the reviews, I will update it accordingly.

Leo





---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 142 +
  1 file changed, 142 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 12f0d18c6ee8..343ff115cff1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 return 0;
  }

+/**
+ * DOC:  amdgpu_cs_ioctl
+ *
+ * This ioctl processes user space command submission chunks,

Maybe give an overview of why we use the ioctl.  Something like:
The CS (Command Submission) ioctl is used to submit command buffers to
the kernel for scheduling on hw queues.  The chunk interface gives us
the flexibility to add new features to the ioctl by simply adding a
new chunk type.


+ * return a fence sequence number associated to a amdgpu fence.
+ *
+ * In data structure:
+ *
+ * __u32 ctx_id:
+ * Integer ID, created via DRM_AMDGPU_CTX ioctl call when user space
+ * command submission context created. It will be used as ID for later
+ * command submission context.

Required for all command submissions.  The kernel uses this to track
dependencies and guilt for command submissions that lead to an engine
lock up.


+ *
+ * __u32 bo_list_handle:
+ * Handle of resources list associated with this CS, created via
+ * DRM_AMDGPU_BO_LIST ioctl call before command submission, and
+ * the BOs in the list will be validated.

to make sure they are resident when the command buffer executes.


+ *
+ * __u32 num_chunks:
+ * Number of chunks, their types include:
+ * AMDGPU_CHUNK_ID_IB
+ * The data will be filled into IB buffer, and mappped to a HW ring.
+ *

Expand this a bit.  E.g.,
An IB (Indirect Buffer) is a stand alone command buffer that can be
scheduled fetching for execution on a hw queue.



+ * AMDGPU_CHUNK_ID_FENCE
+ * The data will be used to find user fence BO and its offset.
+ *

Expand this a bit.  E.g., add something like:
Allows user space to specify their own fences within the command stream.


+ * AMDGPU_CHUNK_ID_DEPENDENCIES
+ * AMDGPU_CHUNK_ID_SYNCOBJ_IN
+ * AMDGPU_CHUNK_ID_SYNCOBJ_OUT
+ * These will be parsed as fence dependencies in given requirement,
+ * and will be remembered and to be synced later.
+ *
+ * __u32 _pad:
+ *
+ * __u64 chunks:
+ * Point to the CS chunks.

Pointer


+ *
+ * amdgpu_cs_submit() function will be called to initialize a scheduler
+ * job, and associate it to a HW ring, add a new fence to the context,

associate it with a


+ * and then push the job to the queue for scheduler to process,
+ * it will return fence sequence number to user space.
+ *
+ */
  int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  {
 struct amdgpu_device *adev = dev->dev_private;
@@ -1272,6 +1315,38 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
 return r;
  }

+/**
+ * DOC:  amdgpu_cs_wait_ioctl
+ *
+ * This ioctl checks a user space fence associated to a amdgpu fence whether
+ * it's signaled or waits to be signaled till timeout with kernel dma fence.

This reads sort of oddly.  how about:
The CS (Command Submission) wait ioctl waits for the specified fence
on the specified hw queue to signal or for the timeout, whichever
comes first.


+ * Once signaled, the associated CS is completed.
+ *
+ * In data structure:
+ *
+ * __u64 handle:
+ * The fence sequence number from amdgpu_cs_ioctl returned.
+ *
+ * __u64 timeout:
+ * Absolute timeout to wait.
+ *
+ * __u32 ip_type:
+ * __u32 ip_instance:
+ * __u32 ring:
+ * Map user space ring to a kernel HW ring, then use the seq(handle) to
+ * find the amdgpu fence, that will be checked and waited.
+ *
+ * __u32 ctx_id:
+ * ID for command submission context
+ *
+ * Out data:
+ *
+ * __u64 status:
+ * 0 CS completed
+ * 1 CS busy
+ *
+ */
+
  /**
   * amdgpu_cs_wait_ioctl - wait for a command submission to finish
   *
@@ -1358,6 +1433,37 @@ static struct dma_fence *amdgpu_cs_get_fence(struct 
amdgpu_device *adev,
 return fence;
  }

+/**
+ * DOC: amdgpu_cs_fence_to_handle_ioctl
+ *
+ * This ioctl converts a user space fence into a fence object handle or fd,
+ * or file fd based on the purpose in “what”, since using handles or fd will
+ * be more efficient than ioctl call from user space to check signaled.


This reads sort of oddly.  how about:
The CS (Command Submission) fence to handle ioctl converts a CS fence
into a drm sync object as specified in the what parameter.



+ *
+ * In data structure:
+ *
+ * struct drm_amdgpu_fence fence:
+ 

Re: [PATCH 2/2] drm/amdgpu/display: enable CONFIG_DRM_AMD_DC_DCN1_0 by default

[Michel Dänzer]

On 2018-05-31 04:33 PM, Alex Deucher wrote:
> It's required for displays on Raven.  The DCN bandwidth calcs use
> floating point, but DCN is APU only and it already depends on
> X86.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/display/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/Kconfig 
> b/drivers/gpu/drm/amd/display/Kconfig
> index 9d56889279b3..4c35625eb2c7 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -12,6 +12,7 @@ config DRM_AMD_DC
>  config DRM_AMD_DC_DCN1_0
>   bool "DCN 1.0 Raven family"
>   depends on DRM_AMD_DC && X86
> + default y
>   help
> Choose this option if you want to have
> RV family for display engine
> 

Can CONFIG_DRM_AMD_DC_DCN1_0 just be replaced by (something like)
CONFIG_X86 altogether?


-- 
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Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amdgpu: add kernel DOC for ioctls in amdgpu_cs.c file

[Alex Deucher]

On Wed, May 30, 2018 at 2:42 PM, Leo Liu  wrote:
> There are four ioctls in this files, and DOC gives details of
> data structures for each of ioctls, and their functionalities.
>
> Signed-off-by: Leo Liu 

A few comments below about readability.  With those fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 142 +
>  1 file changed, 142 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 12f0d18c6ee8..343ff115cff1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1217,6 +1217,49 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> return 0;
>  }
>
> +/**
> + * DOC:  amdgpu_cs_ioctl
> + *
> + * This ioctl processes user space command submission chunks,

Maybe give an overview of why we use the ioctl.  Something like:
The CS (Command Submission) ioctl is used to submit command buffers to
the kernel for scheduling on hw queues.  The chunk interface gives us
the flexibility to add new features to the ioctl by simply adding a
new chunk type.

> + * return a fence sequence number associated to a amdgpu fence.
> + *
> + * In data structure:
> + *
> + * __u32 ctx_id:
> + * Integer ID, created via DRM_AMDGPU_CTX ioctl call when user space
> + * command submission context created. It will be used as ID for later
> + * command submission context.

Required for all command submissions.  The kernel uses this to track
dependencies and guilt for command submissions that lead to an engine
lock up.

> + *
> + * __u32 bo_list_handle:
> + * Handle of resources list associated with this CS, created via
> + * DRM_AMDGPU_BO_LIST ioctl call before command submission, and
> + * the BOs in the list will be validated.

to make sure they are resident when the command buffer executes.

> + *
> + * __u32 num_chunks:
> + * Number of chunks, their types include:
> + * AMDGPU_CHUNK_ID_IB
> + * The data will be filled into IB buffer, and mappped to a HW ring.
> + *

Expand this a bit.  E.g.,
An IB (Indirect Buffer) is a stand alone command buffer that can be
scheduled fetching for execution on a hw queue.


> + * AMDGPU_CHUNK_ID_FENCE
> + * The data will be used to find user fence BO and its offset.
> + *

Expand this a bit.  E.g., add something like:
Allows user space to specify their own fences within the command stream.

> + * AMDGPU_CHUNK_ID_DEPENDENCIES
> + * AMDGPU_CHUNK_ID_SYNCOBJ_IN
> + * AMDGPU_CHUNK_ID_SYNCOBJ_OUT
> + * These will be parsed as fence dependencies in given requirement,
> + * and will be remembered and to be synced later.
> + *
> + * __u32 _pad:
> + *
> + * __u64 chunks:
> + * Point to the CS chunks.

Pointer

> + *
> + * amdgpu_cs_submit() function will be called to initialize a scheduler
> + * job, and associate it to a HW ring, add a new fence to the context,

associate it with a

> + * and then push the job to the queue for scheduler to process,
> + * it will return fence sequence number to user space.
> + *
> + */
>  int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file 
> *filp)
>  {
> struct amdgpu_device *adev = dev->dev_private;
> @@ -1272,6 +1315,38 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void 
> *data, struct drm_file *filp)
> return r;
>  }
>
> +/**
> + * DOC:  amdgpu_cs_wait_ioctl
> + *
> + * This ioctl checks a user space fence associated to a amdgpu fence whether
> + * it's signaled or waits to be signaled till timeout with kernel dma fence.

This reads sort of oddly.  how about:
The CS (Command Submission) wait ioctl waits for the specified fence
on the specified hw queue to signal or for the timeout, whichever
comes first.

> + * Once signaled, the associated CS is completed.
> + *
> + * In data structure:
> + *
> + * __u64 handle:
> + * The fence sequence number from amdgpu_cs_ioctl returned.
> + *
> + * __u64 timeout:
> + * Absolute timeout to wait.
> + *
> + * __u32 ip_type:
> + * __u32 ip_instance:
> + * __u32 ring:
> + * Map user space ring to a kernel HW ring, then use the seq(handle) to
> + * find the amdgpu fence, that will be checked and waited.
> + *
> + * __u32 ctx_id:
> + * ID for command submission context
> + *
> + * Out data:
> + *
> + * __u64 status:
> + * 0 CS completed
> + * 1 CS busy
> + *
> + */
> +
>  /**
>   * amdgpu_cs_wait_ioctl - wait for a command submission to finish
>   *
> @@ -1358,6 +1433,37 @@ static struct dma_fence *amdgpu_cs_get_fence(struct 
> amdgpu_device *adev,
> return fence;
>  }
>
> +/**
> + * DOC: amdgpu_cs_fence_to_handle_ioctl
> + *
> + * This ioctl converts a user space fence into a fence object handle or fd,
> + * or file fd based on the purpose in “what”, since using handles or fd will
> + * be more efficient than ioctl call from user space to check signaled.


This reads sort of oddly.  how about:
The CS (Command Submission) fence to handle ioctl converts a CS fence
into a drm sync object as specified in 

Re: [PATCH 1/3] Revert "drm/amdgpu: Add an ATPX quirk for hybrid laptop"

[Alex Deucher]

Ping?
These patches worked around a regression in the hda driver which has
since been fixed.

On Thu, May 24, 2018 at 3:46 PM, Alex Deucher  wrote:
> This reverts commit 13b40935cf64f59b93cf1c716a2033488e5a228c.
>
> This was a workaround for a bug in the HDA driver that prevented
> the HDA audio chip from going into runtime pm which prevented
> the GPU from going into runtime pm.
>
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106597
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> index 1bcb2b247335..daa06e7c5bb7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> @@ -569,7 +569,6 @@ static const struct amdgpu_px_quirk 
> amdgpu_px_quirk_list[] = {
> { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
> { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
> { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
> -   { 0x1002, 0x67DF, 0x1028, 0x0774, AMDGPU_PX_QUIRK_FORCE_ATPX },
> { 0, 0, 0, 0, 0 },
>  };
>
> --
> 2.13.6
>
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Re: [PATCH] amd/include: Move register declarations from display to include/asic_reg

[Harry Wentland]

On 2018-05-31 09:19 AM, David Francis wrote:
> A few register addresses were declared in
> amd/display/dc/dce*/dce*_resource.c.
> 
> They have been consolidated with the appropriate
> master list of registers in
> amd/include/asic_reg/dce/...
> 
> This will make them accessible to external tools that
> need direct asic register access
> 
> Signed-off-by: David Francis 
> ---
>  .../amd/display/dc/dce100/dce100_resource.c   | 35 ---
>  .../amd/display/dc/dce110/dce110_resource.c   | 35 ---
>  .../amd/display/dc/dce112/dce112_resource.c   | 35 ---
>  .../drm/amd/display/dc/dce80/dce80_resource.c | 34 --
>  .../drm/amd/include/asic_reg/dce/dce_10_0_d.h | 18 ++
>  .../drm/amd/include/asic_reg/dce/dce_11_0_d.h | 10 ++
>  .../drm/amd/include/asic_reg/dce/dce_11_2_d.h | 10 ++
>  .../drm/amd/include/asic_reg/dce/dce_8_0_d.h  | 15 
>  8 files changed, 53 insertions(+), 139 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> index 38ec0d609297..7615668a78e9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> @@ -59,46 +59,11 @@
>  #include "gmc/gmc_8_2_sh_mask.h"
>  #endif
>  
> -#ifndef mmDP_DPHY_INTERNAL_CTRL
> - #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
> - #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
> - #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
> - #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
> - #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
> - #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
> - #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
> - #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
> -#endif
> -
>  #ifndef mmBIOS_SCRATCH_2
>   #define mmBIOS_SCRATCH_2 0x05CB
>   #define mmBIOS_SCRATCH_6 0x05CF
>  #endif
>  
> -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
> - #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
> - #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
> - #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
> - #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
> - #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL   0x4FDC
> - #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL   0x54DC
> -#endif
> -
> -#ifndef mmDP_DPHY_FAST_TRAINING
> - #define mmDP_DPHY_FAST_TRAINING 0x4ABC
> - #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
> - #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
> - #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
> - #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
> - #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
> - #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
> - #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
> -#endif
> -
>  static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
>   {
>   .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> index ee33786bdef6..648187a28671 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> @@ -68,46 +68,11 @@
>  #include "gmc/gmc_8_2_sh_mask.h"
>  #endif
>  
> -#ifndef mmDP_DPHY_INTERNAL_CTRL
> - #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
> - #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
> - #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
> - #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
> - #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
> - #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
> - #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
> - #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
> - #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
> -#endif
> -
>  #ifndef mmBIOS_SCRATCH_2
>   #define mmBIOS_SCRATCH_2 0x05CB
>   #define mmBIOS_SCRATCH_6 0x05CF
>  #endif
>  
> -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
> - #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
> - #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
> - #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
> - #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
> - #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
> - #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL

[PATCH 2/2] drm/amdgpu/display: enable CONFIG_DRM_AMD_DC_DCN1_0 by default

[Alex Deucher]

It's required for displays on Raven.  The DCN bandwidth calcs use
floating point, but DCN is APU only and it already depends on
X86.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 9d56889279b3..4c35625eb2c7 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -12,6 +12,7 @@ config DRM_AMD_DC
 config DRM_AMD_DC_DCN1_0
bool "DCN 1.0 Raven family"
depends on DRM_AMD_DC && X86
+   default y
help
  Choose this option if you want to have
  RV family for display engine
-- 
2.13.6

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[PATCH 1/2] drm/amdgpu/display: drop DRM_AMD_DC_FBC kconfig option

[Alex Deucher]

Just enable it always.  This was leftover from feature
bring up.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/Kconfig| 10 --
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  5 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |  5 +
 drivers/gpu/drm/amd/display/dc/dc.h|  2 --
 drivers/gpu/drm/amd/display/dc/dc_types.h  |  2 --
 .../drm/amd/display/dc/dce110/dce110_compressor.c  |  2 --
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 22 ++
 .../drm/amd/display/dc/dce110/dce110_resource.c|  7 +--
 8 files changed, 5 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index d5d4586e6176..9d56889279b3 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -9,16 +9,6 @@ config DRM_AMD_DC
  support for AMDGPU. This adds required support for Vega and
  Raven ASICs.
 
-config DRM_AMD_DC_FBC
-   bool "AMD FBC - Enable Frame Buffer Compression"
-   depends on DRM_AMD_DC
-   help
- Choose this option if you want to use frame buffer compression
- support.
- This is a power optimisation feature, check its availability
- on your hardware before enabling this option.
-
-
 config DRM_AMD_DC_DCN1_0
bool "DCN 1.0 Raven family"
depends on DRM_AMD_DC && X86
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index da85140a32bb..c2166d801485 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -344,7 +344,6 @@ static void hotplug_notify_work_func(struct work_struct 
*work)
drm_kms_helper_hotplug_event(dev);
 }
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
 /* Allocate memory for FBC compressed data  */
 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 {
@@ -385,7 +384,6 @@ static void amdgpu_dm_fbc_init(struct drm_connector 
*connector)
}
 
 }
-#endif
 
 
 /* Init display KMS
@@ -3499,9 +3497,8 @@ static int amdgpu_dm_connector_get_modes(struct 
drm_connector *connector)
amdgpu_dm_connector_ddc_get_modes(connector, edid);
amdgpu_dm_connector_add_common_modes(encoder, connector);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
amdgpu_dm_fbc_init(connector);
-#endif
+
return amdgpu_dm_connector->num_modes;
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index cf06a642c51f..c159584c04f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -72,13 +72,11 @@ struct irq_list_head {
struct work_struct work;
 };
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
 struct dm_comressor_info {
void *cpu_addr;
struct amdgpu_bo *bo_ptr;
uint64_t gpu_addr;
 };
-#endif
 
 
 struct amdgpu_display_manager {
@@ -129,9 +127,8 @@ struct amdgpu_display_manager {
 * Caches device atomic state for suspend/resume
 */
struct drm_atomic_state *cached_state;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
+
struct dm_comressor_info compressor;
-#endif
 };
 
 struct amdgpu_dm_connector {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index be0dee18e09f..f09fa4722fc9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -289,9 +289,7 @@ struct dc {
bool apply_edp_fast_boot_optimization;
 
/* FBC compressor */
-#if defined(CONFIG_DRM_AMD_DC_FBC)
struct compressor *fbc_compressor;
-#endif
 };
 
 enum frame_buffer_mode {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index f463d3a8ef62..40d620f283ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -92,9 +92,7 @@ struct dc_context {
bool created_bios;
struct gpio_service *gpio_service;
struct i2caux *i2caux;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
uint64_t fbc_gpu_addr;
-#endif
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index e2994d337044..a79fc0b40a20 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -551,9 +551,7 @@ void dce110_compressor_construct(struct dce110_compressor 
*compressor,
compressor->base.lpt_channels_num = 0;
compressor->base.attached_inst = 0;
compressor->base.is_enabled = false;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
compressor->base.funcs = _compressor_funcs;
 
-#endif
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 

[PATCH 17/18] drm/amd/display: Add num_opp to resource_caps

[Harry Wentland]

From: Eric Bernstein 

Number of OPPs to be instantiated is based on number
of timing generators, not number of pipes.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/inc/resource.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 99c223bcad71..2da325ce781b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -417,6 +417,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 
 static const struct resource_caps res_cap = {
.num_timing_generator = 4,
+   .num_opp = 4,
.num_video_plane = 4,
.num_audio = 4,
.num_stream_encoder = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h 
b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 640a647f4611..e92facbd038f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -38,6 +38,7 @@ enum dce_version resource_parse_asic_id(
 
 struct resource_caps {
int num_timing_generator;
+   int num_opp;
int num_video_plane;
int num_audio;
int num_stream_encoder;
-- 
2.17.0

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[PATCH 18/18] drm/amd/display: Do not skip FBC init in failsafe mode

[Harry Wentland]

From: Mikita Lipski 

Initially FBC would be initialized if display's edid was correct
and all the modes acquired from it, but n case when edid is corrupted
or non-existant we must still initialize FBC.

Signed-off-by: Mikita Lipski 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 29176d2c5d6e..a35d2b224a9b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3497,12 +3497,12 @@ static int amdgpu_dm_connector_get_modes(struct 
drm_connector *connector)
 
encoder = helper->best_encoder(connector);
 
-   if (!edid || !drm_edid_is_valid(edid))
-   return drm_add_modes_noedid(connector, 640, 480);
-
-   amdgpu_dm_connector_ddc_get_modes(connector, edid);
-   amdgpu_dm_connector_add_common_modes(encoder, connector);
-
+   if (!edid || !drm_edid_is_valid(edid)) {
+   drm_add_modes_noedid(connector, 640, 480);
+   } else {
+   amdgpu_dm_connector_ddc_get_modes(connector, edid);
+   amdgpu_dm_connector_add_common_modes(encoder, connector);
+   }
 #if defined(CONFIG_DRM_AMD_DC_FBC)
amdgpu_dm_fbc_init(connector);
 #endif
-- 
2.17.0

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[PATCH 09/18] drm/amd/display: Add use_dynamic_meta flag to stream_state

[Harry Wentland]

From: Krunoslav Kovac 

Signed-off-by: Krunoslav Kovac 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 05b7ee82c285..45f9ecbb3d47 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2403,7 +2403,8 @@ static void set_hdr_static_info_packet(
 {
/* HDR Static Metadata info packet for HDR10 */
 
-   if (!stream->hdr_static_metadata.valid)
+   if (!stream->hdr_static_metadata.valid ||
+   stream->use_dynamic_meta)
return;
 
*info_packet = stream->hdr_static_metadata;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index aea4d0b59793..fe4dadd67804 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -66,6 +66,7 @@ struct dc_stream_state {
 
struct dc_info_packet hdr_static_metadata;
PHYSICAL_ADDRESS_LOC dmdata_address;
+   bool   use_dynamic_meta;
 
struct dc_transfer_func *out_transfer_func;
struct colorspace_transform gamut_remap_matrix;
-- 
2.17.0

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[PATCH 07/18] drm/amd/display: Move i2c and aux structs into dc_ddc_types.h

[Harry Wentland]

We'd like to use some of them in dc_link_ddc and amdgpu_dm and should
have them available in dc_ddc_types.h.

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 59 +++
 .../drm/amd/display/dc/i2caux/aux_engine.h| 44 +-
 .../gpu/drm/amd/display/dc/i2caux/engine.h| 15 +
 3 files changed, 62 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
index ee04812b4492..05c8c31d8b31 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
@@ -25,6 +25,65 @@
 #ifndef DC_DDC_TYPES_H_
 #define DC_DDC_TYPES_H_
 
+enum aux_transaction_type {
+   AUX_TRANSACTION_TYPE_DP,
+   AUX_TRANSACTION_TYPE_I2C
+};
+
+
+enum i2caux_transaction_action {
+   I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
+   I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
+   I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
+
+   I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
+   I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
+   I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
+
+   I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80,
+   I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90
+};
+
+enum aux_channel_operation_result {
+   AUX_CHANNEL_OPERATION_SUCCEEDED,
+   AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
+   AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
+   AUX_CHANNEL_OPERATION_FAILED_TIMEOUT,
+   AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
+};
+
+
+struct aux_request_transaction_data {
+   enum aux_transaction_type type;
+   enum i2caux_transaction_action action;
+   /* 20-bit AUX channel transaction address */
+   uint32_t address;
+   /* delay, in 100-microsecond units */
+   uint8_t delay;
+   uint32_t length;
+   uint8_t *data;
+};
+
+enum aux_transaction_reply {
+   AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
+   AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
+   AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
+
+   AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
+   AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
+   AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
+
+   AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40,
+
+   AUX_TRANSACTION_REPLY_INVALID = 0xFF
+};
+
+struct aux_reply_transaction_data {
+   enum aux_transaction_reply status;
+   uint32_t length;
+   uint8_t *data;
+};
+
 struct i2c_payload {
bool write;
uint8_t address;
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h 
b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
index b9e35d0474c6..b01488f710d5 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
@@ -26,49 +26,7 @@
 #ifndef __DAL_AUX_ENGINE_H__
 #define __DAL_AUX_ENGINE_H__
 
-enum aux_transaction_type {
-   AUX_TRANSACTION_TYPE_DP,
-   AUX_TRANSACTION_TYPE_I2C
-};
-
-struct aux_request_transaction_data {
-   enum aux_transaction_type type;
-   enum i2caux_transaction_action action;
-   /* 20-bit AUX channel transaction address */
-   uint32_t address;
-   /* delay, in 100-microsecond units */
-   uint8_t delay;
-   uint32_t length;
-   uint8_t *data;
-};
-
-enum aux_transaction_reply {
-   AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
-   AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
-   AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
-
-   AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
-   AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
-   AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
-
-   AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40,
-
-   AUX_TRANSACTION_REPLY_INVALID = 0xFF
-};
-
-struct aux_reply_transaction_data {
-   enum aux_transaction_reply status;
-   uint32_t length;
-   uint8_t *data;
-};
-
-enum aux_channel_operation_result {
-   AUX_CHANNEL_OPERATION_SUCCEEDED,
-   AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
-   AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
-   AUX_CHANNEL_OPERATION_FAILED_TIMEOUT,
-   AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
-};
+#include "dc_ddc_types.h"
 
 struct aux_engine;
 
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/engine.h 
b/drivers/gpu/drm/amd/display/dc/i2caux/engine.h
index c1109706a880..1e8a1585e401 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/engine.h
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/engine.h
@@ -26,6 +26,8 @@
 #ifndef __DAL_ENGINE_H__
 #define __DAL_ENGINE_H__
 
+#include "dc_ddc_types.h"
+
 enum i2caux_transaction_operation {
I2CAUX_TRANSACTION_READ,
I2CAUX_TRANSACTION_WRITE
@@ -76,19 +78,6 @@ enum i2c_default_speed {
I2CAUX_DEFAULT_I2C_SW_SPEED = 50
 };
 
-enum i2caux_transaction_action {
-   I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
-   I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
-   I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 

[PATCH 08/18] drm/amd/display: Update color props when modeset is required

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

This fixes issues where color management properties don't persist
over DPMS on/off, or when the CRTC is moved across connectors.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b6020a83cdb0..29176d2c5d6e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4848,8 +4848,12 @@ static int dm_update_crtcs_state(struct 
amdgpu_display_manager *dm,
update_stream_scaling_settings(
_crtc_state->mode, dm_new_conn_state, 
dm_new_crtc_state->stream);
 
-   /* Color managment settings */
-   if (dm_new_crtc_state->base.color_mgmt_changed) {
+   /*
+* Color management settings. We also update color properties
+* when a modeset is needed, to ensure it gets reprogrammed.
+*/
+   if (dm_new_crtc_state->base.color_mgmt_changed ||
+   drm_atomic_crtc_needs_modeset(new_crtc_state)) {
ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
if (ret)
goto fail;
-- 
2.17.0

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[PATCH 13/18] drm/amd/display: Disable stats by default

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/modules/stats/stats.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index fa0665d09075..480eb2cdd55d 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -29,7 +29,7 @@
 #include "core_types.h"
 
 #define DAL_STATS_ENABLE_REGKEY"DalStatsEnable"
-#define DAL_STATS_ENABLE_REGKEY_DEFAULT0x0001
+#define DAL_STATS_ENABLE_REGKEY_DEFAULT0x
 #define DAL_STATS_ENABLE_REGKEY_ENABLED0x0001
 
 #define DAL_STATS_ENTRIES_REGKEY   "DalStatsEntries"
-- 
2.17.0

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[PATCH 12/18] drm/amd/display: Convert quotes to Ascii quotes

[Harry Wentland]

From: Krunoslav Kovac 

Signed-off-by: Harry Wentland 
Signed-off-by: Krunoslav Kovac 
Reviewed-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 32a4997714c1..c6a13d0486bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -301,7 +301,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
/* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to 
indicate the
 * Pixel Encoding/Colorimetry Format and that a Sink device shall 
ignore MISC1, bit 7,
-* and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become 
“don’t care”).
+* and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become 
"don't care").
 */
if ((crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
(output_color_space == COLOR_SPACE_2020_YCBCR) ||
-- 
2.17.0

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[PATCH 10/18] drm/amd/display: Drop duplicate dc_stream_set_static_screen_events definition

[Harry Wentland]

From: Krunoslav Kovac 

Signed-off-by: Harry Wentland 
Signed-off-by: Krunoslav Kovac 
Reviewed-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index fe4dadd67804..584c56b94937 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -303,9 +303,4 @@ bool dc_stream_get_crtc_position(struct dc *dc,
 unsigned int *v_pos,
 unsigned int *nom_v_pos);
 
-void dc_stream_set_static_screen_events(struct dc *dc,
-   struct dc_stream_state **stream,
-   int num_streams,
-   const struct dc_static_screen_events 
*events);
-
 #endif /* DC_STREAM_H_ */
-- 
2.17.0

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[PATCH 11/18] drm/amd/display: Make it more clear when info frames affect DP or HDMI

[Harry Wentland]

From: Krunoslav Kovac 

Signed-off-by: Harry Wentland 
Signed-off-by: Krunoslav Kovac 
Reviewed-by: Anthony Koo 
---
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 59e2bbf4d676..9f3b969b5a0e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -667,16 +667,25 @@ static enum dc_status bios_parser_crtc_source_select(
 
 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 {
+   bool is_hdmi;
+   bool is_dp;
+
ASSERT(pipe_ctx->stream);
 
if (pipe_ctx->stream_res.stream_enc == NULL)
return;  /* this is not root pipe */
 
-   if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+   is_hdmi = dc_is_hdmi_signal(pipe_ctx->stream->signal);
+   is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
+
+   if (!is_hdmi && !is_dp)
+   return;
+
+   if (is_hdmi)

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
pipe_ctx->stream_res.stream_enc,
_ctx->stream_res.encoder_info_frame);
-   else if (dc_is_dp_signal(pipe_ctx->stream->signal))
+   else
pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
pipe_ctx->stream_res.stream_enc,
_ctx->stream_res.encoder_info_frame);
-- 
2.17.0

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[PATCH 16/18] drm/amd/display: Allow DP register double buffer

[Harry Wentland]

From: Eric Bernstein 

Remove setting DP_DB_DISABLE to avoid issues when changing
bit depth after vbios take over.
Refactor code to perform single register update for both
pixel encoding and component depth fields.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dce/dce_stream_encoder.c   |  5 ---
 .../display/dc/dcn10/dcn10_stream_encoder.c   | 44 ---
 2 files changed, 19 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index c0e813c7ddd4..91642e684858 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -289,11 +289,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
 
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-   if (REG(DP_DB_CNTL))
-   REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
-#endif
-
/* set pixel encoding */
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index c6a13d0486bb..6f9078f3c4d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -257,20 +257,18 @@ void enc1_stream_encoder_dp_set_stream_attribute(
uint8_t colorimetry_bpc;
uint8_t dynamic_range_rgb = 0; /*full range*/
uint8_t dynamic_range_ycbcr = 1; /*bt709*/
+   uint8_t dp_pixel_encoding = 0;
+   uint8_t dp_component_depth = 0;
 
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
-   REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
-
/* set pixel encoding */
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-   DP_PIXEL_ENCODING_TYPE_YCBCR422);
+   dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
break;
case PIXEL_ENCODING_YCBCR444:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-   DP_PIXEL_ENCODING_TYPE_YCBCR444);
+   dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
 
if (crtc_timing->flags.Y_ONLY)
if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -278,8 +276,8 @@ void enc1_stream_encoder_dp_set_stream_attribute(
 * Color depth of Y-only could be
 * 8, 10, 12, 16 bits
 */
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-   DP_PIXEL_ENCODING_TYPE_Y_ONLY);
+   dp_pixel_encoding = 
DP_PIXEL_ENCODING_TYPE_Y_ONLY;
+
/* Note: DP_MSA_MISC1 bit 7 is the indicator
 * of Y-only mode.
 * This bit is set in HW if register
@@ -287,13 +285,11 @@ void enc1_stream_encoder_dp_set_stream_attribute(
 */
break;
case PIXEL_ENCODING_YCBCR420:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-   DP_PIXEL_ENCODING_TYPE_YCBCR420);
+   dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
break;
default:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-   DP_PIXEL_ENCODING_TYPE_RGB444);
+   dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
break;
}
 
@@ -314,32 +310,30 @@ void enc1_stream_encoder_dp_set_stream_attribute(
/* set color depth */
switch (crtc_timing->display_color_depth) {
case COLOR_DEPTH_666:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-   0);
+   dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
break;
case COLOR_DEPTH_888:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-   DP_COMPONENT_PIXEL_DEPTH_8BPC);
+   dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
break;
case COLOR_DEPTH_101010:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-   DP_COMPONENT_PIXEL_DEPTH_10BPC);
-
+   dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
break;
case COLOR_DEPTH_121212:
-   REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-   DP_COMPONENT_PIXEL_DEPTH_12BPC);
+   

[PATCH 15/18] drm/amd/display: create sink_id in dc_sink structure to idenitify all sinks

[Harry Wentland]

From: Alvin lee 

Signed-off-by: Alvin lee 
Reviewed-by: Jun Lei 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 1 +
 drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 4 
 drivers/gpu/drm/amd/display/dc/dc.h   | 6 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
 4 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d7307b38c0a8..858249ee0a43 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -479,6 +479,7 @@ static bool construct(struct dc *dc,
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = dc;
dc_ctx->asic_id = init_params->asic_id;
+   dc_ctx->dc_sink_id_count = 0;
dc->ctx = dc_ctx;
 
dc->current_state = dc_create_state();
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
index 25fae38409ab..9971b515c3eb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
@@ -53,6 +53,10 @@ static bool construct(struct dc_sink *sink, const struct 
dc_sink_init_data *init
sink->dongle_max_pix_clk = init_params->dongle_max_pix_clk;
sink->converter_disable_audio = init_params->converter_disable_audio;
sink->dc_container_id = NULL;
+   sink->sink_id = init_params->link->ctx->dc_sink_id_count;
+   // increment dc_sink_id_count because we don't want two sinks with same 
ID
+   // unless they are actually the same
+   init_params->link->ctx->dc_sink_id_count++;
 
return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 94ac1248cfd7..2c4784843d4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -668,9 +668,13 @@ struct dc_sink {
struct dc_link *link;
struct dc_context *ctx;
 
+   uint32_t sink_id;
+
/* private to dc_sink.c */
+   // refcount must be the last member in dc_sink, since we want the
+   // sink structure to be logically cloneable up to (but not including)
+   // refcount
struct kref refcount;
-
 };
 
 void dc_sink_retain(struct dc_sink *sink);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index f463d3a8ef62..227cb72481b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -92,6 +92,7 @@ struct dc_context {
bool created_bios;
struct gpio_service *gpio_service;
struct i2caux *i2caux;
+   uint32_t dc_sink_id_count;
 #if defined(CONFIG_DRM_AMD_DC_FBC)
uint64_t fbc_gpu_addr;
 #endif
-- 
2.17.0

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[PATCH 14/18] drm/amd/display: Add new transfer type HWPWL

[Harry Wentland]

From: Vitaly Prosyak 

It is used when curve register settings are generated
by 'matlab', i.e. bypass color module calculation.

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index be0dee18e09f..94ac1248cfd7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -359,6 +359,7 @@ enum dc_transfer_func_type {
TF_TYPE_PREDEFINED,
TF_TYPE_DISTRIBUTED_POINTS,
TF_TYPE_BYPASS,
+   TF_TYPE_HWPWL
 };
 
 struct dc_transfer_func_distributed_points {
@@ -384,12 +385,15 @@ enum dc_transfer_func_predefined {
 
 struct dc_transfer_func {
struct kref refcount;
-   struct dc_transfer_func_distributed_points tf_pts;
enum dc_transfer_func_type type;
enum dc_transfer_func_predefined tf;
/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
uint32_t sdr_ref_white_level;
struct dc_context *ctx;
+   union {
+   struct pwl_params pwl;
+   struct dc_transfer_func_distributed_points tf_pts;
+   };
 };
 
 /*
-- 
2.17.0

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[PATCH 02/18] drm/amd/display: Write TEST_EDID_CHECKSUM_WRITE for EDID tests

[Harry Wentland]

From: Mikita Lipski 

Extract edid's checksum and send it back for verification if EDID_TEST
is requested.

Also added a flag for EDID checksum write in TEST_RESPONSE structure,
and simple spelling fix.

Signed-off-by: Mikita Lipski 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 28 +++
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  5 ++--
 2 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index bd449351803f..dea49dc9b518 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -497,6 +497,34 @@ enum dc_edid_status dm_helpers_read_local_edid(
DRM_ERROR("EDID err: %d, on connector: %s",
edid_status,
aconnector->base.name);
+   if (link->aux_mode) {
+   union test_request test_request = {0};
+   union test_response test_response = {0};
+
+   dm_helpers_dp_read_dpcd(ctx,
+   link,
+   DP_TEST_REQUEST,
+   _request.raw,
+   sizeof(union test_request));
+
+   if (!test_request.bits.EDID_READ)
+   return edid_status;
+
+   test_response.bits.EDID_CHECKSUM_WRITE = 1;
+
+   dm_helpers_dp_write_dpcd(ctx,
+   link,
+   DP_TEST_EDID_CHECKSUM,
+   
>dc_edid.raw_edid[sink->dc_edid.length-1],
+   1);
+
+   dm_helpers_dp_write_dpcd(ctx,
+   link,
+   DP_TEST_RESPONSE,
+   _response.raw,
+   sizeof(test_response));
+
+   }
 
return edid_status;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 90bccd5ccaa2..da93ab43f2d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -430,7 +430,7 @@ union test_request {
struct {
uint8_t LINK_TRAINING :1;
uint8_t LINK_TEST_PATTRN  :1;
-   uint8_t EDID_REAT :1;
+   uint8_t EDID_READ :1;
uint8_t PHY_TEST_PATTERN  :1;
uint8_t AUDIO_TEST_PATTERN:1;
uint8_t RESERVED  :1;
@@ -443,7 +443,8 @@ union test_response {
struct {
uint8_t ACK :1;
uint8_t NO_ACK  :1;
-   uint8_t RESERVED:6;
+   uint8_t EDID_CHECKSUM_WRITE:1;
+   uint8_t RESERVED:5;
} bits;
uint8_t raw;
 };
-- 
2.17.0

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[PATCH 04/18] drm/amd/display: Program vline interrupt on FAST update

[Harry Wentland]

From: SivapiriyanKumarasamy 

Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Tony Cheng 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c88f6612bfb6..d7307b38c0a8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1290,6 +1290,13 @@ static void commit_planes_do_stream_update(struct dc *dc,
stream_update->adjust->v_total_min,
stream_update->adjust->v_total_max);
 
+   if (stream_update->periodic_fn_vsync_delta &&
+   pipe_ctx->stream_res.tg &&
+   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
+   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
+   pipe_ctx->stream_res.tg, 
_ctx->stream->timing,
+   
pipe_ctx->stream->periodic_fn_vsync_delta);
+
/* Full fe update*/
if (update_type == UPDATE_TYPE_FAST)
continue;
@@ -1317,12 +1324,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
pipe_ctx->stream_res.abm, 
stream->abm_level);
}
 
-   if (stream_update->periodic_fn_vsync_delta &&
-   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
-   
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
-   pipe_ctx->stream_res.tg, 
_ctx->stream->timing,
-   
pipe_ctx->stream->periodic_fn_vsync_delta);
-
if (stream_update->hdr_static_metadata ||
stream_update->vrr_infopacket) {
resource_build_info_frame(pipe_ctx);
-- 
2.17.0

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[PATCH 05/18] drm/amd/display: Fix BUG_ON during CRTC atomic check update

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

For cases where the CRTC is inactive (DPMS off), where a modeset is not
required, yet the CRTC is still in the atomic state, we should not
attempt to update anything on it.

Previously, we were relying on the modereset_required() helper to check
the above condition. However, the function returns false immediatly if
a modeset is not required, ignoring the CRTC's enable/active state
flags. The correct way to filter is by looking at these flags instead.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e7ecddf359da..b6020a83cdb0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4830,15 +4830,16 @@ static int dm_update_crtcs_state(struct 
amdgpu_display_manager *dm,
 * We want to do dc stream updates that do not require a
 * full modeset below.
 */
-   if (!enable || !aconnector || 
modereset_required(new_crtc_state))
+   if (!(enable && aconnector && new_crtc_state->enable &&
+ new_crtc_state->active))
continue;
/*
 * Given above conditions, the dc state cannot be NULL because:
-* 1. We're attempting to enable a CRTC. Which has a...
-* 2. Valid connector attached, and
-* 3. User does not want to reset it (disable or mark inactive,
-*which can happen on a CRTC that's already disabled).
-* => It currently exists.
+* 1. We're in the process of enabling CRTCs (just been added
+*to the dc context, or already is on the context)
+* 2. Has a valid connector attached, and
+* 3. Is currently active and enabled.
+* => The dc stream state currently exists.
 */
BUG_ON(dm_new_crtc_state->stream == NULL);
 
-- 
2.17.0

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[PATCH 06/18] drm/amd/display: Stream encoder update

[Harry Wentland]

From: Eric Bernstein 

Update stream encoder based on feedback from HW team.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../display/dc/dcn10/dcn10_stream_encoder.c   | 30 +--
 1 file changed, 1 insertion(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 147f61416fa5..32a4997714c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -1097,27 +1097,6 @@ static union audio_cea_channels speakers_to_channels(
return cea_channels;
 }
 
-static uint32_t calc_max_audio_packets_per_line(
-   const struct audio_crtc_info *crtc_info)
-{
-   uint32_t max_packets_per_line;
-
-   max_packets_per_line =
-   crtc_info->h_total - crtc_info->h_active;
-
-   if (crtc_info->pixel_repetition)
-   max_packets_per_line *= crtc_info->pixel_repetition;
-
-   /* for other hdmi features */
-   max_packets_per_line -= 58;
-   /* for Control Period */
-   max_packets_per_line -= 16;
-   /* Number of Audio Packets per Line */
-   max_packets_per_line /= 32;
-
-   return max_packets_per_line;
-}
-
 static void get_audio_clock_info(
enum dc_color_depth color_depth,
uint32_t crtc_pixel_clock_in_khz,
@@ -1211,16 +1190,9 @@ static void enc1_se_setup_hdmi_audio(
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
struct audio_clock_info audio_clock_info = {0};
-   uint32_t max_packets_per_line;
-
-   /* For now still do calculation, although this field is ignored when
-* above HDMI_PACKET_GEN_VERSION set to 1
-*/
-   max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
 
/* HDMI_AUDIO_PACKET_CONTROL */
-   REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
-   HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
+   REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
HDMI_AUDIO_DELAY_EN, 1);
 
/* AFMT_AUDIO_PACKET_CONTROL */
-- 
2.17.0

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[PATCH 03/18] drm/amd/display: Make atomic-check validate underscan changes

[Harry Wentland]

From: David Francis 

When the underscan state was changed, atomic-check was triggering a
validation but passing the old underscan values.  This change adds a
somewhat hacky check in dm_update_crtcs_state that will update the
stream if old and newunderscan values are different.
This was causing 4k on Fiji to allow underscan when it wasn't permitted.

Signed-off-by: David Francis 
Reviewed-by: David Francis 
Acked-by: Harry Wentland 
Cc: sta...@vger.kernel.org
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +--
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 07f4793a945f..e7ecddf359da 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4679,8 +4679,8 @@ static int dm_update_crtcs_state(struct 
amdgpu_display_manager *dm,
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
struct amdgpu_crtc *acrtc = NULL;
struct amdgpu_dm_connector *aconnector = NULL;
-   struct drm_connector_state *new_con_state = NULL;
-   struct dm_connector_state *dm_conn_state = NULL;
+   struct drm_connector_state *drm_new_conn_state = NULL, 
*drm_old_conn_state = NULL;
+   struct dm_connector_state *dm_new_conn_state = NULL, 
*dm_old_conn_state = NULL;
struct drm_plane_state *new_plane_state = NULL;
 
new_stream = NULL;
@@ -4701,19 +4701,24 @@ static int dm_update_crtcs_state(struct 
amdgpu_display_manager *dm,
/* TODO This hack should go away */
if (aconnector && enable) {
// Make sure fake sink is created in plug-in scenario
-   new_con_state = drm_atomic_get_connector_state(state,
+   drm_new_conn_state = 
drm_atomic_get_new_connector_state(state,

>base);
+   drm_old_conn_state = 
drm_atomic_get_old_connector_state(state,
+   
>base);
+
 
-   if (IS_ERR(new_con_state)) {
-   ret = PTR_ERR_OR_ZERO(new_con_state);
+
+   if (IS_ERR(drm_new_conn_state)) {
+   ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
break;
}
 
-   dm_conn_state = to_dm_connector_state(new_con_state);
+   dm_new_conn_state = 
to_dm_connector_state(drm_new_conn_state);
+   dm_old_conn_state = 
to_dm_connector_state(drm_old_conn_state);
 
new_stream = create_stream_for_sink(aconnector,
 
_crtc_state->mode,
-   dm_conn_state);
+   dm_new_conn_state);
 
/*
 * we can have no stream on ACTION_SET if a display
@@ -4729,7 +4734,7 @@ static int dm_update_crtcs_state(struct 
amdgpu_display_manager *dm,
}
 
set_freesync_on_stream(dm, dm_new_crtc_state,
-  dm_conn_state, new_stream);
+   dm_new_conn_state, new_stream);
 
if (dc_is_stream_unchanged(new_stream, 
dm_old_crtc_state->stream) &&
dc_is_stream_scaling_unchanged(new_stream, 
dm_old_crtc_state->stream)) {
@@ -4837,6 +4842,11 @@ static int dm_update_crtcs_state(struct 
amdgpu_display_manager *dm,
 */
BUG_ON(dm_new_crtc_state->stream == NULL);
 
+   /* Scaling or underscan settings */
+   if (is_scaling_state_different(dm_old_conn_state, 
dm_new_conn_state))
+   update_stream_scaling_settings(
+   _crtc_state->mode, dm_new_conn_state, 
dm_new_crtc_state->stream);
+
/* Color managment settings */
if (dm_new_crtc_state->base.color_mgmt_changed) {
ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
-- 
2.17.0

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[PATCH 00/18] DC Patches May 31, 2018

[Harry Wentland]

 * Fix underscan validation in atomic_check (David)
 * Fix BUG_ON during CRTC atomic check update (Leo)
 * Apply color properties after DPMS changes (Leo)
 * Bunch of DP CTS fixes (Mikita)

Alex, can you pull the following into 4.17 fixes?
  drm/amd/display: Make atomic-check validate underscan changes
  drm/amd/display: Fix BUG_ON during CRTC atomic check update
  drm/amd/display: Update color props when modeset is required

Alvin lee (1):
  drm/amd/display: create sink_id in dc_sink structure to idenitify all
sinks

Anthony Koo (1):
  drm/amd/display: Disable stats by default

David Francis (1):
  drm/amd/display: Make atomic-check validate underscan changes

Eric Bernstein (3):
  drm/amd/display: Stream encoder update
  drm/amd/display: Allow DP register double buffer
  drm/amd/display: Add num_opp to resource_caps

Harry Wentland (1):
  drm/amd/display: Move i2c and aux structs into dc_ddc_types.h

Krunoslav Kovac (4):
  drm/amd/display: Add use_dynamic_meta flag to stream_state
  drm/amd/display: Drop duplicate dc_stream_set_static_screen_events
definition
  drm/amd/display: Make it more clear when info frames affect DP or HDMI
  drm/amd/display: Convert quotes to Ascii quotes

Leo (Sunpeng) Li (2):
  drm/amd/display: Fix BUG_ON during CRTC atomic check update
  drm/amd/display: Update color props when modeset is required

Mikita Lipski (3):
  drm/amd/display: Drop to fail-safe mode if edid is bad
  drm/amd/display: Write TEST_EDID_CHECKSUM_WRITE for EDID tests
  drm/amd/display: Do not skip FBC init in failsafe mode

SivapiriyanKumarasamy (1):
  drm/amd/display: Program vline interrupt on FAST update

Vitaly Prosyak (1):
  drm/amd/display: Add new transfer type HWPWL

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 55 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 28 +++
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 14 ++--
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  3 +-
 drivers/gpu/drm/amd/display/dc/core/dc_sink.c |  4 +
 drivers/gpu/drm/amd/display/dc/dc.h   | 12 ++-
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 59 ++
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  5 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h|  6 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h |  1 +
 .../amd/display/dc/dce/dce_stream_encoder.c   |  5 --
 .../display/dc/dce110/dce110_hw_sequencer.c   | 13 +++-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  1 +
 .../display/dc/dcn10/dcn10_stream_encoder.c   | 76 +--
 .../drm/amd/display/dc/i2caux/aux_engine.h| 44 +--
 .../gpu/drm/amd/display/dc/i2caux/engine.h| 15 +---
 drivers/gpu/drm/amd/display/dc/inc/resource.h |  1 +
 .../gpu/drm/amd/display/modules/stats/stats.c |  2 +-
 18 files changed, 191 insertions(+), 153 deletions(-)

-- 
2.17.0

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[PATCH] amd/include: Move register declarations from display to include/asic_reg

[David Francis]

A few register addresses were declared in
amd/display/dc/dce*/dce*_resource.c.

They have been consolidated with the appropriate
master list of registers in
amd/include/asic_reg/dce/...

This will make them accessible to external tools that
need direct asic register access

Signed-off-by: David Francis 
---
 .../amd/display/dc/dce100/dce100_resource.c   | 35 ---
 .../amd/display/dc/dce110/dce110_resource.c   | 35 ---
 .../amd/display/dc/dce112/dce112_resource.c   | 35 ---
 .../drm/amd/display/dc/dce80/dce80_resource.c | 34 --
 .../drm/amd/include/asic_reg/dce/dce_10_0_d.h | 18 ++
 .../drm/amd/include/asic_reg/dce/dce_11_0_d.h | 10 ++
 .../drm/amd/include/asic_reg/dce/dce_11_2_d.h | 10 ++
 .../drm/amd/include/asic_reg/dce/dce_8_0_d.h  | 15 
 8 files changed, 53 insertions(+), 139 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 38ec0d609297..7615668a78e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -59,46 +59,11 @@
 #include "gmc/gmc_8_2_sh_mask.h"
 #endif
 
-#ifndef mmDP_DPHY_INTERNAL_CTRL
-   #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-   #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-   #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-   #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-   #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-   #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-   #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-   #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-#endif
-
 #ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
#define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
-#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
-   #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
-   #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
-   #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
-   #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
-   #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL   0x4FDC
-   #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL   0x54DC
-#endif
-
-#ifndef mmDP_DPHY_FAST_TRAINING
-   #define mmDP_DPHY_FAST_TRAINING 0x4ABC
-   #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
-   #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
-   #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
-   #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
-   #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
-   #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
-   #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
-#endif
-
 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
{
.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index ee33786bdef6..648187a28671 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -68,46 +68,11 @@
 #include "gmc/gmc_8_2_sh_mask.h"
 #endif
 
-#ifndef mmDP_DPHY_INTERNAL_CTRL
-   #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-   #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-   #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-   #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-   #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-   #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-   #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-   #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-   #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-#endif
-
 #ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
#define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
-#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
-   #define mmDP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL   0x4ADC
-   #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL   0x4BDC
-   #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL   0x4CDC
-   #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL   0x4DDC
-   #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL   0x4EDC
-   #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL   0x4FDC
-   #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL   0x54DC
-#endif
-
-#ifndef mmDP_DPHY_FAST_TRAINING
-   #define mmDP_DPHY_FAST_TRAINING

Re: [PATCH] drm/gfx9: Update gc goldensetting for vega20.

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Feifei Xu 

Sent: Thursday, May 31, 2018 9:10:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei
Subject: [PATCH] drm/gfx9: Update gc goldensetting for vega20.

Update mmCB_DCC_CONFIG register goldensetting.

Signed-off-by: Feifei Xu 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index eb50d86..3647729 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -112,6 +112,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_9_0_vg10[] =

 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 {
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f80, 0x0480),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f00, 
0x0a00),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x3000, 
0x1000),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 
0x22014042),
--
2.7.4

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[PATCH] drm/gfx9: Update gc goldensetting for vega20.

[Feifei Xu]

Update mmCB_DCC_CONFIG register goldensetting.

Signed-off-by: Feifei Xu 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index eb50d86..3647729 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -112,6 +112,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_9_0_vg10[] =
 
 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 {
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f80, 0x0480),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f00, 
0x0a00),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x3000, 
0x1000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
-- 
2.7.4

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Re: [PATCH] drm/amd/display: avoid sleeping in atomic context while creating new state (V2)

[Harry Wentland]

On 2018-05-31 05:59 AM, Shirish S wrote:
> This patch fixes the warning messages that are caused due to calling
> sleep in atomic context as below:
> 
> BUG: sleeping function called from invalid context at mm/slab.h:419
> in_atomic(): 1, irqs_disabled(): 1, pid: 5, name: kworker/u4:0
> CPU: 1 PID: 5 Comm: kworker/u4:0 Tainted: GW   4.14.35 #941
> Workqueue: events_unbound commit_work
> Call Trace:
>  dump_stack+0x4d/0x63
>  ___might_sleep+0x11f/0x12e
>  kmem_cache_alloc_trace+0x41/0xea
>  dc_create_state+0x1f/0x30
>  dc_commit_updates_for_stream+0x73/0x4cf
>  ? amdgpu_get_crtc_scanoutpos+0x82/0x16b
>  amdgpu_dm_do_flip+0x239/0x298
>  amdgpu_dm_commit_planes.isra.23+0x379/0x54b
>  ? dc_commit_state+0x3da/0x404
>  amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
>  ? wait_for_common+0x5b/0x69
>  commit_tail+0x42/0x64
>  process_one_work+0x1b0/0x314
>  worker_thread+0x1cb/0x2c1
>  ? create_worker+0x1da/0x1da
>  kthread+0x156/0x15e
>  ? kthread_flush_work+0xea/0xea
>  ret_from_fork+0x22/0x40
> 
> V2: fix applicable only to dc_create_state() and not dc_create().
> 
> Signed-off-by: Shirish S 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index c88f661..839e3f6 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -953,7 +953,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
>  struct dc_state *dc_create_state(void)
>  {
>   struct dc_state *context = kzalloc(sizeof(struct dc_state),
> -GFP_KERNEL);
> +GFP_ATOMIC);
>  
>   if (!context)
>   return NULL;
> 
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Re: [PATCH] drm/amd/display: avoid sleeping in atomic context while creating new state (V2)

[Deucher, Alexander]

All of the V2 patches are:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Shirish S 

Sent: Thursday, May 31, 2018 5:59:24 AM
To: amd-gfx@lists.freedesktop.org; Wentland, Harry
Cc: S, Shirish
Subject: [PATCH] drm/amd/display: avoid sleeping in atomic context while 
creating new state (V2)

This patch fixes the warning messages that are caused due to calling
sleep in atomic context as below:

BUG: sleeping function called from invalid context at mm/slab.h:419
in_atomic(): 1, irqs_disabled(): 1, pid: 5, name: kworker/u4:0
CPU: 1 PID: 5 Comm: kworker/u4:0 Tainted: GW   4.14.35 #941
Workqueue: events_unbound commit_work
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 kmem_cache_alloc_trace+0x41/0xea
 dc_create_state+0x1f/0x30
 dc_commit_updates_for_stream+0x73/0x4cf
 ? amdgpu_get_crtc_scanoutpos+0x82/0x16b
 amdgpu_dm_do_flip+0x239/0x298
 amdgpu_dm_commit_planes.isra.23+0x379/0x54b
 ? dc_commit_state+0x3da/0x404
 amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 process_one_work+0x1b0/0x314
 worker_thread+0x1cb/0x2c1
 ? create_worker+0x1da/0x1da
 kthread+0x156/0x15e
 ? kthread_flush_work+0xea/0xea
 ret_from_fork+0x22/0x40

V2: fix applicable only to dc_create_state() and not dc_create().

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c88f661..839e3f6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -953,7 +953,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 struct dc_state *dc_create_state(void)
 {
 struct dc_state *context = kzalloc(sizeof(struct dc_state),
-  GFP_KERNEL);
+  GFP_ATOMIC);

 if (!context)
 return NULL;
--
2.7.4

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[PATCH] drm/amdgpu: avoid sleep while executing atombios table (V2)

[Shirish S]

This patch replaces kzalloc's flag from GFP_KERNEL to
GFP_ATOMIC to avoid sleeping in atomic context.

Below is the stack trace:

BUG: sleeping function called from invalid context at mm/slab.h:***
in_atomic(): 1, irqs_disabled(): 0, pid: 1137, name: DrmThread
CPU: 1 PID: 1137 Comm: DrmThread Tainted: GW   4.14.43 #10
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 __kmalloc+0x76/0x126
 amdgpu_atom_execute_table_locked+0xfc/0x285
 amdgpu_atom_execute_table+0x5d/0x72
 transmitter_control_v1_5+0xef/0x11a
 hwss_edp_backlight_control+0x132/0x151
 dce110_disable_stream+0x133/0x16e
 core_link_disable_stream+0x1c5/0x23b
 dce110_reset_hw_ctx_wrap+0xb4/0x1aa
 dce110_apply_ctx_to_hw+0x4e/0x6da
 ? generic_reg_get+0x1f/0x33
 dc_commit_state+0x33f/0x3d2
 amdgpu_dm_atomic_commit_tail+0x2cf/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 drm_atomic_helper_commit+0xdc/0xf9
 drm_atomic_helper_set_config+0x5c/0x76
 __drm_mode_set_config_internal+0x64/0x105
 drm_mode_setcrtc+0x474/0x56f
 ? drm_mode_getcrtc+0x155/0x155
 drm_ioctl_kernel+0x6c/0xa8
 drm_ioctl+0x267/0x353
 ? drm_mode_getcrtc+0x155/0x155
 amdgpu_drm_ioctl+0x4f/0x7f
 vfs_ioctl+0x21/0x2f
 do_vfs_ioctl+0x4c4/0x4e7
 ? security_file_ioctl+0x3b/0x4f
 SyS_ioctl+0x57/0x79
 do_syscall_64+0x64/0x72
 entry_SYSCALL_64_after_hwframe+0x3d/0xa2

V2: Added stack trace in commit message.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index bfd98f0..da4558c 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1221,7 +1221,7 @@ static int amdgpu_atom_execute_table_locked(struct 
atom_context *ctx, int index,
ectx.abort = false;
ectx.last_jump = 0;
if (ws)
-   ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
+   ectx.ws = kzalloc(4 * ws, GFP_ATOMIC);
else
ectx.ws = NULL;
 
-- 
2.7.4

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[PATCH] drm/amdgpu: replace mutex with spin_lock (V2)

[Shirish S]

mutex's lead to sleeps which should be avoided in
atomic context.
Hence this patch replaces it with the spin_locks.

Below is the stack trace:

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:**
in_atomic(): 1, irqs_disabled(): 1, pid: 89, name: kworker/u4:3
CPU: 1 PID: 89 Comm: kworker/u4:3 Tainted: GW   4.14.43 #8
Workqueue: events_unbound commit_work
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 mutex_lock+0x20/0x42
 amdgpu_atom_execute_table+0x26/0x72
 enable_disp_power_gating_v2_1+0x85/0xae
 dce110_enable_display_power_gating+0x83/0x1b1
 dce110_power_down_fe+0x4a/0x6d
 dc_post_update_surfaces_to_stream+0x59/0x87
 amdgpu_dm_do_flip+0x239/0x298
 amdgpu_dm_commit_planes.isra.23+0x379/0x54b
 ? drm_calc_timestamping_constants+0x14b/0x15c
 amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 process_one_work+0x1b0/0x314
 worker_thread+0x1cb/0x2c1
 ? create_worker+0x1da/0x1da
 kthread+0x156/0x15e
 ? kthread_flush_work+0xea/0xea
 ret_from_fork+0x22/0x40

V2: Added stack trace in commit message.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/atom.c| 4 ++--
 drivers/gpu/drm/amd/amdgpu/atom.h| 3 ++-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index bf872f6..ba3d4b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -2033,7 +2033,7 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
return -ENOMEM;
}
 
-   mutex_init(>mode_info.atom_context->mutex);
+   spin_lock_init(>mode_info.atom_context->lock);
if (adev->is_atom_fw) {
amdgpu_atomfirmware_scratch_regs_init(adev);
amdgpu_atomfirmware_allocate_fb_scratch(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 69500a8..bfd98f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1261,7 +1261,7 @@ int amdgpu_atom_execute_table(struct atom_context *ctx, 
int index, uint32_t * pa
 {
int r;
 
-   mutex_lock(>mutex);
+   spin_lock(>lock);
/* reset data block */
ctx->data_block = 0;
/* reset reg block */
@@ -1274,7 +1274,7 @@ int amdgpu_atom_execute_table(struct atom_context *ctx, 
int index, uint32_t * pa
ctx->divmul[0] = 0;
ctx->divmul[1] = 0;
r = amdgpu_atom_execute_table_locked(ctx, index, params);
-   mutex_unlock(>mutex);
+   spin_unlock(>lock);
return r;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h 
b/drivers/gpu/drm/amd/amdgpu/atom.h
index a391709..54063e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -26,6 +26,7 @@
 #define ATOM_H
 
 #include 
+#include 
 #include 
 
 #define ATOM_BIOS_MAGIC0xAA55
@@ -125,7 +126,7 @@ struct card_info {
 
 struct atom_context {
struct card_info *card;
-   struct mutex mutex;
+   spinlock_t lock;
void *bios;
uint32_t cmd_table, data_table;
uint16_t *iio;
-- 
2.7.4

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[PATCH] drm/amdgpu/pp: replace mutex with spin_lock (V2)

[Shirish S]

This patch replaces usage of mutex with spin_lock
to avoid sleep in atomic context.

Below is the stack trace:

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:**
in_atomic(): 1, irqs_disabled(): 1, pid: 5, name: kworker/u4:0
CPU: 1 PID: 5 Comm: kworker/u4:0 Tainted: GW   4.14.43 #9
Workqueue: events_unbound commit_work
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 mutex_lock+0x20/0x42
 amd_powerplay_display_configuration_change+0x32/0x51
 dm_pp_apply_display_requirements+0x10b/0x118
 dce110_set_bandwidth+0x1a1/0x1b5
 dc_commit_updates_for_stream+0x14c/0x4cf
 ? amdgpu_get_crtc_scanoutpos+0x82/0x16b
 amdgpu_dm_do_flip+0x239/0x298
 amdgpu_dm_commit_planes.isra.23+0x379/0x54b
 ? drm_calc_timestamping_constants+0x14b/0x15c
 amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 process_one_work+0x1b0/0x314
 worker_thread+0x1cb/0x2c1
 ? create_worker+0x1da/0x1da
 kthread+0x156/0x15e
 ? kthread_flush_work+0xea/0xea
 ret_from_fork+0x22/0x40

V2: Added stack trace in the commit message.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 152 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   2 +-
 2 files changed, 77 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index b493369..2d9c120 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -183,10 +183,10 @@ static int pp_late_init(void *handle)
int ret;
 
if (hwmgr && hwmgr->pm_en) {
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
hwmgr_handle_task(hwmgr,
AMD_PP_TASK_COMPLETE_INIT, NULL);
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
}
if (adev->pm.smu_prv_buffer_size != 0)
pp_reserve_vram_for_smu(adev);
@@ -375,11 +375,11 @@ static int pp_dpm_force_performance_level(void *handle,
if (level == hwmgr->dpm_level)
return 0;
 
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
pp_dpm_en_umd_pstate(hwmgr, );
hwmgr->request_dpm_level = level;
hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
 
return 0;
 }
@@ -393,9 +393,9 @@ static enum amd_dpm_forced_level 
pp_dpm_get_performance_level(
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
 
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
level = hwmgr->dpm_level;
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
return level;
 }
 
@@ -411,9 +411,9 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
pr_info("%s was not implemented.\n", __func__);
return 0;
}
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
return clk;
 }
 
@@ -429,9 +429,9 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
pr_info("%s was not implemented.\n", __func__);
return 0;
}
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
return clk;
 }
 
@@ -446,9 +446,9 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
pr_info("%s was not implemented.\n", __func__);
return;
}
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
 }
 
 static void pp_dpm_powergate_uvd(void *handle, bool gate)
@@ -462,9 +462,9 @@ static void pp_dpm_powergate_uvd(void *handle, bool gate)
pr_info("%s was not implemented.\n", __func__);
return;
}
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
 }
 
 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
@@ -476,9 +476,9 @@ static int pp_dpm_dispatch_tasks(void *handle, enum 
amd_pp_task task_id,
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
 
-   mutex_lock(>smu_lock);
+   spin_lock(>smu_lock);
ret = hwmgr_handle_task(hwmgr, task_id, user_state);
-   mutex_unlock(>smu_lock);
+   spin_unlock(>smu_lock);
 
return ret;
 }
@@ -492,7 +492,7 @@ static enum amd_pm_state_type 
pp_dpm_get_current_power_state(void *handle)
if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
 

[PATCH] drm/amdgpu: avoid sleep while executing atombios table (V2)

[Shirish S]

This patch replaces kzalloc's flag from GFP_KERNEL to
GFP_ATOMIC to avoid sleeping in atomic context.

Below is the stack trace:

BUG: sleeping function called from invalid context at mm/slab.h:***
in_atomic(): 1, irqs_disabled(): 0, pid: 1137, name: DrmThread
CPU: 1 PID: 1137 Comm: DrmThread Tainted: GW   4.14.43 #10
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 __kmalloc+0x76/0x126
 amdgpu_atom_execute_table_locked+0xfc/0x285
 amdgpu_atom_execute_table+0x5d/0x72
 transmitter_control_v1_5+0xef/0x11a
 hwss_edp_backlight_control+0x132/0x151
 dce110_disable_stream+0x133/0x16e
 core_link_disable_stream+0x1c5/0x23b
 dce110_reset_hw_ctx_wrap+0xb4/0x1aa
 dce110_apply_ctx_to_hw+0x4e/0x6da
 ? generic_reg_get+0x1f/0x33
 dc_commit_state+0x33f/0x3d2
 amdgpu_dm_atomic_commit_tail+0x2cf/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 drm_atomic_helper_commit+0xdc/0xf9
 drm_atomic_helper_set_config+0x5c/0x76
 __drm_mode_set_config_internal+0x64/0x105
 drm_mode_setcrtc+0x474/0x56f
 ? drm_mode_getcrtc+0x155/0x155
 drm_ioctl_kernel+0x6c/0xa8
 drm_ioctl+0x267/0x353
 ? drm_mode_getcrtc+0x155/0x155
 amdgpu_drm_ioctl+0x4f/0x7f
 vfs_ioctl+0x21/0x2f
 do_vfs_ioctl+0x4c4/0x4e7
 ? security_file_ioctl+0x3b/0x4f
 SyS_ioctl+0x57/0x79
 do_syscall_64+0x64/0x72
 entry_SYSCALL_64_after_hwframe+0x3d/0xa2

V2: Added stack trace in commit message.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index bfd98f0..da4558c 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1221,7 +1221,7 @@ static int amdgpu_atom_execute_table_locked(struct 
atom_context *ctx, int index,
ectx.abort = false;
ectx.last_jump = 0;
if (ws)
-   ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
+   ectx.ws = kzalloc(4 * ws, GFP_ATOMIC);
else
ectx.ws = NULL;
 
-- 
2.7.4

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[PATCH] drm/amd/display: avoid sleeping in atomic context while creating new state (V2)

[Shirish S]

This patch fixes the warning messages that are caused due to calling
sleep in atomic context as below:

BUG: sleeping function called from invalid context at mm/slab.h:419
in_atomic(): 1, irqs_disabled(): 1, pid: 5, name: kworker/u4:0
CPU: 1 PID: 5 Comm: kworker/u4:0 Tainted: GW   4.14.35 #941
Workqueue: events_unbound commit_work
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 kmem_cache_alloc_trace+0x41/0xea
 dc_create_state+0x1f/0x30
 dc_commit_updates_for_stream+0x73/0x4cf
 ? amdgpu_get_crtc_scanoutpos+0x82/0x16b
 amdgpu_dm_do_flip+0x239/0x298
 amdgpu_dm_commit_planes.isra.23+0x379/0x54b
 ? dc_commit_state+0x3da/0x404
 amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 process_one_work+0x1b0/0x314
 worker_thread+0x1cb/0x2c1
 ? create_worker+0x1da/0x1da
 kthread+0x156/0x15e
 ? kthread_flush_work+0xea/0xea
 ret_from_fork+0x22/0x40

V2: fix applicable only to dc_create_state() and not dc_create().

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c88f661..839e3f6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -953,7 +953,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 struct dc_state *dc_create_state(void)
 {
struct dc_state *context = kzalloc(sizeof(struct dc_state),
-  GFP_KERNEL);
+  GFP_ATOMIC);
 
if (!context)
return NULL;
-- 
2.7.4

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Re: [PATCH] drm/amd/display: avoid sleeping in atomic context while creating new context or state

[S, Shirish]

On 5/30/2018 9:33 PM, Harry Wentland wrote:

On 2018-05-30 06:17 AM, Shirish S wrote:

This patch fixes the warning messages that are caused due to calling
sleep in atomic context as below:

BUG: sleeping function called from invalid context at mm/slab.h:419
in_atomic(): 1, irqs_disabled(): 1, pid: 5, name: kworker/u4:0
CPU: 1 PID: 5 Comm: kworker/u4:0 Tainted: GW   4.14.35 #941
Workqueue: events_unbound commit_work
Call Trace:
  dump_stack+0x4d/0x63
  ___might_sleep+0x11f/0x12e
  kmem_cache_alloc_trace+0x41/0xea
  dc_create_state+0x1f/0x30
  dc_commit_updates_for_stream+0x73/0x4cf
  ? amdgpu_get_crtc_scanoutpos+0x82/0x16b
  amdgpu_dm_do_flip+0x239/0x298
  amdgpu_dm_commit_planes.isra.23+0x379/0x54b
  ? dc_commit_state+0x3da/0x404
  amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
  ? wait_for_common+0x5b/0x69
  commit_tail+0x42/0x64
  process_one_work+0x1b0/0x314
  worker_thread+0x1cb/0x2c1
  ? create_worker+0x1da/0x1da
  kthread+0x156/0x15e
  ? kthread_flush_work+0xea/0xea
  ret_from_fork+0x22/0x40

Signed-off-by: Shirish S 
---
  drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 33149ed..d62206f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -588,7 +588,7 @@ static void disable_dangling_plane(struct dc *dc, struct 
dc_state *context)
  
  struct dc *dc_create(const struct dc_init_data *init_params)

   {
-   struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
+   struct dc *dc = kzalloc(sizeof(*dc), GFP_ATOMIC);

Are you sure this one can be called in atomic_context?

My bad, you are right, this is not required.
I have re-spun the patch as V2 with the GFP_ATOMIC applied only to 
dc_create_state.

Thanks & Regards,
Shirish S

If so then everything in consstruct() would also need GFP_ATOMIC.

Harry


unsigned int full_pipe_count;
  
  	if (NULL == dc)

@@ -937,7 +937,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
  struct dc_state *dc_create_state(void)
  {
struct dc_state *context = kzalloc(sizeof(struct dc_state),
-  GFP_KERNEL);
+  GFP_ATOMIC);
  
  	if (!context)

return NULL;



--
Regards,
Shirish S

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Re: [PATCH] drm/amdgpu: replace mutex with spin_lock

[S, Shirish]

On 5/30/2018 9:10 PM, Christian König wrote:
Keep in mind that under SRIOV you can read registers while in atomic 
context, e.g. while holding a spinlock.


Please double check if that won't bite us.

Apart from that the change looks good to me,

Thanks Christian, i verified boot, s3, s5 on Stoney with this patch.
Have re-spun V2 which has the exact trace in which scenario this BUG is hit.
Regards,
Shirish S

Christian.

Am 30.05.2018 um 12:19 schrieb Shirish S:

mutex's lead to sleeps which should be avoided in
atomic context.
Hence this patch replaces it with the spin_locks.

Signed-off-by: Shirish S 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +-
  drivers/gpu/drm/amd/amdgpu/atom.c    | 4 ++--
  drivers/gpu/drm/amd/amdgpu/atom.h    | 3 ++-
  3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

index bf872f6..ba3d4b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -2033,7 +2033,7 @@ int amdgpu_atombios_init(struct amdgpu_device 
*adev)

  return -ENOMEM;
  }
  - mutex_init(>mode_info.atom_context->mutex);
+ spin_lock_init(>mode_info.atom_context->lock);
  if (adev->is_atom_fw) {
  amdgpu_atomfirmware_scratch_regs_init(adev);
  amdgpu_atomfirmware_allocate_fb_scratch(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c

index 69500a8..bfd98f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1261,7 +1261,7 @@ int amdgpu_atom_execute_table(struct 
atom_context *ctx, int index, uint32_t * pa

  {
  int r;
  -    mutex_lock(>mutex);
+    spin_lock(>lock);
  /* reset data block */
  ctx->data_block = 0;
  /* reset reg block */
@@ -1274,7 +1274,7 @@ int amdgpu_atom_execute_table(struct 
atom_context *ctx, int index, uint32_t * pa

  ctx->divmul[0] = 0;
  ctx->divmul[1] = 0;
  r = amdgpu_atom_execute_table_locked(ctx, index, params);
-    mutex_unlock(>mutex);
+    spin_unlock(>lock);
  return r;
  }
  diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h 
b/drivers/gpu/drm/amd/amdgpu/atom.h

index a391709..cdfb0d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -26,6 +26,7 @@
  #define ATOM_H
    #include 
+#include 
  #include 
    #define ATOM_BIOS_MAGIC    0xAA55
@@ -125,7 +126,7 @@ struct card_info {
    struct atom_context {
  struct card_info *card;
-    struct mutex mutex;
+    spinlock_t lock;
  void *bios;
  uint32_t cmd_table, data_table;
  uint16_t *iio;




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Shirish S

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Re: [PATCH] drm/amdgpu: replace mutex with spin_lock

[S, Shirish]

On 5/30/2018 8:51 PM, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Shirish S
Sent: Wednesday, May 30, 2018 6:20 AM
To: amd-gfx@lists.freedesktop.org; Wentland, Harry
; Zhu, Rex 
Cc: S, Shirish 
Subject: [PATCH] drm/amdgpu: replace mutex with spin_lock

mutex's lead to sleeps which should be avoided in atomic context.
Hence this patch replaces it with the spin_locks.

Signed-off-by: Shirish S 

Does this actually fix a bug or is it just to be safe?  Do actually call atom 
command tables in an atomic context?
I have re-spun V2 patch, with the stack trace so that you can see the 
path taken.


For reference below is the trace:

BUG: sleeping function called from invalid context at 
kernel/locking/mutex.c:238

in_atomic(): 1, irqs_disabled(): 1, pid: 89, name: kworker/u4:3
CPU: 1 PID: 89 Comm: kworker/u4:3 Tainted: G    W 4.14.43 #8
Workqueue: events_unbound commit_work
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 mutex_lock+0x20/0x42
 amdgpu_atom_execute_table+0x26/0x72
 enable_disp_power_gating_v2_1+0x85/0xae
 dce110_enable_display_power_gating+0x83/0x1b1
 dce110_power_down_fe+0x4a/0x6d
 dc_post_update_surfaces_to_stream+0x59/0x87
 amdgpu_dm_do_flip+0x239/0x298
 amdgpu_dm_commit_planes.isra.23+0x379/0x54b
 ? drm_calc_timestamping_constants+0x14b/0x15c
 amdgpu_dm_atomic_commit_tail+0x4fc/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 process_one_work+0x1b0/0x314
 worker_thread+0x1cb/0x2c1
 ? create_worker+0x1da/0x1da
 kthread+0x156/0x15e
 ? kthread_flush_work+0xea/0xea
 ret_from_fork+0x22/0x40

Its caused when a BUG hit in the kernel.

Thanks & Regards,
Shirish S

Alex


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +-
  drivers/gpu/drm/amd/amdgpu/atom.c| 4 ++--
  drivers/gpu/drm/amd/amdgpu/atom.h| 3 ++-
  3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index bf872f6..ba3d4b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -2033,7 +2033,7 @@ int amdgpu_atombios_init(struct amdgpu_device
*adev)
return -ENOMEM;
}

-   mutex_init(>mode_info.atom_context->mutex);
+   spin_lock_init(>mode_info.atom_context->lock);
if (adev->is_atom_fw) {
amdgpu_atomfirmware_scratch_regs_init(adev);
amdgpu_atomfirmware_allocate_fb_scratch(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 69500a8..bfd98f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1261,7 +1261,7 @@ int amdgpu_atom_execute_table(struct
atom_context *ctx, int index, uint32_t * pa  {
int r;

-   mutex_lock(>mutex);
+   spin_lock(>lock);
/* reset data block */
ctx->data_block = 0;
/* reset reg block */
@@ -1274,7 +1274,7 @@ int amdgpu_atom_execute_table(struct
atom_context *ctx, int index, uint32_t * pa
ctx->divmul[0] = 0;
ctx->divmul[1] = 0;
r = amdgpu_atom_execute_table_locked(ctx, index, params);
-   mutex_unlock(>mutex);
+   spin_unlock(>lock);
return r;
  }

diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h
b/drivers/gpu/drm/amd/amdgpu/atom.h
index a391709..cdfb0d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -26,6 +26,7 @@
  #define ATOM_H

  #include 
+#include 
  #include 

  #define ATOM_BIOS_MAGIC   0xAA55
@@ -125,7 +126,7 @@ struct card_info {

  struct atom_context {
struct card_info *card;
-   struct mutex mutex;
+   spinlock_t lock;
void *bios;
uint32_t cmd_table, data_table;
uint16_t *iio;
--
2.7.4

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Re: [PATCH] drm/amdgpu: avoid sleep while executing atombios table

[S, Shirish]

On 5/30/2018 8:51 PM, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Shirish S
Sent: Wednesday, May 30, 2018 6:19 AM
To: amd-gfx@lists.freedesktop.org; Wentland, Harry
; Zhu, Rex 
Cc: S, Shirish 
Subject: [PATCH] drm/amdgpu: avoid sleep while executing atombios table

This patch replaces kzalloc's flag from GFP_KERNEL to GFP_ATOMIC to avoid
sleeping in atomic context.

Signed-off-by: Shirish S 

Does this actually fix a bug or is it just to be safe.  Do actually call atom 
command tables in an atomic context?
I have re-spun V2 patch, with the stack trace so that you can see the 
path taken.


For reference below is the trace:

BUG: sleeping function called from invalid context at mm/slab.h:419
in_atomic(): 1, irqs_disabled(): 0, pid: 1137, name: DrmThread
CPU: 1 PID: 1137 Comm: DrmThread Tainted: G    W   4.14.43 #10
Call Trace:
 dump_stack+0x4d/0x63
 ___might_sleep+0x11f/0x12e
 __kmalloc+0x76/0x126
 amdgpu_atom_execute_table_locked+0xfc/0x285
 amdgpu_atom_execute_table+0x5d/0x72
 transmitter_control_v1_5+0xef/0x11a
 hwss_edp_backlight_control+0x132/0x151
 dce110_disable_stream+0x133/0x16e
 core_link_disable_stream+0x1c5/0x23b
 dce110_reset_hw_ctx_wrap+0xb4/0x1aa
 dce110_apply_ctx_to_hw+0x4e/0x6da
 ? generic_reg_get+0x1f/0x33
 dc_commit_state+0x33f/0x3d2
 amdgpu_dm_atomic_commit_tail+0x2cf/0x5d2
 ? wait_for_common+0x5b/0x69
 commit_tail+0x42/0x64
 drm_atomic_helper_commit+0xdc/0xf9
 drm_atomic_helper_set_config+0x5c/0x76
 __drm_mode_set_config_internal+0x64/0x105

I see it on Stoney when the system's display turns off while entering 
idle-suspend.


Its caused when a BUG hit in the kernel.

Thanks & Regards,
Shirish S

Alex


---
  drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu/drm/amd/amdgpu/atom.c
index bfd98f0..da4558c 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1221,7 +1221,7 @@ static int
amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index,
ectx.abort = false;
ectx.last_jump = 0;
if (ws)
-   ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
+   ectx.ws = kzalloc(4 * ws, GFP_ATOMIC);
else
ectx.ws = NULL;

--
2.7.4

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Re: [PATCH 1/2] drm/scheduler: Avoid using wait_event_killable for dying process.

[Christian König]

Am 30.05.2018 um 21:54 schrieb Andrey Grodzovsky:

Dying process might be blocked from receiving any more signals
so avoid using it.

Also retire enity->fini_status and just check the SW queue,
if it's not empty do the fallback cleanup.

Also handle entity->last_scheduled == NULL use case which
happens when HW ring is already hangged whem a  new entity
tried to enqeue jobs.

Signed-off-by: Andrey Grodzovsky 


Would be nice to have to split that patch up further, but not sure if 
that is actually doable.


Additional to that a few more nitpicks below.


---
  drivers/gpu/drm/scheduler/gpu_scheduler.c | 47 ++-
  include/drm/gpu_scheduler.h   |  1 -
  2 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/scheduler/gpu_scheduler.c
index 44d4807..4d038f9 100644
--- a/drivers/gpu/drm/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
@@ -135,7 +135,6 @@ int drm_sched_entity_init(struct drm_gpu_scheduler *sched,
entity->rq = rq;
entity->sched = sched;
entity->guilty = guilty;
-   entity->fini_status = 0;
entity->last_scheduled = NULL;
  
  	spin_lock_init(>rq_lock);

@@ -173,7 +172,8 @@ static bool drm_sched_entity_is_initialized(struct 
drm_gpu_scheduler *sched,
  static bool drm_sched_entity_is_idle(struct drm_sched_entity *entity)
  {
rmb();
-   if (spsc_queue_peek(>job_queue) == NULL)
+
+   if (entity->rq == NULL || spsc_queue_peek(>job_queue) == NULL)


Usual kernel coding style is more to use "!entity->rq" instead of 
"entity->rq == NULL".



return true;
  
  	return false;

@@ -227,12 +227,16 @@ void drm_sched_entity_do_release(struct drm_gpu_scheduler 
*sched,
 * The client will not queue more IBs during this fini, consume existing
 * queued IBs or discard them on SIGKILL
*/
-   if ((current->flags & PF_SIGNALED) && current->exit_code == SIGKILL)
-   entity->fini_status = -ERESTARTSYS;
+   if ((current->flags & PF_EXITING))
+   wait_event_timeout(sched->job_scheduled,
+   drm_sched_entity_is_idle(entity), 
msecs_to_jiffies(1000));


Mhm, making the timeout a parameter or at least use a define would be 
nice to have.


Additional to that it might be a good idea to return the remaining 
timeout and use that as parameter for the next call.


E.g. this way when we need to cleanup multiple queues we don't wait for 
1000 ms each, but rather only 1000 ms in total.



else
-   entity->fini_status = wait_event_killable(sched->job_scheduled,
-   drm_sched_entity_is_idle(entity));
-   drm_sched_entity_set_rq(entity, NULL);
+   wait_event_killable(sched->job_scheduled, 
drm_sched_entity_is_idle(entity));
+
+
+   /* For killed process disable any more IBs enqueue right now */
+   if ((current->flags & PF_EXITING) && (current->exit_code == SIGKILL))
+   drm_sched_entity_set_rq(entity, NULL);
  }
  EXPORT_SYMBOL(drm_sched_entity_do_release);
  
@@ -247,7 +251,13 @@ EXPORT_SYMBOL(drm_sched_entity_do_release);

  void drm_sched_entity_cleanup(struct drm_gpu_scheduler *sched,
   struct drm_sched_entity *entity)
  {
-   if (entity->fini_status) {
+
+   drm_sched_entity_set_rq(entity, NULL);
+
+   /* Consumption of existing IBs wasn't completed. Forcefully
+* remove them here.
+*/
+   if (spsc_queue_peek(>job_queue)) {
struct drm_sched_job *job;
int r;
  
@@ -267,12 +277,22 @@ void drm_sched_entity_cleanup(struct drm_gpu_scheduler *sched,

struct drm_sched_fence *s_fence = job->s_fence;
drm_sched_fence_scheduled(s_fence);
dma_fence_set_error(_fence->finished, -ESRCH);
-   r = dma_fence_add_callback(entity->last_scheduled, 
>finish_cb,
-   
drm_sched_entity_kill_jobs_cb);
-   if (r == -ENOENT)
+
+   /*
+* When pipe is hanged by older entity, new entity might
+* not even have chance to submit it's first job to HW
+* and so entity->last_scheduled will remain NULL
+*/
+   if (!entity->last_scheduled)
drm_sched_entity_kill_jobs_cb(NULL, 
>finish_cb);
-   else if (r)
-   DRM_ERROR("fence add callback failed (%d)\n", 
r);
+   else {


Coding style nit pick when one side of an else has { or } the other side 
should have it as well.



+   r = dma_fence_add_callback(entity->last_scheduled, 
>finish_cb,
+