There isn't ucode when executing INVOKE command, so current code can't
check the failure of INVOKE command.
Remove the ucode check.
Signed-off-by: Xiangliang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gp
xGMI session id should get from response buffer, correct it.
Signed-off-by: Xiangliang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8fab0d6..2f126ea7
The new PSP SOS firmware can support both A0 and A1.
Change-Id: I9bf85eb77b183a4403667c77e291e32689aed0af
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgp
From: James Zhu
[ Upstream commit 0a9b89b2e2e7b6d90f81ddc47e489be1043e01b1 ]
Replace vcn_v1_0_stop with vcn_v1_0_set_powergating_state during suspend,
to keep adev->vcn.cur_state update. It will fix VCN S3 hung issue.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
From: Evan Quan
[ Upstream commit 10cb3e6b63bf4266a5198813526fdd7259ffb8be ]
For display config change event only, pre-display config settings are
needed.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/powerpla
From: Christian König
[ Upstream commit 3bfa8897e4d08f822d1d58cf6cbbffbccef82e08 ]
Instead of delaying that to the first query. Otherwise we could try to use the
SDMA for VM updates before the IB tests are done.
Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
Reviewed-by: Junwei Zha
From: Roman Li
[ Upstream commit c679fd55b1ba903c2a770127edbf6aef6f27 ]
[Why]
More than 4x4K didn't lightup on Vega20 due to low dcfclk value.
Powerplay expects valid min requirement for dcfclk from DC.
[How]
Update min_dcfclock_khz based on min_engine_clock value.
v2: backport to 4.20 (Al
Fixed in the new patch which was just sent out.
Regards,
Evan
> -Original Message-
> From: Christian König
> Sent: 2018年12月12日 16:26
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/4] drm/amdgpu: use the idle engine 0/1 for page ring
> 0/1
>
> Am 12.12.18 um 07:5
Page queue is supported on Vega20 with SDMA firmware
123 onwards.
Change-Id: I78d2c4a7ad9d200d89177fae2ad6073955e6bd8b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
Vega20 uses ring id 1 for page queues EOP irq while previous
ASICs take ring id 3.
Change-Id: Id837fa934ab4a60f0360a33216413a8fc9987c56
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/am
We need new invalidation engine layout due to new SDMA page
queues added.
Change-Id: I2f3861689bffb9828c9eae744a7a0de4963ac2b6
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 47 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 10 ++
2 files changed,
As two more SDMA page queue rings are added on Vega20.
Change-Id: I8a3d8fbc924f7c24aaebf17b3f329a4a38fe5a56
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/driver
On Thu, 13 Dec 2018 at 07:13, Alex Deucher wrote:
>
> Hi Dave,
>
> Updates for 4.21:
> - Powerplay updates for newer polaris variants
> - Add cursor plane update fast path
> - Enable gpu reset by default on CI parts
> - Fix config with KFD/HSA not enabled
> - Misc bug fixes
>
Either this or the p
Hi Dave,
Updates for 4.21:
- Powerplay updates for newer polaris variants
- Add cursor plane update fast path
- Enable gpu reset by default on CI parts
- Fix config with KFD/HSA not enabled
- Misc bug fixes
The following changes since commit 22666cc1481ae3814d9c7718418cc4a3aa7d90c3:
drm/amdgpu
Hi Dave,
Fixes for 4.20:
- Stability fixes for new polaris variants (e.g., RX590)
- New vega pci ids
- Vega20 smu fix
- Ctx locking fix
The following changes since commit e594a5e349ddbfdaca1951bb3f8d72f3f1660d73:
drm/ast: Fix connector leak during driver unload (2018-12-06 14:12:02 +1000)
are
Reset decode r/w point after unset jpeg/non_jpeg pause mode to address
a hardware bug.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn
Under Dynamic Power Gate mode, UVD_STATUS needn't be checked.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 4f83520..775
Scan enc/jpeg fences to init dpg pause new state in begin use.
It will help set dpg mode to desire state actively.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
For robustness, it is safe to wait for all vcn rings finish
before switching dpg mode.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu
Always check all vcn ring status during dpg mode stop, it will help
identify which vcn ring may cause the issue.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/am
It is a bug fix.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 7752043..5df6ea9 100644
--- a/drivers/gpu/drm/amd/amdgpu/
> > From: Ken Chalmers
> >
> > [Why]
> > Users would like more accurate pixel clocks, especially for fractional
> > "TV" frame rates like 59.94 Hz.
> >
> > [How]
> > Store and communicate pixel clocks with 100 Hz accuracy from
> > dc_crtc_timing through to BIOS command table setpixelclock call.
>
On 2018-12-12 3:58 p.m., Kazlauskas, Nicholas wrote:
> On 12/12/18 9:40 AM, Michel Dänzer wrote:
>> On 2018-12-12 3:17 p.m., Kazlauskas, Nicholas wrote:
>>> On 12/12/18 9:10 AM, Michel Dänzer wrote:
On 2018-12-12 3:04 p.m., Nicholas Kazlauskas wrote:
> [Why]
> The cursor calculations i
On 12/12/18 10:18 AM, Alex Deucher wrote:
> On Wed, Dec 12, 2018 at 9:04 AM Nicholas Kazlauskas
> wrote:
>>
>> [Why]
>> The cursor calculations in amdgpu_dm incorrectly assume that the
>> cursor hotspot is always (0, 0) and don't respect the hot_x and hot_y
>> attributes that can be passed in via
On Wed, Dec 12, 2018 at 9:04 AM Nicholas Kazlauskas
wrote:
>
> [Why]
> The cursor calculations in amdgpu_dm incorrectly assume that the
> cursor hotspot is always (0, 0) and don't respect the hot_x and hot_y
> attributes that can be passed in via the drm_mode_cursor2_ioctl.
>
> The DC hotspot para
On 12/12/18 9:40 AM, Michel Dänzer wrote:
> On 2018-12-12 3:17 p.m., Kazlauskas, Nicholas wrote:
>> On 12/12/18 9:10 AM, Michel Dänzer wrote:
>>> On 2018-12-12 3:04 p.m., Nicholas Kazlauskas wrote:
[Why]
The cursor calculations in amdgpu_dm incorrectly assume that the
cursor hotspot
On 2018-12-12 3:17 p.m., Kazlauskas, Nicholas wrote:
> On 12/12/18 9:10 AM, Michel Dänzer wrote:
>> On 2018-12-12 3:04 p.m., Nicholas Kazlauskas wrote:
>>> [Why]
>>> The cursor calculations in amdgpu_dm incorrectly assume that the
>>> cursor hotspot is always (0, 0) and don't respect the hot_x and
On 12/12/18 9:10 AM, Michel Dänzer wrote:
> On 2018-12-12 3:04 p.m., Nicholas Kazlauskas wrote:
>> [Why]
>> The cursor calculations in amdgpu_dm incorrectly assume that the
>> cursor hotspot is always (0, 0) and don't respect the hot_x and hot_y
>> attributes that can be passed in via the drm_mode_
On 2018-12-12 3:04 p.m., Nicholas Kazlauskas wrote:
> [Why]
> The cursor calculations in amdgpu_dm incorrectly assume that the
> cursor hotspot is always (0, 0) and don't respect the hot_x and hot_y
> attributes that can be passed in via the drm_mode_cursor2_ioctl.
>
> The DC hotspot parameters ar
[Why]
The cursor calculations in amdgpu_dm incorrectly assume that the
cursor hotspot is always (0, 0) and don't respect the hot_x and hot_y
attributes that can be passed in via the drm_mode_cursor2_ioctl.
The DC hotspot parameters are also incorrectly used to offset the
cursor when it goes beyond
BTW, the problem I pointed out with drm_sched_entity_kill_jobs_cb is not
an issue with this patch set since it removes the cb from
s_fence->finished in general so we only free the job once - directly
from drm_sched_entity_kill_jobs_cb.
Andrey
On 12/11/2018 11:20 AM, Christian König wrote:
> Y
在 2018/12/12 20:24, Daniel Vetter 写道:
> On Wed, Dec 12, 2018 at 12:40 PM Zhou, David(ChunMing)
> wrote:
>> + Daniel Rakos and Jason Ekstrand.
>>
>> Below is the background, which is from Daniel R should be able to explain
>> that's why:
>> " ISVs, especially those coming from D3D12, are unsat
On Wed, Dec 12, 2018 at 12:40 PM Zhou, David(ChunMing)
wrote:
>
> + Daniel Rakos and Jason Ekstrand.
>
> Below is the background, which is from Daniel R should be able to explain
> that's why:
> " ISVs, especially those coming from D3D12, are unsatisfied with the behavior
> of the Vulkan semap
On Wed, Dec 12, 2018 at 1:00 PM Koenig, Christian
wrote:
>
> > Key point is that our Vulcan guys came back and said that this
> > wouldn't be sufficient, but I honestly don't fully understand why.
> > Hm, sounds like we really need those testscases (vk cts on top of mesa, igt)
> > so we can talk a
> Key point is that our Vulcan guys came back and said that this
> wouldn't be sufficient, but I honestly don't fully understand why.
> Hm, sounds like we really need those testscases (vk cts on top of mesa, igt)
> so we can talk about the exact corner cases we care about and why.
Yes, that's why I
+ Daniel Rakos and Jason Ekstrand.
Below is the background, which is from Daniel R should be able to explain
that's why:
" ISVs, especially those coming from D3D12, are unsatisfied with the behavior
of the Vulkan semaphores as they are unhappy with the fact that for every
single dependency t
On Wed, Dec 12, 2018 at 12:08 PM Koenig, Christian
wrote:
>
> Am 12.12.18 um 11:49 schrieb Daniel Vetter:
> > On Fri, Dec 07, 2018 at 11:54:15PM +0800, Chunming Zhou wrote:
> >> From: Christian König
> >>
> >> Use the dma_fence_chain object to create a timeline of fence objects
> >> instead of ju
Am 12.12.18 um 11:49 schrieb Daniel Vetter:
> On Fri, Dec 07, 2018 at 11:54:15PM +0800, Chunming Zhou wrote:
>> From: Christian König
>>
>> Use the dma_fence_chain object to create a timeline of fence objects
>> instead of just replacing the existing fence.
>>
>> v2: rebase and cleanup
>>
>> Signe
On Mon, Dec 10, 2018 at 02:40:25PM +0100, Benjamin Gaignard wrote:
> Le lun. 10 déc. 2018 à 12:10, Benjamin Gaignard
> a écrit :
> >
> > Le lun. 10 déc. 2018 à 11:24, Thierry Reding
> > a écrit :
> > >
> > > On Mon, Dec 10, 2018 at 11:11:33AM +0100, Daniel Vetter wrote:
> > > > Having the probe h
On Fri, Dec 07, 2018 at 11:54:15PM +0800, Chunming Zhou wrote:
> From: Christian König
>
> Use the dma_fence_chain object to create a timeline of fence objects
> instead of just replacing the existing fence.
>
> v2: rebase and cleanup
>
> Signed-off-by: Christian König
Somewhat jumping back i
This series reviewed by: Xiangliang Yu
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Wednesday, December 12, 2018 5:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH 1/2] drm/amdgpu/psp_v3_1: Get psp fw version through reading
register
If PSP FW
If PSP FW is running already, driver will not load PSP FW again and skip
it. So psp fw version is not correct if reading it from FW binary file,
need to get right version from register.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 5 -
1 file changed, 4 insertions(+)
Currently driver only psp v11 support vmr.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 20 +++-
3 files changed, 18 insertions(+), 15 deletions(-
Am 12.12.18 um 09:54 schrieb Emily Deng:
There is no need to access register such as mmSMC_IND_INDEX_11
and mmSMC_IND_DATA_11, PCIE_INDEX, PCIE_DATA through KIQ because
they are VF-copy.
Signed-off-by: Emily Deng
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vi.c | 18
There is no need to access register such as mmSMC_IND_INDEX_11
and mmSMC_IND_DATA_11, PCIE_INDEX, PCIE_DATA through KIQ because
they are VF-copy.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/vi.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/d
Am 12.12.18 um 07:54 schrieb Evan Quan:
We need new invalidation engine layout due to new SDMA page
queues added.
Change-Id: I2f3861689bffb9828c9eae744a7a0de4963ac2b6
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-
Am 11.12.18 um 23:57 schrieb sunpeng...@amd.com:
From: Ken Chalmers
[Why]
Users would like more accurate pixel clocks, especially for fractional
"TV" frame rates like 59.94 Hz.
[How]
Store and communicate pixel clocks with 100 Hz accuracy from
dc_crtc_timing through to BIOS command table setpi
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