Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: 2019年1月22日 2:59
> To: amd-gfx list
> Cc: Deucher, Alexander
> Subject: Re: [PATCH] drm/radeon: check if device is root before getting pci
> speed caps
>
> Ping?
>
> On Thu, Jan 17, 2019
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: 2019年1月22日 3:01
> To: amd-gfx list
> Cc: Deucher, Alexander
> Subject: Re: [PATCH] drm/amdgpu: Add missing power attribute to APU
> check
>
> Ping again?
>
> Alex
>
> On Tue, Jan 15,
Clang warns:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:866:5: warning:
'CONFIG_X86_64' is not defined, evaluates to 0 [-Wundef]
#if CONFIG_X86_64
^
1 warning generated.
Fixes: d1c234e2cd10 ("drm/amdkfd: Allow building KFD on ARM64 (v2)")
Signed-off-by: Nathan Chancellor
---
Resending
From: Marek Olšák
I'm not increasing the DRM version because GDS isn't totally without bugs yet.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 17
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17
Hi Daniel et al.
> >
> > Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy
> > kms drivers. Just removing it from all the atomic drivers caused lots of
> > fallout, I expect even more if you entirely remove the includes it has.
> > Maybe a todo, care to pls create that
On Mon, 21 Jan 2019 at 22:00, Grodzovsky, Andrey
wrote:
>
> + Harry
>
> Looks like this is happening during GPU reset due to job time out. I would
> first try to reproduce this just with a plain reset from sysfs.
> Mikhail, also please provide add2line for dce110_setup_audio_dto.isra.8+0x171
$
On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote:
>
> On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote:
> >> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote:
> >>> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote:
> On 2019-01-21 6:59
On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote:
> On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote:
>> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote:
>>> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote:
On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote:
> On Mon, 21 Jan 2019 at 18:55,
Ping again?
Alex
On Tue, Jan 15, 2019 at 11:32 AM Alex Deucher wrote:
>
> Ping?
>
> On Wed, Jan 9, 2019 at 10:23 PM Alex Deucher wrote:
> >
> > Add missing power_average to visible check for power
> > attributesi for APUs. Was missed before.
> >
> > Signed-off-by: Alex Deucher
> > ---
> >
Ping?
On Thu, Jan 17, 2019 at 2:44 PM Alex Deucher wrote:
>
> Check if the device is root rather before attempting to see what
> speeds the pcie port supports. Fixes a crash with pci passthrough
> in a VM.
>
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109366
> Signed-off-by: Alex
On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote:
>
> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote:
> >>
> >> On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote:
> >>> On Mon, 21 Jan 2019 at 18:55, Michel Dänzer wrote:
>
> On
On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote:
>
> On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 18:55, Michel Dänzer wrote:
> >>
> >> On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote:
> >>> On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig
> >>> wrote:
> >>>
>
On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote:
> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote:
>>
>> On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote:
>>> On Mon, 21 Jan 2019 at 18:55, Michel Dänzer wrote:
On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote:
> On Mon, 21 Jan 2019 at
On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote:
> On Mon, 21 Jan 2019 at 18:55, Michel Dänzer wrote:
>>
>> On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote:
>>> On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig wrote:
>>>
Until that happens we should just change the driver ifdefs to default
On Mon, 21 Jan 2019 at 17:35, Christoph Hellwig wrote:
>
> On Mon, Jan 21, 2019 at 05:30:00PM +0100, Ard Biesheuvel wrote:
> > > Until that happens we should just change the driver ifdefs to default
> > > the hacks to off and only enable them on setups where we 100%
> > > positively know that
On Mon, 21 Jan 2019 at 18:55, Michel Dänzer wrote:
>
> On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig wrote:
> >
> >> Until that happens we should just change the driver ifdefs to default
> >> the hacks to off and only enable them on setups
On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote:
> On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig wrote:
>
>> Until that happens we should just change the driver ifdefs to default
>> the hacks to off and only enable them on setups where we 100%
>> positively know that they actually work. And
+ Harry
Looks like this is happening during GPU reset due to job time out. I would
first try to reproduce this just with a plain reset from sysfs.
Mikhail, also please provide add2line for dce110_setup_audio_dto.isra.8+0x171
Andrey
On 01/20/2019 06:59 AM, Mikhail Gavrilov wrote:
Hi folks.
Yet
On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig wrote:
>
> On Mon, Jan 21, 2019 at 05:14:37PM +0100, Ard Biesheuvel wrote:
> > > I'll add big fat comments. But the fact that nothing is exported
> > > there should be a fairly big hint.
> > >
> >
> > I don't follow. How do other header files
On Mon, 21 Jan 2019 at 16:59, Christoph Hellwig wrote:
>
> On Mon, Jan 21, 2019 at 04:33:27PM +0100, Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 16:07, Christoph Hellwig wrote:
> > >
> > > > +#include
> > >
> > > This header is not for usage in device drivers, but purely for
> > >
On Mon, Jan 21, 2019 at 05:30:00PM +0100, Ard Biesheuvel wrote:
> > Until that happens we should just change the driver ifdefs to default
> > the hacks to off and only enable them on setups where we 100%
> > positively know that they actually work. And document that fact
> > in big fat comments.
On Mon, Jan 21, 2019 at 05:14:37PM +0100, Ard Biesheuvel wrote:
> > I'll add big fat comments. But the fact that nothing is exported
> > there should be a fairly big hint.
> >
>
> I don't follow. How do other header files 'export' things in a way
> that this header doesn't?
Well, I'll add
Series is:
Acked-by: Alex Deucher
From: amd-gfx on behalf of Evan Quan
Sent: Monday, January 21, 2019 4:46:07 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 2/2] drm/amd/powerplay: run btc before enabling all SMU features
BTC is needed
On Mon, Jan 21, 2019 at 04:33:27PM +0100, Ard Biesheuvel wrote:
> On Mon, 21 Jan 2019 at 16:07, Christoph Hellwig wrote:
> >
> > > +#include
> >
> > This header is not for usage in device drivers, but purely for
> > dma-mapping implementations!
> >
>
> Is that documented anywhere?
I'll add big
On Mon, 21 Jan 2019 at 16:07, Christoph Hellwig wrote:
>
> > +#include
>
> This header is not for usage in device drivers, but purely for
> dma-mapping implementations!
>
Is that documented anywhere?
> > +static inline bool drm_device_can_wc_memory(struct drm_device *ddev)
> > {
> > + if
On Mon, Jan 21, 2019 at 5:02 AM Evan Quan wrote:
>
> As the gfxclk for SMU11 can have at most 16 discrete levels.
>
> Change-Id: I0c6a8db8f40206a240286471c6f7b1fffef15ea2
> Signed-off-by: Evan Quan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 +-
> 1
> +#include
This header is not for usage in device drivers, but purely for
dma-mapping implementations!
> +static inline bool drm_device_can_wc_memory(struct drm_device *ddev)
> {
> + if (IS_ENABLED(CONFIG_PPC))
> + return IS_ENABLED(CONFIG_NOT_COHERENT_CACHE);
> + else if
Currently, the DRM code assumes that PCI devices are always cache
coherent for DMA, and that this can be selectively overridden for
some buffers using non-cached mappings on the CPU side and PCIe
NoSnoop transactions on the bus side.
Whether the NoSnoop part is implemented correctly is highly
Am 21.01.19 um 11:06 schrieb Ard Biesheuvel:
> Currently, the DRM code assumes that PCI devices are always cache
> coherent for DMA, and that this can be selectively overridden for
> some buffers using non-cached mappings on the CPU side and PCIe
> NoSnoop transactions on the bus side.
>
> Whether
As the gfxclk for SMU11 can have at most 16 discrete levels.
Change-Id: I0c6a8db8f40206a240286471c6f7b1fffef15ea2
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Am 21.01.19 um 05:35 schrieb Liu, Monk:
> Actually that's not so crazy at all. See the ATC uses the CPU page tables to
> provide parts of the virtual GPU address space.
So aperture 0->hole-start will be translated *not* by GMC9’s page table but
instead by CPU’s (or IOMMU ?) MMU table after ATC
The SOC clock needs also to fit the new performance level.
Change-Id: I24c5c4cdff11a4d2e0946b970ed950a4fc530b0a
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 37 +++
1 file changed, 37 insertions(+)
diff --git
BTC is needed before enabling all SMU features.
Change-Id: Ic717226528f4d09a58264524b2d8e67150a35da7
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
Reviewed-by: Christian König
Am 21.01.2019 07:57 schrieb "Xiao, Jack" :
Replace the last bool type parameter with a general flags parameter,
to make the last parameter be able to contain more information.
v2: drop setting need_ctx_switch = false
Signed-off-by: Jack Xiao
---
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Xiao, Jack
Sent: 2019年1月21日 14:57
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ; Koenig,
Christian
Cc: Xiao, Jack
Subject: [PATCH v2] drm/amdgpu: add flags to emit_ib interface v2
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Kenneth Feng
> Sent: 2019年1月21日 16:17
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth
> Subject: [PATCH] drm/amd/powerplay: OD setting fix on Vega10
>
> gfxclk for OD setting is limited to 1980M for
gfxclk for OD setting is limited to 1980M for non-acg
ASICs of Vega10
Signed-off-by: Kenneth Feng
---
.../amd/powerplay/hwmgr/vega10_processpptables.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git
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