Re: [PATCH 2/2] drm/amd/powerplay: enable MGPU fan boost feature on Vega10
On Tue, Jan 22, 2019 at 10:43 PM Evan Quan wrote:
>
> For those SKUs which support this feature only.
>
> Change-Id: I74de00204d93f951e04073e5c4c4ce9c0d34f662
> Signed-off-by: Evan Quan
Is there a minimum smu version number required to support this? Is it
safe to setup the structures and enable it if the using older smu fw?
With that clarified, the series is:
Reviewed-by: Alex Deucher
Alex
> ---
> .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 1 +
> .../drm/amd/powerplay/hwmgr/vega10_thermal.c | 37 +++
> .../drm/amd/powerplay/hwmgr/vega10_thermal.h | 1 +
> 3 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index f0ba4254361b..1a4c6467a36d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -5168,6 +5168,7 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
> .set_asic_baco_state = vega10_baco_set_state,
> .get_ppfeature_status = vega10_get_ppfeature_status,
> .set_ppfeature_status = vega10_set_ppfeature_status,
> + .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
> };
>
> int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> index 3f807d6c95ce..ba8763daa380 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> @@ -556,6 +556,43 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr
> *hwmgr)
> return ret;
> }
>
> +int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
> +{
> + struct vega10_hwmgr *data = hwmgr->backend;
> + PPTable_t *table = &(data->smc_state_table.pp_table);
> + int ret;
> +
> + if (!data->smu_features[GNLD_FAN_CONTROL].supported)
> + return 0;
> +
> + if (!hwmgr->thermal_controller.advanceFanControlParameters.
> + usMGpuThrottlingRPMLimit)
> + return 0;
> +
> + table->FanThrottlingRpm = hwmgr->thermal_controller.
> + advanceFanControlParameters.usMGpuThrottlingRPMLimit;
> +
> + ret = smum_smc_table_manager(hwmgr,
> + (uint8_t
> *)(&(data->smc_state_table.pp_table)),
> + PPTABLE, false);
> + if (ret) {
> + pr_info("Failed to update fan control table in pptable!");
> + return ret;
> + }
> +
> + ret = vega10_disable_fan_control_feature(hwmgr);
> + if (ret) {
> + pr_info("Attempt to disable SMC fan control feature failed!");
> + return ret;
> + }
> +
> + ret = vega10_enable_fan_control_feature(hwmgr);
> + if (ret)
> + pr_info("Attempt to enable SMC fan control feature failed!");
> +
> + return ret;
> +}
> +
> /**
> * Start the fan control on the SMC.
> * @paramhwmgr the address of the powerplay hardware manager.
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
> index 21e7c4dfa2ca..4a0ede7c1f07 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
> @@ -73,6 +73,7 @@ extern int vega10_thermal_disable_alert(struct pp_hwmgr
> *hwmgr);
> extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
> extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
> struct PP_TemperatureRange *range);
> +extern int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr);
>
>
> #endif
> --
> 2.20.1
>
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[PATCH 2/2] drm/amd/powerplay: enable MGPU fan boost feature on Vega10
For those SKUs which support this feature only.
Change-Id: I74de00204d93f951e04073e5c4c4ce9c0d34f662
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 1 +
.../drm/amd/powerplay/hwmgr/vega10_thermal.c | 37 +++
.../drm/amd/powerplay/hwmgr/vega10_thermal.h | 1 +
3 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f0ba4254361b..1a4c6467a36d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -5168,6 +5168,7 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.set_asic_baco_state = vega10_baco_set_state,
.get_ppfeature_status = vega10_get_ppfeature_status,
.set_ppfeature_status = vega10_set_ppfeature_status,
+ .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
};
int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index 3f807d6c95ce..ba8763daa380 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -556,6 +556,43 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
return ret;
}
+int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
+{
+ struct vega10_hwmgr *data = hwmgr->backend;
+ PPTable_t *table = &(data->smc_state_table.pp_table);
+ int ret;
+
+ if (!data->smu_features[GNLD_FAN_CONTROL].supported)
+ return 0;
+
+ if (!hwmgr->thermal_controller.advanceFanControlParameters.
+ usMGpuThrottlingRPMLimit)
+ return 0;
+
+ table->FanThrottlingRpm = hwmgr->thermal_controller.
+ advanceFanControlParameters.usMGpuThrottlingRPMLimit;
+
+ ret = smum_smc_table_manager(hwmgr,
+ (uint8_t *)(&(data->smc_state_table.pp_table)),
+ PPTABLE, false);
+ if (ret) {
+ pr_info("Failed to update fan control table in pptable!");
+ return ret;
+ }
+
+ ret = vega10_disable_fan_control_feature(hwmgr);
+ if (ret) {
+ pr_info("Attempt to disable SMC fan control feature failed!");
+ return ret;
+ }
+
+ ret = vega10_enable_fan_control_feature(hwmgr);
+ if (ret)
+ pr_info("Attempt to enable SMC fan control feature failed!");
+
+ return ret;
+}
+
/**
* Start the fan control on the SMC.
* @paramhwmgr the address of the powerplay hardware manager.
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
index 21e7c4dfa2ca..4a0ede7c1f07 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
@@ -73,6 +73,7 @@ extern int vega10_thermal_disable_alert(struct pp_hwmgr
*hwmgr);
extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range);
+extern int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr);
#endif
--
2.20.1
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[PATCH 1/2] drm/amd/powerplay: support Vega10 fan table V3
MGPU fan boost related parameter is added.
Change-Id: Iaa6c570373d81199a07028f275b083f459952254
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_pptable.h | 24 +
.../powerplay/hwmgr/vega10_processpptables.c | 50 ++-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
3 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
index b3e63003a789..c934e9612c1b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
@@ -282,6 +282,30 @@ typedef struct _ATOM_Vega10_Fan_Table_V2 {
UCHAR ucFanMaxRPM;
} ATOM_Vega10_Fan_Table_V2;
+typedef struct _ATOM_Vega10_Fan_Table_V3 {
+ UCHAR ucRevId;
+ USHORT usFanOutputSensitivity;
+ USHORT usFanAcousticLimitRpm;
+ USHORT usThrottlingRPM;
+ USHORT usTargetTemperature;
+ USHORT usMinimumPWMLimit;
+ USHORT usTargetGfxClk;
+ USHORT usFanGainEdge;
+ USHORT usFanGainHotspot;
+ USHORT usFanGainLiquid;
+ USHORT usFanGainVrVddc;
+ USHORT usFanGainVrMvdd;
+ USHORT usFanGainPlx;
+ USHORT usFanGainHbm;
+ UCHAR ucEnableZeroRPM;
+ USHORT usFanStopTemperature;
+ USHORT usFanStartTemperature;
+ UCHAR ucFanParameters;
+ UCHAR ucFanMinRPM;
+ UCHAR ucFanMaxRPM;
+ USHORT usMGpuThrottlingRPM;
+} ATOM_Vega10_Fan_Table_V3;
+
typedef struct _ATOM_Vega10_Thermal_Controller {
UCHAR ucRevId;
UCHAR ucType; /* one of ATOM_VEGA10_PP_THERMALCONTROLLER_*/
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index 99d596dc0e89..b6767d74dc85 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -123,6 +123,7 @@ static int init_thermal_controller(
const Vega10_PPTable_Generic_SubTable_Header *header;
const ATOM_Vega10_Fan_Table *fan_table_v1;
const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
+ const ATOM_Vega10_Fan_Table_V3 *fan_table_v3;
thermal_controller = (ATOM_Vega10_Thermal_Controller *)
(((unsigned long)powerplay_table) +
@@ -207,7 +208,7 @@ static int init_thermal_controller(
le16_to_cpu(fan_table_v1->usFanStopTemperature);
hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature
=
le16_to_cpu(fan_table_v1->usFanStartTemperature);
- } else if (header->ucRevId > 10) {
+ } else if (header->ucRevId == 0xb) {
fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
@@ -251,7 +252,54 @@ static int init_thermal_controller(
le16_to_cpu(fan_table_v2->usFanStopTemperature);
hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature
=
le16_to_cpu(fan_table_v2->usFanStartTemperature);
+ } else if (header->ucRevId > 0xb) {
+ fan_table_v3 = (ATOM_Vega10_Fan_Table_V3 *)header;
+
+
hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
+ fan_table_v3->ucFanParameters &
ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
+ hwmgr->thermal_controller.fanInfo.ulMinRPM =
fan_table_v3->ucFanMinRPM * 100UL;
+ hwmgr->thermal_controller.fanInfo.ulMaxRPM =
fan_table_v3->ucFanMaxRPM * 100UL;
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+
hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
+
le16_to_cpu(fan_table_v3->usFanOutputSensitivity);
+
hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
+ fan_table_v3->ucFanMaxRPM * 100UL;
+
hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
+ le16_to_cpu(fan_table_v3->usThrottlingRPM);
+
hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
=
+
le16_to_cpu(fan_table_v3->usFanAcousticLimitRpm);
+ hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
+ le16_to_cpu(fan_table_v3->usTargetTemperature);
+ hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
+ le16_to_cpu(fan_table_v3->usMinimumPWMLimit);
+
Re: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86
On Tue, 22 Jan 2019 at 21:56, Alex Deucher wrote: > > On Tue, Jan 22, 2019 at 4:19 AM Ard Biesheuvel > wrote: > > > > On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote: > > > > > > On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote: > > > > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote: > > > >> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote: > > > >>> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer > > > >>> wrote: > > > On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote: > > > > On Mon, 21 Jan 2019 at 18:55, Michel Dänzer > > > > wrote: > > > >> On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote: > > > >>> On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig > > > >>> wrote: > > > >>> > > > Until that happens we should just change the driver ifdefs to > > > default > > > the hacks to off and only enable them on setups where we 100% > > > positively know that they actually work. And document that fact > > > in big fat comments. > > > >>> > > > >>> Well, as I mentioned in my commit log as well, if we default to > > > >>> off > > > >>> unless CONFIG_X86, we may break working setups on MIPS and Power > > > >>> where > > > >>> the device is in fact non-cache coherent, and relies on this > > > >>> 'optimization' to get things working. > > > >> > > > >> FWIW, the amdgpu driver doesn't rely on non-snooped transfers for > > > >> correct basic operation (the scenario Christian brought up is a > > > >> very > > > >> specialized use-case), so that shouldn't be an issue. > > > > > > > > The point is that this is only true for x86. > > > > > > > > On other architectures, the use of non-cached mappings on the CPU > > > > side > > > > means that you /do/ rely on non-snooped transfers, since if those > > > > transfers turn out not to snoop inadvertently, the accesses are > > > > incoherent with the CPU's view of memory. > > > > > > The driver generally only uses non-cached mappings if > > > drm_arch/device_can_wc_memory returns true. > > > >>> > > > >>> Indeed. And so we should take care to only return 'true' from that > > > >>> function if it is guaranteed that non-cached CPU mappings are coherent > > > >>> with the mappings used by the GPU, either because that is always the > > > >>> case (like on x86), or because we know that the platform in question > > > >>> implements NoSnoop correctly throughout the interconnect. > > > >>> > > > >>> What seems to be complicating matters is that in some cases, the > > > >>> device is non-cache coherent to begin with, so regardless of whether > > > >>> the NoSnoop attribute is used or not, those accesses will not snoop in > > > >>> the caches and be coherent with the non-cached mappings used by the > > > >>> CPU. So if we restrict this optimization [on non-X86] to platforms > > > >>> that are known to implement NoSnoop correctly, we may break platforms > > > >>> that are implicitly NoSnoop all the time. > > > >> > > > >> Since the driver generally doesn't rely on non-snooped accesses for > > > >> correctness, that couldn't "break" anything that hasn't always been > > > >> broken. > > > > > > > > Again, that is only true on x86. > > > > > > > > On other architectures, DMA writes from the device may allocate in the > > > > caches, and be invisible to the CPU when it uses non-cached mappings. > > > > > > Let me try one last time: > > > > > > If drm_arch_can_wc_memory returns false, the driver falls back to the > > > normal mode of operation, using a cacheable CPU mapping and snooped GPU > > > transfers, even if userspace asks (as a performance optimization) for a > > > write-combined CPU mapping and non-snooped GPU transfers via > > > AMDGPU_GEM_CREATE_CPU_GTT_USWC. > > > > Another question: when userspace requests for such a mapping to be > > created, does this involve pages that are mapped cacheable into the > > userland process? > > AMDGPU_GEM_CREATE_CPU_GTT_USWC means the buffer should be uncached and > write combined from the CPU's perspective (hence the 'CPU' in the flag > name). On the GPU side if that flag is set, we do an non-snooped GPU > mapping for better performance if the buffer ends up getting mapped > into the GPU's address space for GPU access. > Yes, so much was clear. And the reason this breaks on some arm64 systems is because a) non-snooped PCIe TLP attributes may be ignored, and b) non-x86 CPUs do not snoop the caches when accessing uncached mappings. I don't think there is actually any disagreement on this part. And I think my patch is reasonable, only Christoph is objecting to it on the grounds that drivers should not go around the DMA API and create vmap()s of DMA pages with self chosen attributes. What I am trying to figure out is why the coherency problem exists: - it could be that the device is reading using cached mappings and sees stale clean cachelines that shadow data written by the CPU
[PATCH] drm/amdgpu: clean up memory/GDS/GWS/OA alignment code
From: Marek Olšák
- move all adjustments into one place
- specify GDS/GWS/OA alignment in basic units of the heaps
- it looks like GDS alignment was 1 instead of 4
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 6 +++---
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index f4f00217546e..d21dd2f369da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -47,24 +47,20 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev,
unsigned long size,
u64 flags, enum ttm_bo_type type,
struct reservation_object *resv,
struct drm_gem_object **obj)
{
struct amdgpu_bo *bo;
struct amdgpu_bo_param bp;
int r;
memset(, 0, sizeof(bp));
*obj = NULL;
- /* At least align on page size */
- if (alignment < PAGE_SIZE) {
- alignment = PAGE_SIZE;
- }
bp.size = size;
bp.byte_align = alignment;
bp.type = type;
bp.resv = resv;
bp.preferred_domain = initial_domain;
retry:
bp.flags = flags;
bp.domain = initial_domain;
r = amdgpu_bo_create(adev, , );
@@ -237,23 +233,20 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
/* if gds bo is created from user space, it must be
* passed to bo list
*/
DRM_ERROR("GDS bo cannot be per-vm-bo\n");
return -EINVAL;
}
flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
- /* GDS allocations must be DW aligned */
- if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
- size = ALIGN(size, 4);
}
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
r = amdgpu_bo_reserve(vm->root.base.bo, false);
if (r)
return r;
resv = vm->root.base.bo->tbo.resv;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 728e15e5d68a..fd9c4beeaaa4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -419,26 +419,34 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
.interruptible = (bp->type != ttm_bo_type_kernel),
.no_wait_gpu = false,
.resv = bp->resv,
.flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
};
struct amdgpu_bo *bo;
unsigned long page_align, size = bp->size;
size_t acc_size;
int r;
- page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
- if (bp->domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS |
- AMDGPU_GEM_DOMAIN_OA))
+ /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
+ if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
+ /* GWS and OA don't need any alignment. */
+ page_align = bp->byte_align;
size <<= PAGE_SHIFT;
- else
+ } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
+ /* Both size and alignment must be a multiple of 4. */
+ page_align = ALIGN(bp->byte_align, 4);
+ size = ALIGN(size, 4) << PAGE_SHIFT;
+ } else {
+ /* Memory should be aligned at least to a page size. */
+ page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
size = ALIGN(size, PAGE_SIZE);
+ }
if (!amdgpu_bo_validate_size(adev, size, bp->domain))
return -ENOMEM;
*bo_ptr = NULL;
acc_size = ttm_bo_dma_acc_size(>mman.bdev, size,
sizeof(struct amdgpu_bo));
bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b852abb9db0f..73e71e61dc99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1749,47 +1749,47 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
/* Initialize various on-chip memory pools */
r = ttm_bo_init_mm(>mman.bdev, AMDGPU_PL_GDS,
adev->gds.mem.total_size);
if (r) {
DRM_ERROR("Failed initializing GDS heap.\n");
return r;
}
r =
Re: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86
On Tue, Jan 22, 2019 at 4:19 AM Ard Biesheuvel wrote: > > On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote: > > > > On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote: > > > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote: > > >> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote: > > >>> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote: > > On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote: > > > On Mon, 21 Jan 2019 at 18:55, Michel Dänzer > > > wrote: > > >> On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote: > > >>> On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig > > >>> wrote: > > >>> > > Until that happens we should just change the driver ifdefs to > > default > > the hacks to off and only enable them on setups where we 100% > > positively know that they actually work. And document that fact > > in big fat comments. > > >>> > > >>> Well, as I mentioned in my commit log as well, if we default to off > > >>> unless CONFIG_X86, we may break working setups on MIPS and Power > > >>> where > > >>> the device is in fact non-cache coherent, and relies on this > > >>> 'optimization' to get things working. > > >> > > >> FWIW, the amdgpu driver doesn't rely on non-snooped transfers for > > >> correct basic operation (the scenario Christian brought up is a very > > >> specialized use-case), so that shouldn't be an issue. > > > > > > The point is that this is only true for x86. > > > > > > On other architectures, the use of non-cached mappings on the CPU side > > > means that you /do/ rely on non-snooped transfers, since if those > > > transfers turn out not to snoop inadvertently, the accesses are > > > incoherent with the CPU's view of memory. > > > > The driver generally only uses non-cached mappings if > > drm_arch/device_can_wc_memory returns true. > > >>> > > >>> Indeed. And so we should take care to only return 'true' from that > > >>> function if it is guaranteed that non-cached CPU mappings are coherent > > >>> with the mappings used by the GPU, either because that is always the > > >>> case (like on x86), or because we know that the platform in question > > >>> implements NoSnoop correctly throughout the interconnect. > > >>> > > >>> What seems to be complicating matters is that in some cases, the > > >>> device is non-cache coherent to begin with, so regardless of whether > > >>> the NoSnoop attribute is used or not, those accesses will not snoop in > > >>> the caches and be coherent with the non-cached mappings used by the > > >>> CPU. So if we restrict this optimization [on non-X86] to platforms > > >>> that are known to implement NoSnoop correctly, we may break platforms > > >>> that are implicitly NoSnoop all the time. > > >> > > >> Since the driver generally doesn't rely on non-snooped accesses for > > >> correctness, that couldn't "break" anything that hasn't always been > > >> broken. > > > > > > Again, that is only true on x86. > > > > > > On other architectures, DMA writes from the device may allocate in the > > > caches, and be invisible to the CPU when it uses non-cached mappings. > > > > Let me try one last time: > > > > If drm_arch_can_wc_memory returns false, the driver falls back to the > > normal mode of operation, using a cacheable CPU mapping and snooped GPU > > transfers, even if userspace asks (as a performance optimization) for a > > write-combined CPU mapping and non-snooped GPU transfers via > > AMDGPU_GEM_CREATE_CPU_GTT_USWC. > > Another question: when userspace requests for such a mapping to be > created, does this involve pages that are mapped cacheable into the > userland process? AMDGPU_GEM_CREATE_CPU_GTT_USWC means the buffer should be uncached and write combined from the CPU's perspective (hence the 'CPU' in the flag name). On the GPU side if that flag is set, we do an non-snooped GPU mapping for better performance if the buffer ends up getting mapped into the GPU's address space for GPU access. Alex ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: add a workaround for GDS ordered append hangs with compute queues
From: Marek Olšák
I'm not increasing the DRM version because GDS isn't totally without bugs yet.
v2: update emit_ib_size
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 19 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 21 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++--
include/uapi/drm/amdgpu_drm.h | 5
5 files changed, 82 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
index ecbcefe49a98..f89f5734d985 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
@@ -30,20 +30,22 @@ struct amdgpu_bo;
struct amdgpu_gds_asic_info {
uint32_ttotal_size;
uint32_tgfx_partition_size;
uint32_tcs_partition_size;
};
struct amdgpu_gds {
struct amdgpu_gds_asic_info mem;
struct amdgpu_gds_asic_info gws;
struct amdgpu_gds_asic_info oa;
+ uint32_tgds_compute_max_wave_id;
+
/* At present, GDS, GWS and OA resources for gfx (graphics)
* is always pre-allocated and available for graphics operation.
* Such resource is shared between all gfx clients.
* TODO: move this operation to user space
* */
struct amdgpu_bo* gds_gfx_bo;
struct amdgpu_bo* gws_gfx_bo;
struct amdgpu_bo* oa_gfx_bo;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 7984292f9282..a59e0fdf5a97 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2257,20 +2257,36 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct
amdgpu_ring *ring,
}
static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
struct amdgpu_job *job,
struct amdgpu_ib *ib,
uint32_t flags)
{
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
+ /* Currently, there is a high possibility to get wave ID mismatch
+* between ME and GDS, leading to a hw deadlock, because ME generates
+* different wave IDs than the GDS expects. This situation happens
+* randomly when at least 5 compute pipes use GDS ordered append.
+* The wave IDs generated by ME are also wrong after suspend/resume.
+* Those are probably bugs somewhere else in the kernel driver.
+*
+* Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
+* GDS to 0 for this ring (me/pipe).
+*/
+ if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID -
PACKET3_SET_CONFIG_REG_START);
+ amdgpu_ring_write(ring,
ring->adev->gds.gds_compute_max_wave_id);
+ }
+
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
amdgpu_ring_write(ring,
#ifdef __BIG_ENDIAN
(2 << 0) |
#endif
(ib->gpu_addr & 0xFFFC));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0x);
amdgpu_ring_write(ring, control);
}
@@ -4993,21 +5009,21 @@ static const struct amdgpu_ring_funcs
gfx_v7_0_ring_funcs_compute = {
.get_rptr = gfx_v7_0_ring_get_rptr,
.get_wptr = gfx_v7_0_ring_get_wptr_compute,
.set_wptr = gfx_v7_0_ring_set_wptr_compute,
.emit_frame_size =
20 + /* gfx_v7_0_ring_emit_gds_switch */
7 + /* gfx_v7_0_ring_emit_hdp_flush */
5 + /* hdp invalidate */
7 + /* gfx_v7_0_ring_emit_pipeline_sync */
CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /*
gfx_v7_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user
fence, vm fence */
- .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
+ .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */
.emit_ib = gfx_v7_0_ring_emit_ib_compute,
.emit_fence = gfx_v7_0_ring_emit_fence_compute,
.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
.test_ring = gfx_v7_0_ring_test_ring,
.test_ib = gfx_v7_0_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
@@ -5050,20 +5066,21 @@ static void gfx_v7_0_set_irq_funcs(struct amdgpu_device
*adev)
[PATCH 19/20] drm/amd/display: Re-enable CRC capture following modeset
From: Nicholas Kazlauskas
[Why]
During any modeset the CRTC stream is removed and a new stream is added.
This new stream doesn't carry over CRC capture state if it was
previously set.
[How]
Re-program the stream for CRC capture. The existing DRM callback can
be re-used here for the most part - the only modification needed is
additional locking now that it's called from within commit tail.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Harry Wentland
Reviewed-by: Sun peng Li
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 8 +++-
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 68355ed..95ec8d8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5026,10 +5026,13 @@ static int amdgpu_dm_atomic_commit(struct drm_device
*dev,
if (drm_atomic_crtc_needs_modeset(new_crtc_state)
&& dm_old_crtc_state->stream) {
/*
-* CRC capture was enabled but not disabled.
-* Release the vblank reference.
+* If the stream is removed and CRC capture was
+* enabled on the CRTC the extra vblank reference
+* needs to be dropped since CRC capture will be
+* disabled.
*/
- if (dm_new_crtc_state->crc_enabled) {
+ if (!dm_new_crtc_state->stream
+ && dm_new_crtc_state->crc_enabled) {
drm_crtc_vblank_put(crtc);
dm_new_crtc_state->crc_enabled = false;
}
@@ -5267,6 +5270,10 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
continue;
manage_dm_interrupts(adev, acrtc, true);
+
+ /* The stream has changed so CRC capture needs to re-enabled. */
+ if (dm_new_crtc_state->crc_enabled)
+ amdgpu_dm_crtc_set_crc_source(crtc, "auto");
}
/* update planes when needed per crtc*/
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 26b6511..a10e3a5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -64,6 +64,7 @@ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const
char *src_name,
int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
{
+ struct amdgpu_device *adev = crtc->dev->dev_private;
struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
struct dc_stream_state *stream_state = crtc_state->stream;
bool enable;
@@ -83,15 +84,20 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc,
const char *src_name)
enable = (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO);
+ mutex_lock(>dm.dc_lock);
if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
-enable, enable))
+enable, enable)) {
+ mutex_unlock(>dm.dc_lock);
return -EINVAL;
+ }
/* When enabling CRC, we should also disable dithering. */
dc_stream_set_dither_option(stream_state,
enable ? DITHER_OPTION_TRUN8
: DITHER_OPTION_DEFAULT);
+ mutex_unlock(>dm.dc_lock);
+
/*
* Reading the CRC requires the vblank interrupt handler to be
* enabled. Keep a reference until CRC capture stops.
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/20] drm/amd/display: Enable vblank interrupt during CRC capture
From: Nicholas Kazlauskas
[Why]
In order to read CRC events when CRC capture is enabled the vblank
interrput handler needs to be running for the CRTC. The handler is
enabled while there is an active vblank reference.
When running IGT tests there will often be no active vblank reference
but the test expects to read a CRC value. This is valid usage (and
works on i915 since they have a CRC interrupt handler) so the reference
to the vblank should be grabbed while capture is active.
This issue was found running:
igt@kms_plane_multiple@atomic-pipe-b-tiling-none
The pipe-b is the only one in the initial commit and was not previously
active so no vblank reference is grabbed. The vblank interrupt is
not enabled and the test times out.
[How]
Keep a reference to the vblank as long as CRC capture is enabled.
If userspace never explicitly disables it then the reference is
also dropped when removing the CRTC from the context (stream = NULL).
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Harry Wentland
Reviewed-by: Sun peng Li
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 42 +++---
2 files changed, 34 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f1de7c8..68355ed 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5020,10 +5020,22 @@ static int amdgpu_dm_atomic_commit(struct drm_device
*dev,
*/
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
struct dm_crtc_state *dm_old_crtc_state =
to_dm_crtc_state(old_crtc_state);
+ struct dm_crtc_state *dm_new_crtc_state =
to_dm_crtc_state(new_crtc_state);
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- if (drm_atomic_crtc_needs_modeset(new_crtc_state) &&
dm_old_crtc_state->stream)
+ if (drm_atomic_crtc_needs_modeset(new_crtc_state)
+ && dm_old_crtc_state->stream) {
+ /*
+* CRC capture was enabled but not disabled.
+* Release the vblank reference.
+*/
+ if (dm_new_crtc_state->crc_enabled) {
+ drm_crtc_vblank_put(crtc);
+ dm_new_crtc_state->crc_enabled = false;
+ }
+
manage_dm_interrupts(adev, acrtc, false);
+ }
}
/*
* Add check here for SoC's that support hardware cursor plane, to
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index f088ac5..26b6511 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -66,6 +66,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc,
const char *src_name)
{
struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
struct dc_stream_state *stream_state = crtc_state->stream;
+ bool enable;
enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
@@ -80,28 +81,27 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc,
const char *src_name)
return -EINVAL;
}
+ enable = (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO);
+
+ if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
+enable, enable))
+ return -EINVAL;
+
/* When enabling CRC, we should also disable dithering. */
- if (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO) {
- if (dc_stream_configure_crc(stream_state->ctx->dc,
- stream_state,
- true, true)) {
- crtc_state->crc_enabled = true;
- dc_stream_set_dither_option(stream_state,
- DITHER_OPTION_TRUN8);
- }
- else
- return -EINVAL;
- } else {
- if (dc_stream_configure_crc(stream_state->ctx->dc,
- stream_state,
- false, false)) {
- crtc_state->crc_enabled = false;
- dc_stream_set_dither_option(stream_state,
- DITHER_OPTION_DEFAULT);
- }
- else
- return -EINVAL;
- }
+ dc_stream_set_dither_option(stream_state,
+ enable ? DITHER_OPTION_TRUN8
+ :
[PATCH 13/20] revert "drm/amd/display: Add condition to sync eDP SW status and HW status"
From: Eric Yang
[Why]
This change causes regression for S4 resume where gamma is not
programmed. The change incorrectly updates the requested dpms_off
state.
This reverts commit d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600.
Signed-off-by: Eric Yang
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 -
.../drm/amd/display/dc/bios/bios_parser_helper.c | 93 --
.../drm/amd/display/dc/bios/bios_parser_helper.h | 4 -
drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 5 --
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 15
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 -
6 files changed, 120 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index c513ab6..190b8c4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1899,8 +1899,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
.is_accelerated_mode = bios_parser_is_accelerated_mode,
- .is_active_display = bios_is_active_display,
-
.set_scratch_critical_state = bios_parser_set_scratch_critical_state,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index d8275ceb..fce46ab 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -87,96 +87,3 @@ uint32_t bios_get_vga_enabled_displays(
return active_disp;
}
-bool bios_is_active_display(
- struct dc_bios *bios,
- enum signal_type signal,
- const struct connector_device_tag_info *device_tag)
-{
- uint32_t active = 0;
- uint32_t connected = 0;
- uint32_t bios_scratch_0 = 0;
- uint32_t bios_scratch_3 = 0;
-
- switch (signal) {
- case SIGNAL_TYPE_DVI_SINGLE_LINK:
- case SIGNAL_TYPE_DVI_DUAL_LINK:
- case SIGNAL_TYPE_HDMI_TYPE_A:
- case SIGNAL_TYPE_DISPLAY_PORT:
- case SIGNAL_TYPE_DISPLAY_PORT_MST:
- {
- if (device_tag->dev_id.device_type == DEVICE_TYPE_DFP) {
- switch (device_tag->dev_id.enum_id) {
- case 1:
- {
- active= ATOM_S3_DFP1_ACTIVE;
- connected = 0x0008;
//ATOM_DISPLAY_DFP1_CONNECT
- }
- break;
-
- case 2:
- {
- active= ATOM_S3_DFP2_ACTIVE;
- connected = 0x0080;
//ATOM_DISPLAY_DFP2_CONNECT
- }
- break;
-
- case 3:
- {
- active= ATOM_S3_DFP3_ACTIVE;
- connected = 0x0200;
//ATOM_DISPLAY_DFP3_CONNECT
- }
- break;
-
- case 4:
- {
- active= ATOM_S3_DFP4_ACTIVE;
- connected = 0x0400;
//ATOM_DISPLAY_DFP4_CONNECT
- }
- break;
-
- case 5:
- {
- active= ATOM_S3_DFP5_ACTIVE;
- connected = 0x0800;
//ATOM_DISPLAY_DFP5_CONNECT
- }
- break;
-
- case 6:
- {
- active= ATOM_S3_DFP6_ACTIVE;
- connected = 0x0040;
//ATOM_DISPLAY_DFP6_CONNECT
- }
- break;
-
- default:
- break;
- }
- }
- }
- break;
-
- case SIGNAL_TYPE_LVDS:
- case SIGNAL_TYPE_EDP:
- {
- active= ATOM_S3_LCD1_ACTIVE;
- connected = 0x0002; //ATOM_DISPLAY_LCD1_CONNECT
- }
- break;
-
- default:
- break;
- }
-
-
-
[PATCH 20/20] drm/amd/display: Add Vline1 interrupt source to InterruptManager
From: Fatemeh Darbehani
[Why]
Enhanced sync need to use vertical_interrupt1.
[How]
Add vertical_interrupt1 source to irq manger,
Implment setup vline interrupt interface.
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +--
drivers/gpu/drm/amd/display/dc/dc_stream.h | 14 -
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 72 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 12 +++-
.../drm/amd/display/dc/inc/hw/timing_generator.h | 13 +++-
drivers/gpu/drm/amd/display/dc/irq_types.h | 8 +++
6 files changed, 61 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1dabafc..e22be0a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1463,11 +1463,13 @@ static void commit_planes_do_stream_update(struct dc
*dc,
stream_update->adjust->v_total_min,
stream_update->adjust->v_total_max);
- if (stream_update->periodic_fn_vsync_delta &&
-
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
+ if (stream_update->vline0_config &&
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
- pipe_ctx->stream_res.tg,
_ctx->stream->timing,
-
pipe_ctx->stream->periodic_fn_vsync_delta);
+ pipe_ctx->stream_res.tg, VLINE0,
stream->vline0_config);
+
+ if (stream_update->vline1_config &&
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
+
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
+ pipe_ctx->stream_res.tg, VLINE1,
stream->vline1_config);
if ((stream_update->hdr_static_metadata &&
!stream->use_dynamic_meta) ||
stream_update->vrr_infopacket ||
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 7bb1da1..0de6d7f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -45,6 +45,11 @@ struct freesync_context {
bool dummy;
};
+struct vline_config {
+ unsigned int start_line;
+ unsigned int end_line;
+};
+
struct dc_stream_state {
// sink is deprecated, new code should not reference
// this pointer
@@ -85,8 +90,6 @@ struct dc_stream_state {
uint8_t qs_bit;
uint8_t qy_bit;
- unsigned long long periodic_fn_vsync_delta;
-
/* TODO: custom INFO packets */
/* TODO: ABM info (DMCU) */
/* PSR info */
@@ -96,6 +99,9 @@ struct dc_stream_state {
/* DMCU info */
unsigned int abm_level;
+ struct vline_config vline0_config;
+ struct vline_config vline1_config;
+
/* from core_stream struct */
struct dc_context *ctx;
@@ -143,7 +149,9 @@ struct dc_stream_update {
struct dc_info_packet *hdr_static_metadata;
unsigned int *abm_level;
- unsigned long long *periodic_fn_vsync_delta;
+ struct vline_config *vline0_config;
+ struct vline_config *vline1_config;
+
struct dc_crtc_timing_adjust *adjust;
struct dc_info_packet *vrr_infopacket;
struct dc_info_packet *vsc_infopacket;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index eb019d4..1d4f9b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -92,68 +92,26 @@ static void optc1_disable_stereo(struct timing_generator
*optc)
OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
}
-static uint32_t get_start_vline(struct timing_generator *optc, const struct
dc_crtc_timing *dc_crtc_timing)
-{
- struct dc_crtc_timing patched_crtc_timing;
- int vesa_sync_start;
- int asic_blank_end;
- int vertical_line_start;
-
- patched_crtc_timing = *dc_crtc_timing;
- optc1_apply_front_porch_workaround(optc, _crtc_timing);
-
- vesa_sync_start = patched_crtc_timing.v_addressable +
- patched_crtc_timing.v_border_bottom +
- patched_crtc_timing.v_front_porch;
-
- asic_blank_end = (patched_crtc_timing.v_total -
- vesa_sync_start -
- patched_crtc_timing.v_border_top);
-
- vertical_line_start = asic_blank_end -
optc->dlg_otg_param.vstartup_start + 1;
- if (vertical_line_start < 0)
- vertical_line_start = 0;
-
-
[PATCH 16/20] drm/amd/display: Connect dig_fe to otg directly instead of calling bios
From: hersen wu
[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other fmt register
for bios usage which is redundancy and uncessary.
[How] Program dig_soruce_select register directly
Signed-off-by: hersen wu
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 14 ---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 14 ---
.../gpu/drm/amd/display/dc/bios/command_table.c| 116 -
.../gpu/drm/amd/display/dc/bios/command_table.h| 3 -
.../gpu/drm/amd/display/dc/bios/command_table2.c | 70 -
.../gpu/drm/amd/display/dc/bios/command_table2.h | 3 -
drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 4 -
.../drm/amd/display/dc/dce/dce_stream_encoder.c| 10 +-
.../drm/amd/display/dc/dce/dce_stream_encoder.h| 8 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 54 +-
.../amd/display/dc/dcn10/dcn10_stream_encoder.c| 9 ++
.../amd/display/dc/dcn10/dcn10_stream_encoder.h| 10 +-
.../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 4 +
13 files changed, 39 insertions(+), 280 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index c2ab026..a4c97d3 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -835,18 +835,6 @@ static enum bp_result bios_parser_enable_crtc(
return bp->cmd_tbl.enable_crtc(bp, id, enable);
}
-static enum bp_result bios_parser_crtc_source_select(
- struct dc_bios *dcb,
- struct bp_crtc_source_select *bp_params)
-{
- struct bios_parser *bp = BP_FROM_DCB(dcb);
-
- if (!bp->cmd_tbl.select_crtc_source)
- return BP_RESULT_FAILURE;
-
- return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-}
-
static enum bp_result bios_parser_enable_disp_power_gating(
struct dc_bios *dcb,
enum controller_id controller_id,
@@ -2842,8 +2830,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
.program_crtc_timing = bios_parser_program_crtc_timing, /* still use.
should probably retire and program directly */
- .crtc_source_select = bios_parser_crtc_source_select, /* still use.
should probably retire and program directly */
-
.program_display_engine_pll = bios_parser_program_display_engine_pll,
.enable_disp_power_gating = bios_parser_enable_disp_power_gating,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 190b8c4..a1c56f2 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1083,18 +1083,6 @@ static enum bp_result bios_parser_enable_crtc(
return bp->cmd_tbl.enable_crtc(bp, id, enable);
}
-static enum bp_result bios_parser_crtc_source_select(
- struct dc_bios *dcb,
- struct bp_crtc_source_select *bp_params)
-{
- struct bios_parser *bp = BP_FROM_DCB(dcb);
-
- if (!bp->cmd_tbl.select_crtc_source)
- return BP_RESULT_FAILURE;
-
- return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-}
-
static enum bp_result bios_parser_enable_disp_power_gating(
struct dc_bios *dcb,
enum controller_id controller_id,
@@ -1915,8 +1903,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
.program_crtc_timing = bios_parser_program_crtc_timing,
- .crtc_source_select = bios_parser_crtc_source_select,
-
.enable_disp_power_gating = bios_parser_enable_disp_power_gating,
.bios_parser_destroy = firmware_parser_destroy,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 67c119b..5815983 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -55,7 +55,6 @@ static void init_adjust_display_pll(struct bios_parser *bp);
static void init_dac_encoder_control(struct bios_parser *bp);
static void init_dac_output_control(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
-static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_enable_crtc_mem_req(struct bios_parser *bp);
static void init_external_encoder_control(struct bios_parser *bp);
@@ -73,7 +72,6 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_dac_encoder_control(bp);
init_dac_output_control(bp);
init_set_crtc_timing(bp);
- init_select_crtc_source(bp);
init_enable_crtc(bp);
init_enable_crtc_mem_req(bp);
init_program_clock(bp);
@@ -1898,120 +1896,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
[PATCH 17/20] drm/amd/display: Poll pending down rep before clear payload allocation table
From: Martin Tsai
[Why]
On current design, driver cannot handle the interrupt for
down reply when link training is processing. The DOWN REQ
send before link training will keep in the pending DOWN REP
state in the queue.
It makes the next DOWN REQ be queued until time out.
[How]
To add a polling sequence before clear payload allocation table
to make sure the pending DOWN REP can be handled.
Signed-off-by: Martin Tsai
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 7 +++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 7 +++
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index e6ab018..cae16b6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -263,6 +263,13 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
return true;
}
+/*
+ * poll pending down reply before clear payload allocation table
+ */
+void dm_helpers_dp_mst_poll_pending_down_reply(
+ struct dc_context *ctx,
+ const struct dc_link *link)
+{}
/*
* Clear payload allocation table before enable MST DP link.
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 3dd5f27..8ff5d42 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1467,6 +1467,11 @@ static enum dc_status enable_link_dp_mst(
if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
return DC_OK;
+ /* to make sure the pending down rep can be processed
+* before clear payload table
+*/
+ dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
+
/* clear payload table */
dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 5d4527d..e81b243 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -58,6 +58,13 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
bool enable);
/*
+ * poll pending down reply before clear payload allocation table
+ */
+void dm_helpers_dp_mst_poll_pending_down_reply(
+ struct dc_context *ctx,
+ const struct dc_link *link);
+
+/*
* Clear payload allocation table before enable MST DP link.
*/
void dm_helpers_dp_mst_clear_payload_allocation_table(
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/20] drm/amd/display: take dpms_off into account for edp turn off logic
From: Eric Yang
[why]
Previously we incorrectly skipped backlight control when stream is
present but dpms_off = true. This causes backlight to remain on in
the we boot up or resume into a external display only configuration
where VBIOS posted on the eDP.
[How]
Add dpms_off into the condition for edp need to turn off.
Signed-off-by: Eric Yang
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 97796fa2..026d973 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1520,7 +1520,7 @@ static struct dc_link *get_link_for_edp(struct dc *dc)
return NULL;
}
-static struct dc_link *get_link_for_edp_not_in_use(
+static struct dc_link *get_link_for_edp_to_turn_off(
struct dc *dc,
struct dc_state *context)
{
@@ -1529,8 +1529,12 @@ static struct dc_link *get_link_for_edp_not_in_use(
/* check if eDP panel is suppose to be set mode, if yes, no need to
disable */
for (i = 0; i < context->stream_count; i++) {
- if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
- return NULL;
+ if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
+ if (context->streams[i]->dpms_off == true)
+ return context->streams[i]->sink->link;
+ else
+ return NULL;
+ }
}
/* check if there is an eDP panel not in use */
@@ -1572,7 +1576,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct
dc_state *context)
}
if (can_edp_fast_boot_optimize)
- edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
+ edp_link_to_turnoff = get_link_for_edp_to_turn_off(dc, context);
/* if OS doesn't light up eDP and eDP link is available, we want to
disable
* If resume from S4/S5, should optimization.
--
2.7.4
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/20] drm/amd/display: Call into DC once per multiplane flip
From: David Francis
[Why]
amdgpu_dm_commit_planes was performing multi-plane
flips incorrectly:
It waited for vblank once per flipped plane
It prepared flip ISR and acquired the corresponding vblank ref
once per plane, although it closed ISR and put the ref once
per crtc
It called into dc once per flipped plane, duplicating some work
[How]
Wait for vblank, get vblank ref, prepare flip ISR, and call into
DC only once, and only if there is a pageflip
Make freesync continue to update planes even if vrr information
has already been changed
Signed-off-by: David Francis
Reviewed-by: Harry Wentland
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 335 ++
1 file changed, 154 insertions(+), 181 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index db060da..818a2a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4691,12 +4691,12 @@ static void update_freesync_state_on_stream(
TRANSFER_FUNC_UNKNOWN,
_infopacket);
- new_crtc_state->freesync_timing_changed =
+ new_crtc_state->freesync_timing_changed |=
(memcmp(_crtc_state->vrr_params.adjust,
_params.adjust,
sizeof(vrr_params.adjust)) != 0);
- new_crtc_state->freesync_vrr_info_changed =
+ new_crtc_state->freesync_vrr_info_changed |=
(memcmp(_crtc_state->vrr_infopacket,
_infopacket,
sizeof(vrr_infopacket)) != 0);
@@ -4721,156 +4721,6 @@ static void update_freesync_state_on_stream(
}
/*
- * Executes flip
- *
- * Waits on all BO's fences and for proper vblank count
- */
-static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- uint32_t target,
- struct dc_state *state)
-{
- unsigned long flags;
- uint64_t timestamp_ns;
- uint32_t target_vblank;
- int r, vpos, hpos;
- struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
- struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
- struct amdgpu_device *adev = crtc->dev->dev_private;
- bool async_flip = (crtc->state->pageflip_flags &
DRM_MODE_PAGE_FLIP_ASYNC) != 0;
- struct dc_flip_addrs addr = { {0} };
- /* TODO eliminate or rename surface_update */
- struct dc_surface_update surface_updates[1] = { {0} };
- struct dc_stream_update stream_update = {0};
- struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
- struct dc_stream_status *stream_status;
- struct dc_plane_state *surface;
- uint64_t tiling_flags, dcc_address;
-
-
- /* Prepare wait for target vblank early - before the fence-waits */
- target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
- amdgpu_get_vblank_counter_kms(crtc->dev,
acrtc->crtc_id);
-
- /*
-* TODO This might fail and hence better not used, wait
-* explicitly on fences instead
-* and in general should be called for
-* blocking commit to as per framework helpers
-*/
- r = amdgpu_bo_reserve(abo, true);
- if (unlikely(r != 0)) {
- DRM_ERROR("failed to reserve buffer before flip\n");
- WARN_ON(1);
- }
-
- /* Wait for all fences on this FB */
- WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
-
MAX_SCHEDULE_TIMEOUT) < 0);
-
- amdgpu_bo_get_tiling_flags(abo, _flags);
-
- amdgpu_bo_unreserve(abo);
-
- /*
-* Wait until we're out of the vertical blank period before the one
-* targeted by the flip
-*/
- while ((acrtc->enabled &&
- (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
- 0, , , NULL,
- NULL, >hwmode)
-& (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
- (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
- (int)(target_vblank -
- amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) >
0)) {
- usleep_range(1000, 1100);
- }
-
- /* Flip */
- spin_lock_irqsave(>dev->event_lock, flags);
-
- WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
- WARN_ON(!acrtc_state->stream);
-
- addr.address.grph.addr.low_part = lower_32_bits(afb->address);
- addr.address.grph.addr.high_part = upper_32_bits(afb->address);
-
- dcc_address = get_dcc_address(afb->address, tiling_flags);
-
[PATCH 06/20] drm/amd/display: Let updates with no scaling changes be fast
From: David Francis [Why] DC was assuming that any surface_update->scaling_info meant the update was at least medium. However, if nothing has changed there is no scaling to program, so there is no problem with the update being fast [How] If every update flag is not set, the update is fast Signed-off-by: David Francis Reviewed-by: Harry Wentland Acked-by: Leo Li Acked-by: Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5670284..1dabafc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1240,7 +1240,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa || update_flags->bits.output_tf_change) return UPDATE_TYPE_FULL; - return UPDATE_TYPE_MED; + return update_flags->raw ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST; } static enum surface_update_type get_scaling_info_update_type( -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/20] drm/amd/display: Default to linear output gamma
From: Krunoslav Kovac
[Why] Our output TF calculation doesn't work if no user-specified gamma
correction. Normally, user provides this, but driver sohuld just assume
default (linear) gamma otherwise.
[How] Remove output TF dependency on user gamma being provided.
Signed-off-by: Krunoslav Kovac
Reviewed-by: Anthony Koo
Acked-by: Leo Li
Acked-by: Sivapiriyan Kumarasamy
---
.../drm/amd/display/modules/color/color_gamma.c| 73 --
1 file changed, 40 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 4cee084..eefb8592 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1508,7 +1508,7 @@ static bool map_regamma_hw_to_x_user(
struct hw_x_point *coords = coords_x;
const struct pwl_float_data_ex *regamma = rgb_regamma;
- if (mapUserRamp) {
+ if (ramp && mapUserRamp) {
copy_rgb_regamma_to_coordinates_x(coords,
hw_points_num,
rgb_regamma);
@@ -1545,7 +1545,7 @@ bool mod_color_calculate_regamma_params(struct
dc_transfer_func *output_tf,
struct pwl_float_data *rgb_user = NULL;
struct pwl_float_data_ex *rgb_regamma = NULL;
- struct gamma_pixel *axix_x = NULL;
+ struct gamma_pixel *axis_x = NULL;
struct pixel_gamma_point *coeff = NULL;
enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
bool ret = false;
@@ -1555,47 +1555,54 @@ bool mod_color_calculate_regamma_params(struct
dc_transfer_func *output_tf,
/* we can use hardcoded curve for plain SRGB TF */
if (output_tf->type == TF_TYPE_PREDEFINED && canRomBeUsed == true &&
- output_tf->tf == TRANSFER_FUNCTION_SRGB &&
- (ramp->is_identity || (!mapUserRamp && ramp->type ==
GAMMA_RGB_256)))
- return true;
+ output_tf->tf == TRANSFER_FUNCTION_SRGB) {
+ if (ramp == NULL)
+ return true;
+ if (ramp->is_identity || (!mapUserRamp && ramp->type ==
GAMMA_RGB_256))
+ return true;
+ }
output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
- rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
+ if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
+ rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
sizeof(*rgb_user),
GFP_KERNEL);
- if (!rgb_user)
- goto rgb_user_alloc_fail;
+ if (!rgb_user)
+ goto rgb_user_alloc_fail;
+
+ axis_x = kvcalloc(ramp->num_entries + 3, sizeof(*axis_x),
+ GFP_KERNEL);
+ if (!axis_x)
+ goto axis_x_alloc_fail;
+
+ dividers.divider1 = dc_fixpt_from_fraction(3, 2);
+ dividers.divider2 = dc_fixpt_from_int(2);
+ dividers.divider3 = dc_fixpt_from_fraction(5, 2);
+
+ build_evenly_distributed_points(
+ axis_x,
+ ramp->num_entries,
+ dividers);
+
+ if (ramp->type == GAMMA_RGB_256 && mapUserRamp)
+ scale_gamma(rgb_user, ramp, dividers);
+ else if (ramp->type == GAMMA_RGB_FLOAT_1024)
+ scale_gamma_dx(rgb_user, ramp, dividers);
+ }
+
rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
sizeof(*rgb_regamma),
GFP_KERNEL);
if (!rgb_regamma)
goto rgb_regamma_alloc_fail;
- axix_x = kvcalloc(ramp->num_entries + 3, sizeof(*axix_x),
- GFP_KERNEL);
- if (!axix_x)
- goto axix_x_alloc_fail;
+
coeff = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, sizeof(*coeff),
GFP_KERNEL);
if (!coeff)
goto coeff_alloc_fail;
- dividers.divider1 = dc_fixpt_from_fraction(3, 2);
- dividers.divider2 = dc_fixpt_from_int(2);
- dividers.divider3 = dc_fixpt_from_fraction(5, 2);
-
tf = output_tf->tf;
-
- build_evenly_distributed_points(
- axix_x,
- ramp->num_entries,
- dividers);
-
- if (ramp->type == GAMMA_RGB_256 && mapUserRamp)
- scale_gamma(rgb_user, ramp, dividers);
- else if (ramp->type == GAMMA_RGB_FLOAT_1024)
- scale_gamma_dx(rgb_user, ramp, dividers);
-
if (tf == TRANSFER_FUNCTION_PQ) {
tf_pts->end_exponent = 7;
tf_pts->x_point_at_y1_red = 125;
@@ -1623,22 +1630,22 @@ bool
[PATCH 08/20] drm/amd/display: Update DMCU versioning mechanism
From: Josip Pavic
[Why]
Current date based versioning doesn't tell us about feature version
and build version, and is not useful for debug.
[How]
Add versioning based on feature and build
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +++---
drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 6 +++---
drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 9 -
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index e927c89..c2926cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -331,10 +331,10 @@ static void dcn10_get_dmcu_version(struct dmcu *dmcu)
/* Write address to IRAM_RD_ADDR and read from DATA register */
REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
- dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
+ dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
+ dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
+ dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
REG_READ(DMCU_IRAM_RD_DATA));
- dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA);
- dmcu->dmcu_version.date = REG_READ(DMCU_IRAM_RD_DATA);
/* Disable write access to IRAM to allow dynamic sleep state */
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index ed32a75..cbaa438 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -39,10 +39,10 @@ enum dmcu_state {
};
struct dmcu_version {
- unsigned int date;
- unsigned int month;
- unsigned int year;
unsigned int interface_version;
+ unsigned int abm_version;
+ unsigned int psr_version;
+ unsigned int build_version;
};
struct dmcu {
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 89b082b..5432183 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -87,11 +87,10 @@ struct iram_table_v_2 {
/* For reading PSR State directly from IRAM */
uint8_t psr_state; /* 0xf0
*/
- uint8_t dmcu_interface_version; /* 0xf1
*/
- uint8_t dmcu_date_version_year_b0; /* 0xf2
*/
- uint8_t dmcu_date_version_year_b1; /* 0xf3
*/
- uint8_t dmcu_date_version_month;/* 0xf4
*/
- uint8_t dmcu_date_version_day; /* 0xf5
*/
+ uint8_t dmcu_mcp_interface_version;
/* 0xf1 */
+ uint8_t dmcu_abm_feature_version;
/* 0xf2 */
+ uint8_t dmcu_psr_feature_version;
/* 0xf3 */
+ uint16_t dmcu_version;
/* 0xf4 */
uint8_t dmcu_state; /* 0xf6
*/
uint16_t blRampReduction; /* 0xf7
*/
--
2.7.4
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[PATCH 04/20] drm/amd/display: Know what a pageflip is
From: David Francis
[Why]
We were assuming that any commit with allow_modeset == false
was a pageflip. This was against drm intention and only
worked by sheer luck
[How]
A pageflip is the change from one framebuffer to another
Signed-off-by: David Francis
Reviewed-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 405c263..db060da 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4995,6 +4995,8 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
struct drm_crtc *crtc = new_plane_state->crtc;
struct drm_crtc_state *new_crtc_state;
struct drm_framebuffer *fb = new_plane_state->fb;
+ struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
+ struct amdgpu_framebuffer *old_afb =
to_amdgpu_framebuffer(old_plane_state->fb);
bool pflip_needed;
struct dm_plane_state *dm_new_plane_state =
to_dm_plane_state(new_plane_state);
@@ -5010,7 +5012,8 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
if (!new_crtc_state->active)
continue;
- pflip_needed = !state->allow_modeset;
+ pflip_needed = old_plane_state->fb &&
+ (old_plane_state->fb != new_plane_state->fb ||
afb->address != old_afb->address);
spin_lock_irqsave(>dev->event_lock, flags);
if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
--
2.7.4
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[PATCH 09/20] drm/amd/display: Create switching mechanism for ABM 2.2
From: Josip Pavic
[Why]
Need method of detecting which version of the DMCU FW is loaded and
load the appropriate iRAM.
[How]
Create definition for ABM 2.2 iRAM, and load it if the DMCU FW version
number matches the ABM 2.2 version; otherwise load ABM 2.1 iRAM.
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
.../drm/amd/display/modules/power/power_helpers.c | 583 +++--
1 file changed, 418 insertions(+), 165 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 5432183..29b7a26 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -41,6 +41,17 @@ static const unsigned char min_reduction_table[13] = {
static const unsigned char max_reduction_table[13] = {
0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
+/* ABM 2.2 Min Reduction effectively disabled (100% for all configs)*/
+static const unsigned char min_reduction_table_v_2_2[13] = {
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+/* Possible ABM 2.2 Max Reduction configs from least aggressive to most
aggressive
+ * 01 2 3 4 5 6 7 8 9 1011 12
+ * 96.1 89.8 85.1 80.3 69.4 64.7 54.9 45.1 30.2 25.1 19.6 12.5 12.5 %
+ */
+static const unsigned char max_reduction_table_v_2_2[13] = {
+0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0x8c, 0x73, 0x4d, 0x40, 0x32, 0x20, 0x20};
+
/* Predefined ABM configuration sets. We may have different configuration sets
* in order to satisfy different power/quality requirements.
*/
@@ -57,6 +68,7 @@ static const unsigned char
abm_config[abm_defines_max_config][abm_defines_max_le
#define NUM_POWER_FN_SEGS 8
#define NUM_BL_CURVE_SEGS 16
#define IRAM_RESERVE_AREA_START 0xF0 // reserve 0xF0~0xFF are write by DMCU
only
+#define IRAM_SIZE 256
#pragma pack(push, 1)
/* NOTE: iRAM is 256B in size */
@@ -101,6 +113,49 @@ struct iram_table_v_2 {
uint8_t dummy8; /* 0xfe
*/
uint8_t dummy9; /* 0xff
*/
};
+
+struct iram_table_v_2_2 {
+ /* flags */
+ uint16_t flags; /* 0x00
U16 */
+
+ /* parameters for ABM2.2 algorithm */
+ uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02
U0.8 */
+ uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16
U0.8 */
+ uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];/* 0x2a
U2.6 */
+ uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e
U2.6 */
+ uint8_t hybridFactor[NUM_AGGR_LEVEL];
/* 0x52 U0.8 */
+ uint8_t contrastFactor[NUM_AGGR_LEVEL];
/* 0x56 U0.8 */
+ uint8_t deviation_gain[NUM_AGGR_LEVEL];
/* 0x5a U0.8 */
+ uint8_t iir_curve[NUM_AMBI_LEVEL];
/* 0x5e U0.8 */
+ uint8_t pad[29];
/* 0x63 U0.8 */
+
+ /* parameters for crgb conversion */
+ uint16_t crgb_thresh[NUM_POWER_FN_SEGS];
/* 0x80 U3.13 */
+ uint16_t crgb_offset[NUM_POWER_FN_SEGS];
/* 0x90 U1.15 */
+ uint16_t crgb_slope[NUM_POWER_FN_SEGS];
/* 0xa0 U4.12 */
+
+ /* parameters for custom curve */
+ /* thresholds for brightness --> backlight */
+ uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];
/* 0xb0 U16.0 */
+ /* offsets for brightness --> backlight */
+ uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];
/* 0xd0 U16.0 */
+
+ /* For reading PSR State directly from IRAM */
+ uint8_t psr_state;
/* 0xf0 */
+ uint8_t dmcu_mcp_interface_version;
/* 0xf1 */
+ uint8_t dmcu_abm_feature_version;
/* 0xf2 */
+ uint8_t dmcu_psr_feature_version;
/* 0xf3 */
+ uint16_t dmcu_version;
/* 0xf4 */
+ uint8_t dmcu_state;
/* 0xf6 */
+
+ uint16_t blRampReduction;
[PATCH 07/20] drm/amd/display: Perform plane updates only when needed
From: David Francis
[Why]
Our old logic: if pageflip, update freesync and plane address.
Otherwise, update everything.
This over-updated on non-pageflip cases, and it failed to
update if pageflip and non-pageflip changes occurred on
the same commit
[How]
Update flip_addrs on pageflips.
Update scaling_info when it changes.
Update color fields on color changes.
Updates plane_info always because we don't have a good way of
knowing when it needs to be updated.
Unfortunately, this means that every stream commit involves two
calls into DC. In particular, on pageflips there is a second,
pointless update that changes nothing but costs several
microseconds (about a 50% increase in time taken). The update is
fast, but there are comparisons and some useless programming.
Leave TODOs indicating dissatisfaction.
Signed-off-by: David Francis
Reviewed-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 193 +++---
1 file changed, 63 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 818a2a1..f1de7c8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4720,105 +4720,6 @@ static void update_freesync_state_on_stream(
vrr_params.adjust.v_total_max);
}
-/*
- * TODO this whole function needs to go
- *
- * dc_surface_update is needlessly complex. See if we can just replace this
- * with a dc_plane_state and follow the atomic model a bit more closely here.
- */
-static bool commit_planes_to_stream(
- struct amdgpu_display_manager *dm,
- struct dc *dc,
- struct dc_plane_state **plane_states,
- uint8_t new_plane_count,
- struct dm_crtc_state *dm_new_crtc_state,
- struct dm_crtc_state *dm_old_crtc_state,
- struct dc_state *state)
-{
- /* no need to dynamically allocate this. it's pretty small */
- struct dc_surface_update updates[MAX_SURFACES];
- struct dc_flip_addrs *flip_addr;
- struct dc_plane_info *plane_info;
- struct dc_scaling_info *scaling_info;
- int i;
- struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
- struct dc_stream_update *stream_update =
- kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
- unsigned int abm_level;
-
- if (!stream_update) {
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
- GFP_KERNEL);
- plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
-GFP_KERNEL);
- scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
- GFP_KERNEL);
-
- if (!flip_addr || !plane_info || !scaling_info) {
- kfree(flip_addr);
- kfree(plane_info);
- kfree(scaling_info);
- kfree(stream_update);
- return false;
- }
-
- memset(updates, 0, sizeof(updates));
-
- stream_update->src = dc_stream->src;
- stream_update->dst = dc_stream->dst;
- stream_update->out_transfer_func = dc_stream->out_transfer_func;
-
- if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
- abm_level = dm_new_crtc_state->abm_level;
- stream_update->abm_level = _level;
- }
-
- for (i = 0; i < new_plane_count; i++) {
- updates[i].surface = plane_states[i];
- updates[i].gamma =
- (struct dc_gamma *)plane_states[i]->gamma_correction;
- updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
- flip_addr[i].address = plane_states[i]->address;
- flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
- plane_info[i].color_space = plane_states[i]->color_space;
- plane_info[i].format = plane_states[i]->format;
- plane_info[i].plane_size = plane_states[i]->plane_size;
- plane_info[i].rotation = plane_states[i]->rotation;
- plane_info[i].horizontal_mirror =
plane_states[i]->horizontal_mirror;
- plane_info[i].stereo_format = plane_states[i]->stereo_format;
- plane_info[i].tiling_info = plane_states[i]->tiling_info;
- plane_info[i].visible = plane_states[i]->visible;
- plane_info[i].per_pixel_alpha =
plane_states[i]->per_pixel_alpha;
- plane_info[i].dcc = plane_states[i]->dcc;
- scaling_info[i].scaling_quality =
plane_states[i]->scaling_quality;
- scaling_info[i].src_rect = plane_states[i]->src_rect;
-
[PATCH 10/20] drm/amd/display: Fix use of uninitialized union
From: John Barberiz
[Why]
An uninitialized variable would randomly initialize to a large
value. This caused enough delay to fail DP Compliance Test 400.2.1.
[How]
Initialize the variable.
Signed-off-by: John Barberiz
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 431805c..92f565c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -47,7 +47,7 @@ static void wait_for_training_aux_rd_interval(
struct dc_link *link,
uint32_t default_wait_in_micro_secs)
{
- union training_aux_rd_interval training_rd_interval;
+ union training_aux_rd_interval training_rd_interval = {0};
/* overwrite the delay if rev > 1.1*/
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
--
2.7.4
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[PATCH 15/20] drm/amd/display: 3.2.15
From: Steven Chiu Signed-off-by: Steven Chiu Reviewed-by: Aric Cyr Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f362b04..8391bc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -39,7 +39,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.14" +#define DC_VER "3.2.15" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/20] drm/amd/display: Adjust ABM 2.2 contrast parameters
From: Josip Pavic [Why] Improved contrast in ABM 2.2 is desired [How] Increase the contrast factor for ABM levels 2, 3 and 4 Signed-off-by: Josip Pavic Reviewed-by: Anthony Koo Acked-by: Leo Li --- drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 29b7a26..baab6c4 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -517,9 +517,9 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parame ram_table->hybridFactor[3] = 0xc0; ram_table->contrastFactor[0] = 0x99; - ram_table->contrastFactor[1] = 0x80; - ram_table->contrastFactor[2] = 0x80; - ram_table->contrastFactor[3] = 0x4D; + ram_table->contrastFactor[1] = 0x99; + ram_table->contrastFactor[2] = 0x99; + ram_table->contrastFactor[3] = 0x80; ram_table->iir_curve[0] = 0x65; ram_table->iir_curve[1] = 0x65; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/20] DC Patches Jan 22, 2019
From: Leo Li Summary of change: * Fixes for pageflipping logic * Multiplane flipping support * Make it more atomic * Fix CRC capture on pipes with no active vblank reference * Simplify commit for scaling and ABM changes David Francis (5): drm/amd/display: Simplify underscan and ABM commit drm/amd/display: Know what a pageflip is drm/amd/display: Call into DC once per multiplane flip drm/amd/display: Let updates with no scaling changes be fast drm/amd/display: Perform plane updates only when needed Eric Yang (2): revert "drm/amd/display: Add condition to sync eDP SW status and HW status" drm/amd/display: take dpms_off into account for edp turn off logic Eryk Brol (2): drm/amd/display: Restructure DCN10 hubbub drm/amd/display: Introduce DC VM interface Fatemeh Darbehani (1): drm/amd/display: Add Vline1 interrupt source to InterruptManager John Barberiz (1): drm/amd/display: Fix use of uninitialized union Josip Pavic (3): drm/amd/display: Update DMCU versioning mechanism drm/amd/display: Create switching mechanism for ABM 2.2 drm/amd/display: Adjust ABM 2.2 contrast parameters Krunoslav Kovac (1): drm/amd/display: Default to linear output gamma Martin Tsai (1): drm/amd/display: Poll pending down rep before clear payload allocation table Nicholas Kazlauskas (2): drm/amd/display: Enable vblank interrupt during CRC capture drm/amd/display: Re-enable CRC capture following modeset Steven Chiu (1): drm/amd/display: 3.2.15 hersen wu (1): drm/amd/display: Connect dig_fe to otg directly instead of calling bios drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 583 +--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 48 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 7 + drivers/gpu/drm/amd/display/dc/Makefile| 3 +- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 14 - drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 16 - .../drm/amd/display/dc/bios/bios_parser_helper.c | 93 .../drm/amd/display/dc/bios/bios_parser_helper.h | 4 - .../gpu/drm/amd/display/dc/bios/command_table.c| 116 .../gpu/drm/amd/display/dc/bios/command_table.h| 3 - .../gpu/drm/amd/display/dc/bios/command_table2.c | 70 --- .../gpu/drm/amd/display/dc/bios/command_table2.h | 3 - drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 127 + drivers/gpu/drm/amd/display/dc/dc.h| 2 +- drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 9 - drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 + drivers/gpu/drm/amd/display/dc/dc_stream.h | 14 +- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +- .../drm/amd/display/dc/dce/dce_stream_encoder.c| 10 +- .../drm/amd/display/dc/dce/dce_stream_encoder.h| 8 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c| 81 +-- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 131 +++-- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h| 23 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 5 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 72 +-- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 12 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 9 +- .../amd/display/dc/dcn10/dcn10_stream_encoder.c| 9 + .../amd/display/dc/dcn10/dcn10_stream_encoder.h| 10 +- drivers/gpu/drm/amd/display/dc/dm_helpers.h| 7 + drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 4 + drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 +- .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 4 + .../drm/amd/display/dc/inc/hw/timing_generator.h | 13 +- drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h | 49 ++ drivers/gpu/drm/amd/display/dc/inc/vm_helper.h | 55 ++ drivers/gpu/drm/amd/display/dc/irq_types.h | 8 + .../drm/amd/display/modules/color/color_gamma.c| 73 +-- .../drm/amd/display/modules/power/power_helpers.c | 592 +++-- 45 files changed, 1229 insertions(+), 1100 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h create mode 100644 drivers/gpu/drm/amd/display/dc/inc/vm_helper.h -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/20] drm/amd/display: Restructure DCN10 hubbub
From: Eryk Brol
[Why]
Change DCN10 hubbub to use hubbub as a base and allow all future DCN
hubbubs to do the same instead of using DCN10_hubbub. This increases
readability and doesn't require future hubbubs to inherit anything
other than the base hubbub struct.
[How]
Create separate DCN10_hubbub struct which uses the hubbub struct as
a base.
Signed-off-by: Eryk Brol
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 131 -
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h| 9 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 4 +
4 files changed, 88 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index eb31a5e..5a4614c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -29,19 +29,20 @@
#include "reg_helper.h"
#define CTX \
- hubbub->ctx
+ hubbub1->base.ctx
#define DC_LOGGER \
- hubbub->ctx->logger
+ hubbub1->base.ctx->logger
#define REG(reg)\
- hubbub->regs->reg
+ hubbub1->regs->reg
#undef FN
#define FN(reg_name, field_name) \
- hubbub->shifts->field_name, hubbub->masks->field_name
+ hubbub1->shifts->field_name, hubbub1->masks->field_name
void hubbub1_wm_read_state(struct hubbub *hubbub,
struct dcn_hubbub_wm *wm)
{
+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
struct dcn_hubbub_wm_set *s;
memset(wm, 0, sizeof(struct dcn_hubbub_wm));
@@ -89,12 +90,14 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub)
{
+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0);
}
bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
{
+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
uint32_t enable = 0;
REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
@@ -107,6 +110,8 @@ bool hububu1_is_allow_self_refresh_enabled(struct hubbub
*hubbub)
bool hubbub1_verify_allow_pstate_change_high(
struct hubbub *hubbub)
{
+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
/* pstate latency is ~20us so if we wait over 40us and pstate allow
* still not asserted, we are probably stuck and going to hang
*
@@ -193,7 +198,7 @@ bool hubbub1_verify_allow_pstate_change_high(
* 31:SOC pstate change request
*/
- REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);
+ REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate);
for (i = 0; i < pstate_wait_timeout_us; i++) {
debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
@@ -244,6 +249,8 @@ static uint32_t convert_and_clamp(
void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
{
+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
}
@@ -254,7 +261,9 @@ void hubbub1_program_watermarks(
unsigned int refclk_mhz,
bool safe_to_lower)
{
- uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;
+ struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
+ uint32_t force_en = hubbub1->base.ctx->dc->debug.disable_stutter ? 1 :
0;
/*
* Need to clamp to max of the register values (i.e. no wrap)
* for dcn1, all wm registers are 21-bit wide
@@ -264,8 +273,8 @@ void hubbub1_program_watermarks(
/* Repeat for water mark set A, B, C and D. */
/* clock state A */
- if (safe_to_lower || watermarks->a.urgent_ns >
hubbub->watermarks.a.urgent_ns) {
- hubbub->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
+ if (safe_to_lower || watermarks->a.urgent_ns >
hubbub1->watermarks.a.urgent_ns) {
+ hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
refclk_mhz, 0x1f);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
@@ -276,8 +285,8 @@ void hubbub1_program_watermarks(
}
if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) {
- if (safe_to_lower || watermarks->a.pte_meta_urgent_ns >
hubbub->watermarks.a.pte_meta_urgent_ns) {
- hubbub->watermarks.a.pte_meta_urgent_ns =
watermarks->a.pte_meta_urgent_ns;
+ if (safe_to_lower || watermarks->a.pte_meta_urgent_ns >
hubbub1->watermarks.a.pte_meta_urgent_ns) {
+
[PATCH 03/20] drm/amd/display: Simplify underscan and ABM commit
From: David Francis
[Why]
Underscan and ABM are connector properties but require updates
to DC stream state. Previously, on updates to these properties
the affected stream and all its planes were committed.
This is unnecessary; only a few fields on the stream need
to be changed.
[How]
If scaling or ABM have changed, change the stream and
create a stream update with those changes. Call
DC with only those fields.
Signed-off-by: David Francis
Reviewed-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 49 ++-
1 file changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5298a13..405c263 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5262,11 +5262,13 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
}
}
- /* Handle scaling, underscan, and abm changes*/
+ /* Handle connector state changes */
for_each_oldnew_connector_in_state(state, connector, old_con_state,
new_con_state, i) {
struct dm_connector_state *dm_new_con_state =
to_dm_connector_state(new_con_state);
struct dm_connector_state *dm_old_con_state =
to_dm_connector_state(old_con_state);
struct amdgpu_crtc *acrtc =
to_amdgpu_crtc(dm_new_con_state->base.crtc);
+ struct dc_surface_update dummy_updates[MAX_SURFACES] = { 0 };
+ struct dc_stream_update stream_update = { 0 };
struct dc_stream_status *status = NULL;
if (acrtc) {
@@ -5278,37 +5280,48 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
continue;
-
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
- /* Skip anything that is not scaling or underscan changes */
if (!is_scaling_state_different(dm_new_con_state,
dm_old_con_state) &&
(dm_new_crtc_state->abm_level ==
dm_old_crtc_state->abm_level))
continue;
-
update_stream_scaling_settings(_new_con_state->base.crtc->mode,
- dm_new_con_state, (struct dc_stream_state
*)dm_new_crtc_state->stream);
+ if (is_scaling_state_different(dm_new_con_state,
dm_old_con_state)) {
+
update_stream_scaling_settings(_new_con_state->base.crtc->mode,
+ dm_new_con_state, (struct
dc_stream_state *)dm_new_crtc_state->stream);
- if (!dm_new_crtc_state->stream)
- continue;
+ stream_update.src = dm_new_crtc_state->stream->src;
+ stream_update.dst = dm_new_crtc_state->stream->dst;
+ }
+
+ if (dm_new_crtc_state->abm_level !=
dm_old_crtc_state->abm_level) {
+ dm_new_crtc_state->stream->abm_level =
dm_new_crtc_state->abm_level;
+
+ stream_update.abm_level = _new_crtc_state->abm_level;
+ }
status = dc_stream_get_status(dm_new_crtc_state->stream);
WARN_ON(!status);
WARN_ON(!status->plane_count);
- dm_new_crtc_state->stream->abm_level =
dm_new_crtc_state->abm_level;
+ /*
+* TODO: DC refuses to perform stream updates without a
dc_surface_update.
+* Here we create an empty update on each plane.
+* To fix this, DC should permit updating only stream
properties.
+*/
+ for (j = 0; j < status->plane_count; j++)
+ dummy_updates[j].surface = status->plane_states[0];
- /*TODO How it works with MPO ?*/
- if (!commit_planes_to_stream(
- dm,
- dm->dc,
- status->plane_states,
- status->plane_count,
- dm_new_crtc_state,
- to_dm_crtc_state(old_crtc_state),
- dc_state))
- dm_error("%s: Failed to update stream scaling!\n",
__func__);
+
+ mutex_lock(>dc_lock);
+ dc_commit_updates_for_stream(dm->dc,
+dummy_updates,
+status->plane_count,
+dm_new_crtc_state->stream,
+_update,
+
[PATCH 02/20] drm/amd/display: Introduce DC VM interface
From: Eryk Brol
Virtual memory allows display to support flipping to surfaces which
are not allocated contiguously in memory with physical addresses,
instead a 1-4 level page table is used.
This is beneficial because it allows the scattering of large surfaces
to improve memory efficiency and security.
Signed-off-by: Eryk Brol
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/Makefile| 3 +-
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 127 +
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h| 14 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 5 -
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 +-
drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h | 49
drivers/gpu/drm/amd/display/dc/inc/vm_helper.h | 55 +
10 files changed, 254 insertions(+), 10 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/vm_helper.h
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index fa24e4c..b8ddb4a 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -41,7 +41,8 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix
$(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI
include $(AMD_DC)
DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
-dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
+dc_vm_helper.o
AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
new file mode 100644
index 000..e54b8ac
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "vm_helper.h"
+
+static void mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos,
uint8_t hubp_idx)
+{
+ struct vmid_usage vmids = vm_helper->hubp_vmid_usage[hubp_idx];
+
+ vmids.vmid_usage[0] = vmids.vmid_usage[1];
+ vmids.vmid_usage[1] = 1 << pos;
+}
+
+static void add_ptb_to_table(struct vm_helper *vm_helper, unsigned int vmid,
uint64_t ptb)
+{
+ vm_helper->ptb_assigned_to_vmid[vmid] = ptb;
+ vm_helper->num_vmids_available--;
+}
+
+static void clear_entry_from_vmid_table(struct vm_helper *vm_helper, unsigned
int vmid)
+{
+ vm_helper->ptb_assigned_to_vmid[vmid] = 0;
+ vm_helper->num_vmids_available++;
+}
+
+static void evict_vmids(struct vm_helper *vm_helper)
+{
+ int i;
+ uint16_t ord = 0;
+
+ for (i = 0; i < vm_helper->num_vmid; i++)
+ ord |= vm_helper->hubp_vmid_usage[i].vmid_usage[0] |
vm_helper->hubp_vmid_usage[i].vmid_usage[1];
+
+ // At this point any positions with value 0 are unused vmids, evict them
+ for (i = 1; i < vm_helper->num_vmid; i++) {
+ if (ord & (1u << i))
+ clear_entry_from_vmid_table(vm_helper, i);
+ }
+}
+
+// Return value of -1 indicates vmid table unitialized or ptb dne in the table
+static int get_existing_vmid_for_ptb(struct vm_helper *vm_helper, uint64_t ptb)
+{
+ int i;
+
+ for (i = 0; i < vm_helper->num_vmid; i++) {
+ if (vm_helper->ptb_assigned_to_vmid[i] == ptb)
+ return i;
+ }
+
+ return -1;
+}
+
+// Expected to be called only when there's an available
[ANNOUNCE] libdrm 2.4.97
-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 Alex Deucher (1): amdgpu: update to latest marketing names from 18.50 Andrey Grodzovsky (3): amdgpu/test: Add illegal register and memory access test v2 amdgpu/test: Disable deadlock tests for all non gfx8/9 ASICs. amdgpu/test: Enable deadlock test for CI family (gfx7) Christian König (1): amdgpu: add VM test to exercise max/min address space Daniel Vetter (1): doc: Rename README to .rst Eric Anholt (2): Avoid hardcoded strlens in drmParseSubsystemType(). drm: Attempt to parse SPI devices as platform bus devices. Eric Engestrom (6): xf86drmHash: remove unused loop variable meson: fix typo in compiler flag tests: skip drmdevice test if the machine doesn't have any drm device freedreno: remove always-defined #ifdef xf86atomic: #undef internal define README: reflow the project description to improve readability François Tigeot (2): xf86drm: implement drmParseSubsystemType for DragonFly libdrm: Use DRM_IOCTL_GET_PCIINFO on DragonFly Leo Liu (1): tests/amdgpu/vcn: fix the nop command in IBs Lucas De Marchi (2): gitignore: sort file gitignore: add _build Marek Olšák (3): amdgpu: update amdgpu_drm.h amdgpu: add a faster BO list API Bump the version to 2.4.97 Mauro Rossi (1): android: Fix 32-bit app crashing in 64-bit Android git tag: libdrm-2.4.97 https://dri.freedesktop.org/libdrm/libdrm-2.4.97.tar.bz2 MD5: acef22d0c62c89692348c2dd5591393e libdrm-2.4.97.tar.bz2 SHA1: 7635bec769a17edd140282fa2c46838c4a44bc91 libdrm-2.4.97.tar.bz2 SHA256: 77d0ccda3e10d6593398edb70b1566bfe1a23a39bd3da98ace2147692eadd123 libdrm-2.4.97.tar.bz2 SHA512: 3e08ee9d6c9ce265d783a59b51e22449905ea73aa27f25a082a1e9e1532f7c99e1c9f7cb966eb0970be2a08e2e5993dc9aa55093b1bff548689fdb465e7145ed libdrm-2.4.97.tar.bz2 PGP: https://dri.freedesktop.org/libdrm/libdrm-2.4.97.tar.bz2.sig https://dri.freedesktop.org/libdrm/libdrm-2.4.97.tar.gz MD5: a8bb09d6f4ed28191ba6e86e788dc3a4 libdrm-2.4.97.tar.gz SHA1: af778f72d716589e9eacec9336bafc81b447cc42 libdrm-2.4.97.tar.gz SHA256: 8c6f4d0934f5e005cc61bc05a917463b0c867403de176499256965f6797092f1 libdrm-2.4.97.tar.gz SHA512: 9a7130ab5534555d7cf5ff95ac761d2cd2fe2c44eb9b63c7ad3f9b912d0f13f1e3ff099487d8e90b08514329c61adb4e73fe25404e7c2f4c26b205c64be8d114 libdrm-2.4.97.tar.gz PGP: https://dri.freedesktop.org/libdrm/libdrm-2.4.97.tar.gz.sig -BEGIN PGP SIGNATURE- iQEyBAEBCgAdFiEEzUfFNBo3XzO+97r6/dFdWs7w8rEFAlxHR3sACgkQ/dFdWs7w 8rEg/Af3d1I0DnABd0j3GUTxUAfHn7/yYkyFunFmqD9tmhdZZ8rl+PzXMocEhtDz dn+lrG3JHhj4O0istZBe0B8oZIyCuSk+36j5t3XEgR1SfF5YlDhXnlEMaPuJQerr ZrdXsggmQyv1BjeaLcseHM4wdnbkcClSoHXCNqbKQLPOyS0r0xEj0Ft6QvtDfPxh rpCMdNjIPSFhBiJqyFuaHw6dWbX1elzSIjtXpdBOYrf7mfF/laE6OX7p+P7LtwC4 PkoeuzdHqt77iGASBoQI28XfVGpfQvBrTzDI4xRGI9IGXyc5oeJuk0uTnVjT3A9I zHocD5j8r4pQJdfb49RQzyPOaxvF =Lxi8 -END PGP SIGNATURE- ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add APTX quirk for Lenovo laptop
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v4.20.3, v4.19.16, v4.14.94, v4.9.151,
v4.4.171, v3.18.132.
v4.20.3: Build OK!
v4.19.16: Build OK!
v4.14.94: Failed to apply! Possible dependencies:
Unable to calculate
v4.9.151: Failed to apply! Possible dependencies:
b3fc2ab37e27 ("drm/amdgpu: add another ATPX quirk for TOPAZ")
v4.4.171: Failed to apply! Possible dependencies:
052c299080cd ("drm/amdgpu: add atpx quirk handling (v2)")
1db4496f167b ("drm/amdgpu: fix power state when port pm is unavailable")
2f5af82eeab2 ("drm/amdgpu/atpx: track whether if this is a hybrid graphics
platform")
5c614792474b ("drm/amdgpu: disable power control on hybrid laptops")
6b1095eedd39 ("drm/amdgpu: init atpx at switcheroo register time (v2)")
6c24a85d236e ("drm/amdgpu: add new device to use atpx quirk")
7ac33e47d576 ("drm/amdgpu: fix check for port PM availability")
8d45f80ed08b ("drm/amdgpu: clean up atpx power control handling")
a78fe13389f0 ("drm/amdgpu/atpx: add a query for ATPX dGPU power control")
b3fc2ab37e27 ("drm/amdgpu: add another ATPX quirk for TOPAZ")
c8791a13d281 ("drm/amdgpu: print a message if ATPX dGPU power control is
missing")
v3.18.132: Failed to apply! Possible dependencies:
052c299080cd ("drm/amdgpu: add atpx quirk handling (v2)")
1db4496f167b ("drm/amdgpu: fix power state when port pm is unavailable")
2f5af82eeab2 ("drm/amdgpu/atpx: track whether if this is a hybrid graphics
platform")
5c614792474b ("drm/amdgpu: disable power control on hybrid laptops")
6c24a85d236e ("drm/amdgpu: add new device to use atpx quirk")
7ac33e47d576 ("drm/amdgpu: fix check for port PM availability")
8d45f80ed08b ("drm/amdgpu: clean up atpx power control handling")
97b2e202fba0 ("drm/amdgpu: add amdgpu.h (v2)")
a78fe13389f0 ("drm/amdgpu/atpx: add a query for ATPX dGPU power control")
b3fc2ab37e27 ("drm/amdgpu: add another ATPX quirk for TOPAZ")
bedf2a65c1aa ("drm/amdgpu: disable runtime pm on PX laptops without dGPU
power control")
c8791a13d281 ("drm/amdgpu: print a message if ATPX dGPU power control is
missing")
d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
e9bef455af8e ("Revert "drm/amdgpu: disable runtime pm on PX laptops without
dGPU power control"")
How should we proceed with this patch?
--
Thanks,
Sasha
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Re: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86
On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote: > > On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote: > > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote: > >> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote: > >>> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote: > On 2019-01-21 6:59 p.m., Ard Biesheuvel wrote: > > On Mon, 21 Jan 2019 at 18:55, Michel Dänzer wrote: > >> On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote: > >>> On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig > >>> wrote: > >>> > Until that happens we should just change the driver ifdefs to default > the hacks to off and only enable them on setups where we 100% > positively know that they actually work. And document that fact > in big fat comments. > >>> > >>> Well, as I mentioned in my commit log as well, if we default to off > >>> unless CONFIG_X86, we may break working setups on MIPS and Power where > >>> the device is in fact non-cache coherent, and relies on this > >>> 'optimization' to get things working. > >> > >> FWIW, the amdgpu driver doesn't rely on non-snooped transfers for > >> correct basic operation (the scenario Christian brought up is a very > >> specialized use-case), so that shouldn't be an issue. > > > > The point is that this is only true for x86. > > > > On other architectures, the use of non-cached mappings on the CPU side > > means that you /do/ rely on non-snooped transfers, since if those > > transfers turn out not to snoop inadvertently, the accesses are > > incoherent with the CPU's view of memory. > > The driver generally only uses non-cached mappings if > drm_arch/device_can_wc_memory returns true. > >>> > >>> Indeed. And so we should take care to only return 'true' from that > >>> function if it is guaranteed that non-cached CPU mappings are coherent > >>> with the mappings used by the GPU, either because that is always the > >>> case (like on x86), or because we know that the platform in question > >>> implements NoSnoop correctly throughout the interconnect. > >>> > >>> What seems to be complicating matters is that in some cases, the > >>> device is non-cache coherent to begin with, so regardless of whether > >>> the NoSnoop attribute is used or not, those accesses will not snoop in > >>> the caches and be coherent with the non-cached mappings used by the > >>> CPU. So if we restrict this optimization [on non-X86] to platforms > >>> that are known to implement NoSnoop correctly, we may break platforms > >>> that are implicitly NoSnoop all the time. > >> > >> Since the driver generally doesn't rely on non-snooped accesses for > >> correctness, that couldn't "break" anything that hasn't always been broken. > > > > Again, that is only true on x86. > > > > On other architectures, DMA writes from the device may allocate in the > > caches, and be invisible to the CPU when it uses non-cached mappings. > > Let me try one last time: > > If drm_arch_can_wc_memory returns false, the driver falls back to the > normal mode of operation, using a cacheable CPU mapping and snooped GPU > transfers, even if userspace asks (as a performance optimization) for a > write-combined CPU mapping and non-snooped GPU transfers via > AMDGPU_GEM_CREATE_CPU_GTT_USWC. Another question: when userspace requests for such a mapping to be created, does this involve pages that are mapped cacheable into the userland process? ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: sriov put csa below AMDGPU_GMC_HOLE
since vm_size enlarged to 0x4 GB,
sriov need to put csa below AMDGPU_GMC_HOLE.
or amdgpu_vm_alloc_pts would receive saddr among AMDGPU_GMC_HOLE,
and result in a range fault interrupt IIRC.
Change-Id: I405a25a01d949f3130889b346f71bedad8ebcae7
Signed-off-by: Wenta Lou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 --
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index dd3bd01..7a93c36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -26,8 +26,10 @@
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
- uint64_t addr = min(adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT,
- AMDGPU_GMC_HOLE_START);
+ uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
+ /* sriov put csa below AMDGPU_GMC_HOLE */
+ if (amdgpu_sriov_vf(adev))
+ addr = min(addr, AMDGPU_GMC_HOLE_START);
addr -= AMDGPU_VA_RESERVED_SIZE;
addr = amdgpu_gmc_sign_extend(addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f87f717..cf9ec28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -707,8 +707,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
vm_size = min(vm_size, 1ULL << 40);
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
- dev_info.virtual_address_max =
- min(vm_size, AMDGPU_GMC_HOLE_START);
+ if (amdgpu_sriov_vf(adev))
+ dev_info.virtual_address_max = min(vm_size,
AMDGPU_GMC_HOLE_START - AMDGPU_VA_RESERVED_SIZE);
+ else
+ dev_info.virtual_address_max = min(vm_size,
AMDGPU_GMC_HOLE_START);
if (vm_size > AMDGPU_GMC_HOLE_START) {
dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
--
2.7.4
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Re: [PATCH] drm/amdgpu: add a workaround for GDS ordered append hangs with compute queues
Am 22.01.19 um 00:46 schrieb Marek Olšák:
From: Marek Olšák
I'm not increasing the DRM version because GDS isn't totally without bugs yet.
Looks mostly good on first glance.
But one things that is certainly wrong is when you add any
amdgpu_ring_write() call to the emit_ibs callback you also need to
update the estimation on how many DW can be used by an IB.
Look out for the structure where the gfx_*_ring_emit_ib is used.
Regards,
Christian.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 17
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 +
include/uapi/drm/amdgpu_drm.h | 5
5 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
index ecbcefe49a98..f89f5734d985 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
@@ -30,20 +30,22 @@ struct amdgpu_bo;
struct amdgpu_gds_asic_info {
uint32_ttotal_size;
uint32_tgfx_partition_size;
uint32_tcs_partition_size;
};
struct amdgpu_gds {
struct amdgpu_gds_asic_info mem;
struct amdgpu_gds_asic_info gws;
struct amdgpu_gds_asic_info oa;
+ uint32_tgds_compute_max_wave_id;
+
/* At present, GDS, GWS and OA resources for gfx (graphics)
* is always pre-allocated and available for graphics operation.
* Such resource is shared between all gfx clients.
* TODO: move this operation to user space
* */
struct amdgpu_bo* gds_gfx_bo;
struct amdgpu_bo* gws_gfx_bo;
struct amdgpu_bo* oa_gfx_bo;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 7984292f9282..d971ea914755 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2257,20 +2257,36 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct
amdgpu_ring *ring,
}
static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
struct amdgpu_job *job,
struct amdgpu_ib *ib,
uint32_t flags)
{
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
+ /* Currently, there is a high possibility to get wave ID mismatch
+* between ME and GDS, leading to a hw deadlock, because ME generates
+* different wave IDs than the GDS expects. This situation happens
+* randomly when at least 5 compute pipes use GDS ordered append.
+* The wave IDs generated by ME are also wrong after suspend/resume.
+* Those are probably bugs somewhere else in the kernel driver.
+*
+* Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
+* GDS to 0 for this ring (me/pipe).
+*/
+ if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID -
PACKET3_SET_CONFIG_REG_START);
+ amdgpu_ring_write(ring,
ring->adev->gds.gds_compute_max_wave_id);
+ }
+
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
amdgpu_ring_write(ring,
#ifdef __BIG_ENDIAN
(2 << 0) |
#endif
(ib->gpu_addr & 0xFFFC));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0x);
amdgpu_ring_write(ring, control);
}
@@ -5050,20 +5066,21 @@ static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
adev->gfx.priv_inst_irq.num_types = 1;
adev->gfx.priv_inst_irq.funcs = _v7_0_priv_inst_irq_funcs;
}
static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
{
/* init asci gds info */
adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
adev->gds.gws.total_size = 64;
adev->gds.oa.total_size = 16;
+ adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
if (adev->gds.mem.total_size == 64 * 1024) {
adev->gds.mem.gfx_partition_size = 4096;
adev->gds.mem.cs_partition_size = 4096;
adev->gds.gws.gfx_partition_size = 4;
adev->gds.gws.cs_partition_size = 4;
adev->gds.oa.gfx_partition_size = 4;
adev->gds.oa.cs_partition_size = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a26747681ed6..dcdae74fc0e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++
Re: [PATCH] drm: Split out drm_probe_helper.h
On Mon, Jan 21, 2019 at 11:13 PM Sam Ravnborg wrote: > > Hi Daniel et al. > > > > > > > Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy > > > kms drivers. Just removing it from all the atomic drivers caused lots of > > > fallout, I expect even more if you entirely remove the includes it has. > > > Maybe a todo, care to pls create that patch since it's your idea? > > > > The main reason I bailed out initially was that this would create > > small changes to several otherwise seldomly touched files. > > And then we would later come and remove drmP.h - so lots of > > small but incremental changes to the same otherwise seldomly > > edited files. > > And the job was only partially done. > > > > I will try to experiment with an approach where I clean up the > > include/drm/*.h files a little (like suggested above, +delete drmP.h > > and maybe a bit more). > > > > Then to try on a driver by driver basis to make it build with a > > cleaned set of include files. > > I hope that the cleaned up driver can still build without the > > cleaned header files so the changes can be submitted piecemal. > > > > Will do so with an eye on the lesser maintained drivers to try it > > out to avoid creating too much chrunch for others. > > I have now a few patches queued, but the result is not too pretty. > I did the following: > > - For all files in include/drm/*.h the set of include files > were adjusted to the minimum number of files required to make > them build without any other files included first. > > Created one .c file for each .h file. Then included the .h > file and adjusted to the minimal set of include files. > In the process a lot of forwards were added. > > - Deleted drmP.h > > - Fixed build of a few drivers: sti, tilcdc, gma500, tve200, via > > Some observations: > > - Killing all the includes not needed in the headers files > results in a a lot of extra changes. > Examples: > drm_modseset_helper_vtables.h is no longer > included by anyone, so needs to be added in many files > > drm_atomic_state_helper.h is no longer included > by anyone so likewise needs to be added in many files > > - It is very tedious to do this properly. > The process I followed was: > - delete / comment out all include files > - add back the obvious from a quick scan of the code > - build - fix - build - fix - build - fix ... > - next file... > > - The result is errorprone as only the allyesconfig + allmodconfig > variants are tested. But reallife configurations are more diverse. > > Current diffstat: >111 files changed, 771 insertions(+), 401 deletions(-) > > This is for the 5 drivers alone and not the header cleanup. > So long story short - this is not good and not the way forward. > > I will try to come up with a few improvements to make the > headers files selfcontained, but restricted to the changes that > add forwards/include to avoid the chrunch in all the drivers. > > And then post for review a few patches to clean up some headers. > If the cleanup gets a go I will try to persuade the introduction > of these. > This will include, but will not be limited to, the above mentioned > drm_crtc_helper.h header file. > > For now too much time was already spent on this, so it is at the > moment pushed back on my TODO list. > This mail serve also as a kind of "where had I left", when/if I > pick this up again. > > If there are anyone that knows some tooling that can help in the > process of adjusting the header files I am all ears. Yeah in the process of splitting up drmP.h we've created a few smaller such piles of headers. I think in some cases it's just not going to be worth it to fully split them up, e.g. drm_crtc_helper.h is going to be a pure legacy helper, only needed by pre-atomic drivers. Splitting that up doesn't seem to useful to me. Similarly we might want drm_atomic_helper.h to keep pulling in the other helper headers. So probably going to be a judgement call on a case-by-case basis. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
