maybe just:
amdgpu.lockup_timeout=
I don't think we really need separate timeouts for all the different video
related engines.
Alex
From: Quan, Evan
Sent: Sunday, April 28, 2019 1:37 AM
To: Deucher, Alexander; Michel Dänzer; Koenig, Christian
Cc: Xu, Feifei;
From: Colin Ian King
Currently an allocation is being made but the allocation failure
check is being performed on another pointer. Fix this by checking
the correct pointer. Also use the normal kernel idiom for null
pointer checks.
Addresses-Coverity: ("Resource leak")
Fixes: 43e3ac8389ef
Hello,
I experience a bug that prevents me from setting the MCLK of my Vega 64
LC above 1107MHz.
I am using Unigine Superposition 1.1 in "Game"-mode to check the
performance by watching the FPS.
*Behaviour with a single monitor:*
First I set the MCLK to a known stable value below
On Tue, 16 Apr 2019, Christian K??nig wrote:
> To allow a smooth transition from pinning buffer objects to dynamic
> invalidation we first start to cache the sg_table for an attachment
> unless the driver explicitly says to not do so.
>
> ---
> drivers/dma-buf/dma-buf.c | 24
In amdgpu open path, CSA will be mappened in VM, so when opening
KFD, calling mdgpu_vm_make_compute will fail because it found this
VM is not a clean VM with some mappings, as a result, it will lead
to failed to create process VM object
The fix is try to unmap CSA, and actually CSA is not needed
From: Jay Cornwall
When MEM_VIOL is asserted the context save handler rewinds the
program counter. This is incorrect for any source of the exception.
MEM_VIOL may be raised in normal operation by out-of-bounds access
to LDS or GDS and does not require special handling.
Remove PC adjustment when
Fix a circular lock dependency exposed under userptr memory pressure.
The DQM lock is the only one taken inside the MMU notifier. We need
to make sure that no reclaim is done under this lock, and that
no other locks are taken under which reclaim is possible.
Signed-off-by: Felix Kuehling
From: Yong Zhao
This avoids duplicated code.
Signed-off-by: Yong Zhao
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 29 +++
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git
From: Jay Cornwall
ttmp[4:5] is initialized by the SPI with SPI_GDBG_TRAP_DATA* values.
These values are more useful to the debugger than ttmp[14:15], which
carries dispatch_scratch_base*. There are too few registers to
preserve both.
Signed-off-by: Jay Cornwall
Reviewed-by: Felix Kuehling
From: shaoyunl
There is a bug found in vml2 xgmi logic:
mtype is always sent as NC on the VMC to TC interface for a page walk,
regardless of whether the request is being sent to local or remote GPU.
NC means non-coherent and will cause the VMC return data to be cached
in the TCC (versus UC –
From: Oak Zeng
Existing QUEUE_TYPE_SDMA means PCIe optimized SDMA queues.
Introduce a new QUEUE_TYPE_SDMA_XGMI, which is optimized
for non-PCIe transfer such as XGMI.
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
From: Oak Zeng
MEC FW for some new asic requires all SDMA MQDs to be in a continuous
trunk of memory right after HIQ MQD. Add a field in device queue manager
to hold the HIQ/SDMA MQD memory object and allocate MQD trunk on device
queue manager initialization.
Signed-off-by: Oak Zeng
From: Jay Cornwall
If instruction fetch fails the wave cannot be halted and returned to
the shader without raising MEM_VIOL again. Currently the wave is
terminated if this occurs, but this loses information about the cause
of the fault. The debugger would prefer the faulting wave state to be
From: Oak Zeng
Instead of allocat hiq and sdma mqd from sub-allocator, allocate
them from a mqd trunk pool. This is done for all asics
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 49 +++
From: Oak Zeng
sdma_queue_id is sdma queue index inside one sdma engine.
sdma_id is sdma queue index among all sdma engines. Use
those two names properly.
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
From: Oak Zeng
Maximumly support 64 sdma queues
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 10 +-
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +-
2 files changed, 6
From: Oak Zeng
With introduction of new mqd allocation scheme for HIQ,
DIQ and HIQ use different mqd allocation scheme, DIQ
can't reuse HIQ mqd manager
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
From: Oak Zeng
Free mqd_mem_obj it GTT buffer allocation for MQD+control stack fails.
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
From: Oak Zeng
Add debug messages during SDMA queue allocation.
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Kent Russell
GTT size is currently limited to the minimum of VRAM size or 3/4 of
system memory. This severely limits the quanitity of system memory
that can be used by ROCm application.
Increase GTT size to the maximum of VRAM size or system memory size.
Signed-off-by: Kent Russell
From: Amber Lin
A multi-socket server can have multiple PCIe segments so BFD is not enough
to distingush each GPU. Also add domain number into account when generating
gpu_id.
Signed-off-by: Amber Lin
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
From: Oak Zeng
Alloc format was never really supported by MEC FW. FW always
does one per pipe allocation.
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 2 --
From: Oak Zeng
This is preparation work to introduce more mqd allocation
scheme
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 20 ++--
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 51
Assorted KFD changes that have been accumulating on amd-kfd-staging. New
features and fixes included:
* Support for VegaM
* Support for systems with multiple PCI domains
* New SDMA queue type that's optimized for XGMI links
* SDMA MQD allocation changes to support future ASICs with more SDMA
From: Oak Zeng
FW of some new ASICs requires sdma mqd size to be not more than
128 dwords. Repurpose the last 2 reserved fields of sdma mqd for
driver internal use, so the total mqd size is no bigger than 128
dwords
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix
From: Oak Zeng
Also initialize mqd size on mqd manager initialization
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4
From: Kent Russell
Add the VegaM information to KFD
Signed-off-by: Kent Russell
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 +++
From: Oak Zeng
Global function mqd_manager_init just calls asic-specific functions and it
is not necessary. Delete it and introduce a mqd_manager_init interface in
dqm for asic-specific mqd manager init. Call mqd_manager_init interface
directly to initialize mqd manager
Signed-off-by: Oak Zeng
From: Oak Zeng
Expose available numbers of both SDMA queue types in the topology.
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 7 +++
drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 2 ++
2 files changed, 9
From: Oak Zeng
Previously mqd managers was initialized on demand. As there
are only a few type of mqd managers, the on demand initialization
doesn't save too much memory. Initialize them on device
queue initialization instead and delete the get_mqd_manager
interface. This makes codes more
From: Jay Cornwall
SQ_WAVE_IB_STS.RCNT grew from 4 bits to 5 in gfx9. Do not truncate
when saving in the high bits of TTMP1.
Signed-off-by: Jay Cornwall
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 12 ++--
From: Oak Zeng
Previous codes assumes there are two sdma engines.
This is not true e.g., Raven only has 1 SDMA engine.
Fix the issue by using sdma engine number info in
device_info.
Signed-off-by: Oak Zeng
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
From: Harish Kasiviswanathan
Fix compute profile switching on process termination.
Add a dedicated reference counter to keep track of entry/exit to/from
compute profile. This enables switching compute profiles for other
reasons than process creation or termination.
Signed-off-by: Harish
33 matches
Mail list logo