Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Xu, Feifei
Sent: Friday, July 26, 2019 12:20 PM
To: Alex Deucher ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu/powerplay: use proper revision id
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, July 26, 2019 12:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/powerplay: use proper revision id for navi
The PCI revision id determines the
The PCI revision id determines the sku.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index
I think that's ok to put in sw_init.
Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Quan,
Evan
Sent: Friday, July 26, 2019 9:04 AM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/2]
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 29 +++
1 file changed, 29 insertions(+)
diff --git
Navi uses either mode1 or baco depending on various
conditions.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
When doing a GPU reset or unloading the driver, we need to
put the SMU into the apprpriate state for the re-init after
the reset or unload to reliably work.
I don't think this is necessary for BACO because the SMU actually
controls the BACO state to it needs to be active.
For suspend (S3), the
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git
VI always uses the legacy pci based reset.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index fffae4c2973b..56c882b3ea3c 100644
SI always uses the legacy pci based reset.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 4b1e0c16ac41..904361451650 100644
Sometimes the driver may have to behave differently depending
on the method we are using to reset the GPU.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git
This is required for certain cases such as various GPU resets
(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
the appropriate state for when the hw is re-initialized.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 8
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 25 +++
1 file changed, 25 insertions(+)
diff --git
APUs only support mode2 reset. dGPUs use either mode1 or
baco depending on various conditions.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
CIK always uses the legacy pci based reset.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 3a4f20766a39..7b63d7a8298a
On Thu, Jul 25, 2019 at 10:20 PM Quan, Evan wrote:
>
> Patch1 - patch11: Reviewed-by: Evan Quan
>
> For patch12, comment inline
>
> > -Original Message-
> > From: amd-gfx On Behalf Of Alex
> > Deucher
> > Sent: Friday, July 26, 2019 12:58 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc:
Patch1 - patch11: Reviewed-by: Evan Quan
For patch12, comment inline
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Friday, July 26, 2019 12:58 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 12/12] drm/amdgpu: put the SMC
It's a bug fix for uploading new pptable from sysfs.
And it's not hardware involved. The real hardware operation involved with this
is in smu_v11_0_enable_thermal_alert.
And in old powerplay routine, this is also put in sw_init and we do not find
any problem with that until now.
Regards,
Evan
From: Christoph Hellwig
Add a HMM_FAULT_SNAPSHOT flag so that hmm_range_snapshot can be merged
into the almost identical hmm_range_fault function.
Signed-off-by: Christoph Hellwig
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason Gunthorpe
---
Documentation/vm/hmm.rst | 17
hmm_range_fault() calls find_vma() and walk_page_range() in a loop.
This is unnecessary duplication since walk_page_range() calls find_vma()
in a loop already.
Simplify hmm_range_fault() by defining a walk_test() callback function
to filter unhandled vmas.
Signed-off-by: Ralph Campbell
Cc:
From: Christoph Hellwig
This allows easier expansion to other flags, and also makes the
callers a little easier to read.
Signed-off-by: Christoph Hellwig
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason Gunthorpe
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
walk_page_range() will only call hmm_vma_walk_hugetlb_entry() for
hugetlbfs pages and doesn't call hmm_vma_walk_pmd() in this case.
Therefore, it is safe to remove the check for vma->vm_flags & VM_HUGETLB
in hmm_vma_walk_pmd().
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason
A few more comments and minor programming style clean ups.
There should be no functional changes.
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason Gunthorpe
Cc: Christoph Hellwig
---
mm/hmm.c | 39 +--
1 file changed, 17 insertions(+), 22
Here are seven more patches for things I found to clean up.
This was based on top of Christoph's seven patches:
"hmm_range_fault related fixes and legacy API removal v3".
I assume this will go into Jason's tree since there will likely be
more HMM changes in this cycle.
Changes from v1 to v2:
The hmm_mirror_ops callback function sync_cpu_device_pagetables() passes
a struct hmm_update which is a simplified version of struct
mmu_notifier_range. This is unnecessary so replace hmm_update with
mmu_notifier_range directly.
Signed-off-by: Ralph Campbell
Reviewed: Christoph Hellwig
Cc:
Works perfectly here, and no warnings (at least not any that are relevant to
this patch series :) when reloading nouveau.
Reviewed-by: Lyude Paul
On Tue, 2019-07-23 at 19:28 -0400, sunpeng...@amd.com wrote:
> From: Leo Li
>
> Implement late_register and early_unregister hooks for MST
Noticed something! important note below
On Tue, 2019-07-23 at 19:28 -0400, sunpeng...@amd.com wrote:
> From: Ville Syrjälä
>
> All available downstream ports - physical and logical - are exposed for
> each MST device. They are listed in /dev/, following the same naming
> scheme as SST devices
On 2019-07-25 2:15 p.m., Thai, Thong wrote:
> VCN 2.0 firmware now requires a packet start command to be sent before
> any other decode ring buffer command.
>
> Signed-off-by: Thong Thai
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 32 ++-
> 1 file changed, 31
On 2019-07-25 2:15 p.m., Thai, Thong wrote:
> Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
> bit was previously set by the RBC HW on older firmware. Newer firmware
> uses a SW RBC and this bit has to be set by the driver.
>
> Signed-off-by: Thong Thai
> ---
>
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.
Signed-off-by: Thong Thai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
VCN 2.0 firmware now requires a packet start command to be sent before
any other decode ring buffer command.
Signed-off-by: Thong Thai
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 32 ++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git
On 7/25/19 1:57 PM, sunpeng...@amd.com wrote:
> From: Leo Li
>
> Using a static int array will cause errors if the given dm_pp_clk_type
> is out-of-bounds. For robustness, use a switch table, with a default
> case to handle all invalid values.
>
> v2: 0 is a valid clock type for smu_clk_type.
From: Leo Li
Using a static int array will cause errors if the given dm_pp_clk_type
is out-of-bounds. For robustness, use a switch table, with a default
case to handle all invalid values.
v2: 0 is a valid clock type for smu_clk_type. Return SMU_CLK_COUNT
instead on invalid mapping.
On 7/25/19 1:40 PM, sunpeng...@amd.com wrote:
> From: Leo Li
>
> Using a static int array will cause errors if the given dm_pp_clk_type
> is out-of-bounds. For robustness, use a switch table, with a default
> case to handle all invalid values.
>
> Signed-off-by: Leo Li
> ---
>
From: Leo Li
Using a static int array will cause errors if the given dm_pp_clk_type
is out-of-bounds. For robustness, use a switch table, with a default
case to handle all invalid values.
Signed-off-by: Leo Li
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 38 +--
1 file
On 2019-07-25 12:14 p.m., Kazlauskas, Nicholas wrote:
> On 7/25/19 12:00 PM, Li, Sun peng (Leo) wrote:
>>
>>
>> On 2019-07-18 11:16 p.m., Nathan Chancellor wrote:
>>> On Wed, Jul 03, 2019 at 10:52:16PM -0700, Nathan Chancellor wrote:
clang warns:
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 29 +++
1 file changed, 29 insertions(+)
diff --git
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git
SI always uses the legacy pci based reset.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 4b1e0c16ac41..904361451650 100644
CIK always uses the legacy pci based reset.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 3a4f20766a39..7b63d7a8298a
This is required for certain cases such as various GPU resets
(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
the appropriate state for when the hw is re-initialized.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 8
APUs only support mode2 reset. dGPUs use either mode1 or
baco depending on various conditions.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
VI always uses the legacy pci based reset.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index fffae4c2973b..56c882b3ea3c 100644
Navi uses either mode1 or baco depending on various
conditions.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
Suspend is used for S3/S4, GPU reset, and PCI shutdown. In
each case, we need to put the SMC into the proper state
in order to resume or reload correctly.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 ++
1 file changed, 33 insertions(+)
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 25 +++
1 file changed, 25 insertions(+)
diff --git
Sometimes the driver may have to behave differently depending
on the method we are using to reset the GPU.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git
When we are tearing down the device for PCI shutdown, set the
flag. The driver needs to know this case so it can set the
SMC into the proper state.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
2 files changed, 3
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.
Signed-off-by: Thong Thai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
On 7/25/19 12:00 PM, Li, Sun peng (Leo) wrote:
>
>
> On 2019-07-18 11:16 p.m., Nathan Chancellor wrote:
>> On Wed, Jul 03, 2019 at 10:52:16PM -0700, Nathan Chancellor wrote:
>>> clang warns:
>>>
>>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:336:8:
>>> warning: implicit
On 2019-07-18 11:16 p.m., Nathan Chancellor wrote:
> On Wed, Jul 03, 2019 at 10:52:16PM -0700, Nathan Chancellor wrote:
>> clang warns:
>>
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:336:8:
>> warning: implicit conversion from enumeration type 'enum smu_clk_type'
>> to
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.
Signed-off-by: Thong Thai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
VCN 2.0 firmware now requires a packet start command to be sent before
any other decode ring buffer command.
Signed-off-by: Thong Thai
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 32 ++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git
On 2019-07-25 4:24 p.m., Andrey Grodzovsky wrote:
> First patches fixes a hard hang introduced by placing the display BO in
> GTT memory because of HW issues with cached mappings. Second patch does
> some minor reafactoring to resue code in thrid patch. Third patch adds
> check for USWC support
On 7/25/19 10:24 AM, Andrey Grodzovsky wrote:
> From: Shirish S
>
> enables gpu_vm_support in dm and adds
> AMDGPU_GEM_DOMAIN_GTT as supported domain
>
> v2:
> Move BO placement logic into amdgpu_display_supported_domains
>
> v3:
> Use amdgpu_bo_validate_uswc in
This verifies we don't add GTT as allowed domnain for APUs when USWC
is disabled.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in
amdgpu_bo_do_create into standalone helper so it can be reused
in other functions.
v4:
Switch to return bool.
v5: Fix typos.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 61
From: Shirish S
enables gpu_vm_support in dm and adds
AMDGPU_GEM_DOMAIN_GTT as supported domain
v2:
Move BO placement logic into amdgpu_display_supported_domains
v3:
Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
v4:
amdgpu_bo_validate_uswc moved to sepperate patch.
HW requires for caching to be unset for scanout BO
mappings when the BO placement is in GTT memory.
Usually the flag to unset is passed from user mode
but for FB mode this was missing.
v2:
Keep all BO placement logic in amdgpu_display_supported_domains
Suggested-by: Alex Deucher
Signed-off-by:
First patches fixes a hard hang introduced by placing the display BO in
GTT memory because of HW issues with cached mappings. Second patch does
some minor reafactoring to resue code in thrid patch. Third patch adds
check for USWC support as condition to placing APUs scanout BO in GTT.
Last patch
That way we can ditch our gem_prime_res_obj implementation. Since ttm
absolutely needs the right reservation object all the boilerplate is
already there and we just have to wire it up correctly.
Note that gem/prime doesn't care when we do this, as long as we do it
before the bo is registered and
On Tue, Jun 25, 2019 at 10:52:17PM +0200, Sam Ravnborg wrote:
> On Tue, Jun 25, 2019 at 10:42:05PM +0200, Daniel Vetter wrote:
> > That way we can ditch our gem_prime_res_obj implementation. Since ttm
> > absolutely needs the right reservation object all the boilerplate is
> > already there and we
No it doesn't. We get clocks for --top from the sensors interface.
On 2019-07-25 9:01 a.m., Deucher, Alexander wrote:
> Tom, does umr use it?
>
> Alex
>
> *From:* Huang, Ray
> *Sent:* Thursday, July 25, 2019 4:49 AM
>
I don't recommend that, because obviously this is a hardware operation, so why
need to move it into sw init?
Is this a workaround solution, or is it specific to which asic?
and set pptable from sysfs and do baco reset operation need to call these
functions, have you test it?
the function in
Tom, does umr use it?
Alex
From: Huang, Ray
Sent: Thursday, July 25, 2019 4:49 AM
To: Wang, Kevin(Yang) ; Quan, Evan ;
amd-gfx@lists.freedesktop.org ; Zhang, Hawking
; Deucher, Alexander
Cc: Feng, Kenneth
Subject: RE: [PATCH 5/5] drm/amd/powerplay: implment
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Evan Quan
Sent: Thursday, July 25, 2019 12:23 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: fix null pointer dereference around dpm
state relates
DPM state
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Evan Quan
Sent: Wednesday, July 24, 2019 10:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: minor fixes around SW SMU power and fan
setting
Add checking for
On Wed, Jul 24, 2019 at 9:25 PM Jason Gunthorpe wrote:
>
> On Tue, Jul 23, 2019 at 07:58:48PM +0200, Andrey Konovalov wrote:
> > This patch is a part of a series that extends kernel ABI to allow to pass
> > tagged user pointers (with the top byte set to something else other than
> > 0x00) as
i will addressed it before submit patch.
thanks.
Best Regards,
Kevin
From: Quan, Evan
Sent: Thursday, July 25, 2019 5:29 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Feng, Kenneth ; Wang, Kevin(Yang)
Subject:
this is my intention,
i think we should to keep the macro name of __SMU_DUMMY_MAP.
the smu driver code will use macro SMU_MESSAGE_TYPES and SMU_FEATURE_MASKS.
the __SMU_DUMMY_MAP just a placeholder, the driver shouldn't add more one.
Best Regards,
Kevin
From:
For patch2 and patch3, __SMU_DUMMY_MAP has several different defines.
It's not sure what it is defined as and that's why you need "#undef
__SMU_DUMMY_MAP" before each use.
Please give them separate names and avoid this confusing.
Regards,
Evan
> -Original Message-
> From: amd-gfx On
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Wang, Kevin(Yang)
> Sent: Thursday, July 25, 2019 1:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Feng, Kenneth ; Wang,
> Kevin(Yang)
> Subject: [PATCH 1/5]
+ feature_mask = 1UL << feature_id;
Use "ULL" here. That can guard it to be 64bits long even on 32bits target.
With that fixed, reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Wang, Kevin(Yang)
> Sent: Thursday, July 25, 2019 1:11 PM
> To:
Any other user mode tool use the "ppfeature" sysfs interface?
Thanks,
Ray
From: Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 4:44 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org; Zhang,
Hawking ; Deucher, Alexander
Cc: Huang, Ray ; Feng, Kenneth
Subject: Re: [PATCH 5/5]
in fact, i don't want to change this sysfs name from "ppfeatures" to
"pp_features",
but it seems that don't have same name format with other pp sysfs node.
the other powerplay sysfs name have "pp_" prefix, i think we'd better to change
it name to "pp_features"
eg:
pp_cur_statepp_dpm_fclk
On 2019-07-24 5:48 p.m., Grodzovsky, Andrey wrote:
> On 7/24/19 11:40 AM, Michel Dänzer wrote:
>> On 2019-07-24 5:27 p.m., Andrey Grodzovsky wrote:
>>> Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in
>>> amdgpu_bo_do_create into standalone helper so it can be reused
>>> in other
To keep backward compatibility, we cannot change the sysfs file naming.
But it's a good idea to summarize these as common APIs.
Regards,
Evan
From: amd-gfx On Behalf Of Wang,
Kevin(Yang)
Sent: Thursday, July 25, 2019 4:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
Series are Reviewed-by: Kenneth Feng
mailto:kenneth.f...@amd.com>>
From: Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 4:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Huang, Ray ;
Deucher, Alexander
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status
add sample data from sysfs pp_features with this patch.
print format:
index. feature name (Hardware Message ID): state
sudo find /sys -name "pp_features" -exec cat {} \;
features high: 0x0623 low: 0xb3cdaffb
00. DPM_PREFETCHER ( 0) : enabeld
01. DPM_GFXCLK ( 1) : enabeld
02.
Should we have a define for the 0x8000 somewhere?
And please break the commit log into fewer characters per line.
Apart from that looks good to me,
Christian.
Am 25.07.19 um 00:23 schrieb Liu, Leo:
Please separate the patches to 2 patches. i. e. New ring test as one
patch.
Regards,
Leo
A little difficult for me to understand, but the logic is ok.
Reviewed-by: Kenneth Feng
-Original Message-
From: Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Huang, Ray ;
Deucher, Alexander ; Wang, Kevin(Yang)
Subject:
Reviewed-by: Kenneth Feng
-Original Message-
From: Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Huang, Ray ;
Deucher, Alexander ; Wang, Kevin(Yang)
Subject: [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h
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