On 2019-10-31 3:29 a.m., Christian König wrote:
> Am 31.10.19 um 00:43 schrieb Tuikov, Luben:
>> Implement an accessor of adev->tmz.enabled. Let not
>> code around access it as "if (adev->tmz.enabled)"
>> as the organization may change. Instead...
>>
>> Recruit "bool amdgpu_is_tmz(adev)" to return
On Fri, Oct 25, 2019 at 06:20:01PM +0200, Michel Dänzer wrote:
> On 2019-10-25 6:18 p.m., Will Deacon wrote:
> > On Fri, Oct 25, 2019 at 06:06:26PM +0200, Michel Dänzer wrote:
> >> On 2019-10-25 1:04 p.m., Will Deacon wrote:
> >>> In the highly unlikely event that we fail to allocate the
On 2019-10-31 11:40 a.m., Li, Roman wrote:
> On Behalf Of: Hersen Wu
> Series is:
> Reviewed-by: Hersen Wu
I only managed to skim the patches but it looks reasonable.
Series is
Acked-by: Harry Wentland
Harry
>
> -Original Message-
> From: amd-gfx On Behalf Of Nicholas
>
On Behalf Of: Hersen Wu
Series is:
Reviewed-by: Hersen Wu
-Original Message-
From: amd-gfx On Behalf Of Nicholas
Kazlauskas
Sent: Monday, October 28, 2019 10:08 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kazlauskas, Nicholas
Subject: [PATCH 01/11] drm/amdgpu: Add ucode support for
On 10/30/19 5:35 AM, Michael Ellerman wrote:
Hi Kyle,
KyleMahlkuch writes:
From: Kyle Mahlkuch
During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.
Enabled only on PPC because this
Reviewed-by: James Zhu
On 2019-10-31 10:43 a.m., Alex Deucher wrote:
> It's safe to enable dynamic VCN powergating on raven and
> raven2 for increased power savings.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++--
> 1 file changed, 6 insertions(+), 2
It's safe to enable dynamic VCN powergating on raven and
raven2 for increased power savings.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
From: abdoulaye berthe
[Why]
The aux timeout value is not default before reading link cap.
Setting it to default when lttpr is not enabled causes some monitor
not to light up.
[How]
Read the aux engine timeout value before setting it to extended.
Set the aux engine timeout to its previous value
From: Yongqiang Sun
[Why]
PSP version format is AB.CD.EF.GH, where CD and GH is the main version.
current psp version check for dmcub loading dmcu check 0x00110029, in
case of some psp version eg: 0x00110227 which main version should be
0x00110027, will result in unexpeceted dmcub loading dmcu
From: David Galiffi
[WHY]
V.Active dram clock change workaround need a small modification for DMLv2
to ensure that the dummy p-state check doesn't fail.
Signed-off-by: David Galiffi
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0416a17b0897..d931e5878b4c 100644
From: Yongqiang Sun
[Why]
DMCU isn't intiliazed properly by dmcub loading due to dmcub initialize
sequence.
[How]
Change dmcu init sequece to meet dmcub initilize.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Yongqiang Sun
[Why]
System is unable to enter S0i3 due to DISPLAY_OFF_MASK not asserted
in SMU.
[How]
Optimized bandwidth should be called paired and to resolve unplug
display underflow issue, optimize bandwidth after commit streams is
moved to next page flip, in case of S0i3, there is a
From: abdoulaye berthe
1-If at least one repeater is present in the link and we are in non
transparent mode, perform clock recovery then channel equalization
with all repeaters one by one before training DPRX.
2-Mark the end of LT with a repeater by setting training pattern 0
at the end of
From: Reza Amini
[why]
We want to guarantee integer ratio scaling for all scaling modes.
[how]
Treat centered, fullscreen, preserve aspect ratio the same: scale
the view as many times as possible, and fill in the rest with a black
border.
Signed-off-by: Reza Amini
Reviewed-by: Aric Cyr
From: abdoulaye berthe
[Description]
1-Grant extended timeout request. Done once after detection
2-Configure lttpr mode based on lttpr support before LT
3-Account for lttpr cap when determining max link settings
Signed-off-by: abdoulaye berthe
Reviewed-by: Aric Cyr
---
Summary Of Changes
*configure and init lttpr
*DSC sanity check
*Bandwidth optimization
*Some assert fixes
Anthony Koo (1):
drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC
SDP
Aric Cyr (2):
drm/amd/display: 3.2.57
drm/amd/display: 3.2.58
David Galiffi (2):
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7bf0241999c7..32eafff6b043 100644
From: "Leo (Hanghong) Ma"
[Why]
For debug purpose, we need to check the following hardware status
in DTN log debugfs:
1.dpp & hubp clock enable;
2.crtc blank enable;
3.link phy status;
[How]
Add the upper information in the amdgpu_dm_dtn_log debugfs.
For CRTC blanked status, since DCN2 and
From: Jun Lei
[why]
Need it for some OEM I2C devices in Nv10
[how]
Link up code to parse OEM table and expose DC interface
to access the pins
Signed-off-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/bios/bios_parser2.c| 63 ---
From: Eric Yang
[Why]
For unknown reason, immediate flip with host VM translation on NV12
surface will underflow on last row of PTE.
[How]
Hack chroma viewport height to make fetch one more row of PTE.
Note that this will cause hubp underflow on all video underlay
cases, but the underflow is
From: Nikola Cornij
[why]
If acquire/release DSC resource sequence is affected by a regression,
it can happen that the already-in-use DSC HW block is being wrongly
re-used for a different pipe. The reverse is also possible, i.e.
already-disabled DSC HW block could be disabled from other context.
From: abdoulaye berthe
1-Read lttpr caps in 5-bytes
2-Parse caps
3-Validate caps and set lttpr_mode
4-Use hw default timeout when lttpr is disabled.
Signed-off-by: abdoulaye berthe
Reviewed-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 90 ++-
From: abdoulaye berthe
[Why]
LTTPR was introduced after DP1.2. Reading LTTPR registers 0xF
on some DP 1.2 display is causing an unexpected behavior.
[How]
Make sure that we don't read any lttpr registers on 1.2 displays.
Signed-off-by: abdoulaye berthe
Reviewed-by: Aric Cyr
---
From: abdoulaye berthe
[Description]
When reading link, update the procedure as follows:
1-Set aux timeout to extended: 3.2ms
2-Start with reading lttpr caps
3-Determine if lttpr support should be enabled. Reset aux timeout to
400us if no repeater is found.
Signed-off-by: abdoulaye berthe
From: David Galiffi
[WHY]
It has been a useful option in debugging GFXOFF and P.State Change issues.
May be required as for platform specific workaround.
[HOW]
Create option in enum dc_debug_options, "disable_vactive_clock_change".
When it is set, dm_dram_clock_change_vactive, will translate
From: Anthony Koo
[Why]
It is confusing to sinks if we send VSC SDP only on some format. Today we
signal colorimetry format using MSA while in formats like sRGB.
But when we switch to BT2020 we set the bit to ignore MSA colorimetry and
instead use the colorimetry information in the VSC SDP.
From: Sung Lee
[WHY]
Currently made a change where disable_output is called using signal_type.
Using actual signal_type when calilng disable_output in power_down_encoders
would make DP to HDMI dongle not light up on boot. As it would have signal_type
SIGNAL_TYPE_DISPLAY_PORT.
[HOW]
Set
The hardware is vega10 and test is KFDMemoryTest.BigBufferStressTest.
More detail is on Jira SWDEV-201443.
Regards,
Eric
On 2019-10-31 10:08 a.m., StDenis, Tom wrote:
> I could try it on my carrizo/polaris setup. Is there a test procedure I
> could folllow to trigger the changed code paths?
>
Series is:
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Thursday, October 31, 2019 3:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kim, Jonathan ; Deucher, Alexander
; Quan, Evan
Subject: [PATCH 3/3] drm/amd/powerplay: support xgmi pstate setting on
I could try it on my carrizo/polaris setup. Is there a test procedure I
could folllow to trigger the changed code paths?
Tom
On 2019-10-31 6:41 a.m., Koenig, Christian wrote:
> Just tested this and amdgpu_vm_update_ptes() indeed works as expected.
>
> When you free at least a 2MB the lowest
On 31.10.2019 9:16, Kazlauskas, Nicholas wrote:
> On 2019-10-30 3:24 p.m., mikita.lip...@amd.com wrote:
>> From: Mikita Lipski
>>
>> - Adding encoder atomic check to find vcpi slots for a connector
>> - Using DRM helper functions to calculate PBN
>> - Adding connector atomic check to release
On 2019-10-30 3:24 p.m., mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> - Adding encoder atomic check to find vcpi slots for a connector
> - Using DRM helper functions to calculate PBN
> - Adding connector atomic check to release vcpi slots if connector
> loses CRTC
> - Calculate PBN
Just tested this and amdgpu_vm_update_ptes() indeed works as expected.
When you free at least a 2MB the lowest level of page tables is freed up again.
BTW: What hardware have you tested this on? On gfx8 and older it is expected
that page tables are never freed.
Regards,
Christian.
Am 30.10.19
Am 31.10.19 um 00:43 schrieb Tuikov, Luben:
Implement an accessor of adev->tmz.enabled. Let not
code around access it as "if (adev->tmz.enabled)"
as the organization may change. Instead...
Recruit "bool amdgpu_is_tmz(adev)" to return
exactly this Boolean value. That is, this function
is now an
Am 30.10.19 um 19:41 schrieb Alex Deucher:
To better clarify what is happening in this function.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
Add check for is_sw_smu routine and drop check
for amdgpu_dpm which seems non-sense.
Change-Id: I2b694a6255a76d35305fc64ca39625730e3463db
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
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