From: changzhu
It may fail to load guest driver in round 2 when using invalidate
semaphore for SRIOV. So it needs to avoid using invalidate semaphore
for SRIOV.
Change-Id: I2719671cf86a1755b05c5f2ac7420a901abbe916
Signed-off-by: changzhu
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 29
From: changzhu
It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.
Change-Id: I806f8e99ec97be84e6aed0f5c499a53b1931b490
Signed-off-by: changzhu
---
[Why]
External monitor cannot be displayed consistently, if connecting
via this Apple dongle (A1621, USB Type-C to HDMI).
Experiments prove that the dongle needs 200ms at least to be ready
for communication, after it drives HPDsignal high, and DPCD cannot
be read correctly during the period, even
Reviewed-by: Feifei Xu
-Original Message-
From: Tianci Yin
Sent: Wednesday, December 11, 2019 2:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ;
Yuan, Xiaojie ; Long, Gang ; Li,
Pauline ; Yin, Tianci (Rico)
Subject: [PATCH] drm/amdgpu/gfx10: update gfx
From: "Tianci.Yin"
add registers: mmSPI_CONFIG_CNTL
update registers: mmDB_DEBUG4 and mmUTCL1_CTRL
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
Acked-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Yintian
> Tao
> Sent: Wednesday, December 11, 2019 10:51 AM
> To: Deucher, Alexander ; Feng, Kenneth
>
> Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
> Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode
[AMD Official Use Only - Internal Distribution Only]
I assume the smu firmware has been changed accordingly.
Reviewed-by: Kenneth Feng
-Original Message-
From: Yintian Tao
Sent: Wednesday, December 11, 2019 10:51 AM
To: Deucher, Alexander ; Feng, Kenneth
Cc:
Feng, Kenneth would like to recall the message, "[PATCH] drm/amd/powerplay:
enable pp one vf mode for vega10".
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Yintian Tao
Sent: Wednesday, December 11, 2019 10:51 AM
To: Deucher, Alexander ; Feng, Kenneth
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for
[AMD Official Use Only - Internal Distribution Only]
Thanks Feifei!
From: Xu, Feifei
Sent: Wednesday, December 11, 2019 11:29
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Yuan, Xiaojie
; Long, Gang ; Li, Pauline
; Yin, Tianci
Series is Reviewed-by: Feifei Xu
-Original Message-
From: Tianci Yin
Sent: Wednesday, December 11, 2019 11:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ;
Yuan, Xiaojie ; Long, Gang ; Li,
Pauline ; Yin, Tianci (Rico)
Subject: [PATCH 1/2]
From: "Tianci.Yin"
add registers: mmSPI_CONFIG_CNTL
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ed630d37c32c..f3324fa4e194 100644
From: "Tianci.Yin"
add registers: mmSPI_CONFIG_CNTL
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f3324fa4e194..db9b8bfb1c3c 100644
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between
On 2019/12/11 上午6:08, Alex Deucher wrote:
Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend. Doesn't fix any known issue.
We already do this via the fence driver suspend function, but we
just force completion rather than bailing. This
> + /* under pp_one_vf mode, vbios or hypervisor driver
> + * has already copy table to smc so here only skip it
> + */
> + if (!hwmgr->not_vf && !hwmgr->pp_one_vf)
> + return 0;
This code seems inconsistent with the comment. Maybe using "if
(hwmgr->pp_one_vf)" is
Applied. Thanks!
Alex
On Tue, Dec 10, 2019 at 2:59 PM Arnd Bergmann wrote:
>
> Calling kzalloc() and related functions requires the
> linux/slab.h header to be included:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function
> 'dcn21_ipp_create':
>
Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend. Doesn't fix any known issue.
We already do this via the fence driver suspend function, but we
just force completion rather than bailing. This bails on runtime
suspend so we can try again
From: Pan Bian
[ Upstream commit 946ab8db6953535a3a88c957db8328beacdfed9d ]
The object fence is not set to NULL after its reference is dropped. As a
result, its reference may be dropped again if error occurs after that,
which may lead to a use after free bug. To avoid the issue, fence is
On Tue, Dec 10, 2019 at 9:56 PM Kazlauskas, Nicholas
wrote:
> On 2019-12-10 3:54 p.m., Liu, Zhan wrote:
> >>
> >> Fixes: c3d03c5a196f ("drm/amd/display: Include num_vmid and num_dsc
> >> within NV14's resource caps")
> >> Signed-off-by: Arnd Bergmann
> >
> > Thank you for catching that On my
> -Original Message-
> From: Kazlauskas, Nicholas
> Sent: Tuesday, December 10, 2019 3:56 PM
> To: Liu, Zhan ; Arnd Bergmann ;
> Wentland, Harry ; Li, Sun peng (Leo)
> ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; David Airlie ; Daniel Vetter
>
> Cc: Liu,
An initialization was added for two optional struct members. One of
these is always present in the dcn20_resource file, but the other one
depends on CONFIG_DRM_AMD_DC_DSC_SUPPORT and causes a build failure if
that is missing:
Calling kzalloc() and related functions requires the
linux/slab.h header to be included:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function
'dcn21_ipp_create':
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:679:3: error:
implicit declaration of
On Tue, Dec 10, 2019 at 9:30 PM Kazlauskas, Nicholas
wrote:
>
> On 2019-12-10 2:59 p.m., Arnd Bergmann wrote:
> > Calling kzalloc() and related functions requires the
> > linux/slab.h header to be included:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In
> > function
From: Sam Bobroff
[ Upstream commit 3d0e3ce52ce3eb4b9de3caf9c38dbb5a4d3e13c3 ]
The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address. This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8
From: Pan Bian
[ Upstream commit 946ab8db6953535a3a88c957db8328beacdfed9d ]
The object fence is not set to NULL after its reference is dropped. As a
result, its reference may be dropped again if error occurs after that,
which may lead to a use after free bug. To avoid the issue, fence is
From: Hawking Zhang
[ Upstream commit 58f46d4b65021083ef4b4d49c6e2c58e5783f626 ]
Direct uploading save/restore list via mmio register writes breaks the security
policy. Instead, the driver should pass s list to psp.
For all the ASICs that use rlc v2_1 headers, the driver actually upload s list
From: David Galiffi
[ Upstream commit dd998291dbe92106d8c4a7581c409b356928d711 ]
[WHY]
During detection:
function: get_active_converter_info populates link->dpcd_caps.dongle_caps
only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is
DOWN_STREAM_DETAILED_HDMI or
From: Allen Pais
[ Upstream commit 81de29d842ccb776c0f77aa3e2b11b07fff0c0e2 ]
alloc_workqueue is not checked for errors and as a result,
a potential NULL dereference could occur.
v2 (Felix Kuehling):
* Fix compile error (kfifo_free instead of fifo_free)
* Return proper error code
From: Christian König
[ Upstream commit 6817bf283b2b851095825ec7f0e9f10398e09125 ]
Need to make sure that we actually dropping the right fence.
Could be done with RCU as well, but to complicated for a fix.
Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
Signed-off-by: Alex Deucher
From: Jack Zhang
[ Upstream commit 51c0f58e9f6af3a387d14608033e6796a7ad90ee ]
psp v11 code missed ring stop in ring create function(VMR)
while psp v3.1 code had the code. This will cause VM destroy1
fail and psp ring create fail.
For SIOV-VF, ring_stop should not be deleted in ring_create
From: Christian König
[ Upstream commit 6817bf283b2b851095825ec7f0e9f10398e09125 ]
Need to make sure that we actually dropping the right fence.
Could be done with RCU as well, but to complicated for a fix.
Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
Signed-off-by: Alex Deucher
From: Martin Tsai
[ Upstream commit 616f5b65f1c02d3d6ae370644670d14c57de2fd8 ]
[Why]
The new implementation changed the behavior to allow process setMode
to DAL when DAL returns empty mode query for unplugged display.
This will trigger additional disable_link().
When unplug HDMI from MST dock,
From: Jing Zhou
[ Upstream commit b131932215c993ea5adf8192d1de2e8d6b23048d ]
[Why]
DP1.2 LL CTS test failure.
[How]
The failure is caused by not verify stream link is equal
to link, only check stream and link is not null.
Signed-off-by: Jing Zhou
Reviewed-by: Wenjing Liu
Acked-by:
From: Anthony Koo
[ Upstream commit 952f6c4b5d72d40f93f3deb61239290b357d434e ]
[Why]
In diags environment we are not programming the DPP DTO
correctly.
[How]
Populate the dpp refclk in dccg so it can be used to correctly
program DPP DTO.
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
From: Allen Pais
[ Upstream commit 81de29d842ccb776c0f77aa3e2b11b07fff0c0e2 ]
alloc_workqueue is not checked for errors and as a result,
a potential NULL dereference could occur.
v2 (Felix Kuehling):
* Fix compile error (kfifo_free instead of fifo_free)
* Return proper error code
From: chen gong
[ Upstream commit 068ad870bbd8f4f2c5b2fd4977a4f3330c9988f4 ]
Changes to function "smu_suspend" in amdgpu_smu.c is a workaround.
We should get real information about if baco is enabled or not, while we
always consider APU SMU feature as enabled in current code.
I know APU do
From: Josip Pavic
[ Upstream commit 15caeabc5787c15babad7ee444afe9c26df1c8b3 ]
[Why]
When the driver sends a pipe set command to the DMCU FW, it does not wait
for the command to complete. This can lead to unpredictable behavior if,
for example, the driver were to request a pipe disable to the
From: Vitaly Prosyak
[ Upstream commit 566b4252fe9da9582dde008c5e9c3eb7c136e348 ]
[Why & How]
Dongle 0x00E04C power down all internal circuits including
AUX communication preventing reading DPCD table.
Encoder will skip DP RX power down on disable output
to keep receiver powered all the time.
From: Raul E Rangel
[ Upstream commit 960b6f4f2d2e96d5f7ffe2854e0040b46cafbd36 ]
dcn20_resource.c:2636:9: error: missing braces around initializer
[-Werror=missing-braces]
struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES]
= {0};
^
Fixes: 7ed4e6352c16f
From: Hawking Zhang
[ Upstream commit 58f46d4b65021083ef4b4d49c6e2c58e5783f626 ]
Direct uploading save/restore list via mmio register writes breaks the security
policy. Instead, the driver should pass s list to psp.
For all the ASICs that use rlc v2_1 headers, the driver actually upload s list
From: Oak Zeng
[ Upstream commit 40a9592a26608e16f7545a068ea4165e1869f629 ]
On device initialization, a chunk of GTT memory is pre-allocated for
HIQ and all SDMA queues mqd. The size of this allocation was wrong.
The correct sdma engine number should be PCIe-optimized SDMA engine
number plus
From: Andrey Grodzovsky
[ Upstream commit a28fda312a9fabdf0e5f5652449d6197c9fb0a90 ]
Problem:
During GPU reset we call the GPU scheduler to suspend it's
thread, those two functions in amdgpu also suspend and resume
the sceduler for their needs but this can collide with GPU
reset in progress and
From: Le Ma
[ Upstream commit df9331e561dab0a451cbd6a679ee88a95f306fd6 ]
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
for ECC supported SKU.
Signed-off-by: Le Ma
Reviewed-by: Alex
From: David Galiffi
[ Upstream commit dd998291dbe92106d8c4a7581c409b356928d711 ]
[WHY]
During detection:
function: get_active_converter_info populates link->dpcd_caps.dongle_caps
only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is
DOWN_STREAM_DETAILED_HDMI or
From: Dmytro Laktyushkin
[ Upstream commit 48d92e8eda3d9b61978377e7539bfc5958e850cf ]
Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
From: Julian Parkin
[ Upstream commit edb922b022c0c94805c4ffad202b3edff83d76f0 ]
[Why]
When diags adds a DWB via a stream update, we calculate MMHUBBUB
paramaters, but dc->current_state has not yet been updated
when the DWB programming happens. This leads to overflow on
high bandwidth tests
From: Pan Bian
[ Upstream commit 946ab8db6953535a3a88c957db8328beacdfed9d ]
The object fence is not set to NULL after its reference is dropped. As a
result, its reference may be dropped again if error occurs after that,
which may lead to a use after free bug. To avoid the issue, fence is
From: Aric Cyr
[ Upstream commit c59802313e84bede954235b3a5dd0dd5325f49c5 ]
[Why]
Some displays rely on the SPD verticle frequency maximum value.
Must round the calculated refresh rate to the nearest integer.
[How]
Round the nominal calculated refresh rate to the nearest whole
integer.
From: Nikola Cornij
[ Upstream commit 2fef0faa1cdc5d41ce3ef83f7b8f7e7ecb02d700 ]
[why]
Some ODM-related register settings are inconsistently updated by VBIOS, causing
the state in DC to be invalid, which would then end up crashing in certain
use-cases (such as disable/enable device).
[how]
From: joseph gravenor
[ Upstream commit cd83fa1ea9b9431cf1d57ac4179a11bc4393a5b6 ]
[why]
Should always MP0_BASE for any register definition from MP per-IP header files.
I belive the reason the linux version of MP1_BASE works is The 0th element of
the 0th table
of that is identical to the
From: Raul E Rangel
[ Upstream commit d942070575910fdb687b9c8fd5467704b2f77c24 ]
drivers/gpu/drm/amd/powerplay/renoir_ppt.c:186:2: error: missing braces
around initializer [-Werror=missing-braces]
SmuMetrics_t metrics = {0};
^
Fixes: 8b8031703bd7 ("drm/amd/powerplay: implement sysfs for
From: Kevin Wang
[ Upstream commit 2c2fdb8bca290c439e383cfb6857b0c65e528964 ]
the trace event print string format error.
(use integer type to handle string)
before:
amdgpu_test_kev-1556 [002] 138.508781: amdgpu_cs_ioctl:
sched_job=8, timeline=gfx_0.0.0, context=177, seqno=1,
From: Zhan liu
[ Upstream commit 967a3b85bac91c55eff740e61bf270c2732f48b2 ]
[Why]
This patch is for fixing Navi14 HDMI display pink screen issue.
[How]
Call stream->link->link_enc->funcs->setup twice. This is setting
the DIG_MODE to the correct value after having been overridden by
the call to
From: Anthony Koo
[ Upstream commit 2ad0cdf9e2e9e079af34af681863fa638f2ee212 ]
[Why]
A lot of the time, the backlight characteristic curve maps min backlight
to a non-zero value.
But there are cases where we want the curve to intersect at 0.
In this scenario even if OS never asks to set 0%
From: Sam Bobroff
[ Upstream commit 3d0e3ce52ce3eb4b9de3caf9c38dbb5a4d3e13c3 ]
The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address. This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8
On 2019-12-10 3:54 p.m., Liu, Zhan wrote:
-Original Message-
From: Arnd Bergmann
Sent: 2019/December/10, Tuesday 3:31 PM
To: Wentland, Harry ; Li, Sun peng (Leo)
; Deucher, Alexander
; Koenig, Christian
; Zhou, David(ChunMing)
; David Airlie ; Daniel Vetter
; Liu, Zhan
Cc: Arnd
> -Original Message-
> From: Arnd Bergmann
> Sent: 2019/December/10, Tuesday 3:31 PM
> To: Wentland, Harry ; Li, Sun peng (Leo)
> ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; David Airlie ; Daniel Vetter
> ; Liu, Zhan
> Cc: Arnd Bergmann ; Laktyushkin,
On 2019-12-10 2:59 p.m., Arnd Bergmann wrote:
Calling kzalloc() and related functions requires the
linux/slab.h header to be included:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function
'dcn21_ipp_create':
I switched the workqueue we were using for xgmi_reset_work from
system_highpri_wq to system_unbound_wq - the difference is that workers
servicing the queue in system_unbound_wq are not bounded to specific CPU
and so the reset jobs for each XGMI node are getting scheduled to
different CPU while
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between
On 12/10/19 6:32 PM, Christian König wrote:
Maybe make this "num_sched_list > 1 ? sched_list : NULL" to avoid
accidentally dereferencing a stale pointer to the stack.
Do you mean "num_sched_list >= 1 ? sched_list : NULL"
No, the entity->sched_list field should be NULL when
Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
Am 10.12.19 um 17:20 schrieb Changfeng.Zhu:
From: changzhu
It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.
Change-Id:
() On Tue, Dec 10, 2019 at 4:36 AM Yintian Tao wrote:
>
> Originally, due to the restriction from PSP and SMU, VF has
> to send message to hypervisor driver to handle powerplay
> change which is complicated and redundant. Currently, SMU
> and PSP can support VF to directly handle powerplay
>
Am 10.12.19 um 16:08 schrieb Nirmoy:
I think amdgpu_ctx_init() should check for num_scheds and not call
drm_sched_entity_init()
if its zero.
Ah, that's where that came from. No that is intentionally this way, but
see below.
On 12/10/19 3:47 PM, Nirmoy wrote:
On 12/10/19 2:00 PM,
Ping...
-Original Message-
From: Yintian Tao
Sent: 2019年12月10日 17:36
To: Deucher, Alexander ; Feng, Kenneth
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
Originally, due to the restriction from PSP and SMU, VF
On Tue, Dec 10, 2019 at 11:22 AM Changfeng.Zhu wrote:
>
> From: changzhu
>
> It may fail to load guest driver in round 2 when using invalidate
> semaphore for SRIOV. So it needs to avoid using invalidate semaphore
> for SRIOV.
>
> Change-Id: I2719671cf86a1755b05c5f2ac7420a901abbe916
>
On Tue, Dec 10, 2019 at 11:21 AM Changfeng.Zhu wrote:
>
> From: changzhu
>
> It may fail to load guest driver in round 2 or cause Xstart problem
> when using invalidate semaphore for SRIOV or picasso. So it needs avoid
> using invalidate semaphore for SRIOV and picasso.
>
> Change-Id:
From: changzhu
It may fail to load guest driver in round 2 when using invalidate
semaphore for SRIOV. So it needs to avoid using invalidate semaphore
for SRIOV.
Change-Id: I2719671cf86a1755b05c5f2ac7420a901abbe916
Signed-off-by: changzhu
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 32
From: changzhu
It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.
Change-Id: I806f8e99ec97be84e6aed0f5c499a53b1931b490
Signed-off-by: changzhu
---
Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 3 +
I think amdgpu_ctx_init() should check for num_scheds and not call
drm_sched_entity_init()
if its zero.
On 12/10/19 3:47 PM, Nirmoy wrote:
On 12/10/19 2:00 PM, Christian König wrote:
Am 10.12.19 um 13:53 schrieb Nirmoy Das:
entity should not keep copy and maintain sched list for
itself.
On 12/10/19 2:00 PM, Christian König wrote:
Am 10.12.19 um 13:53 schrieb Nirmoy Das:
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff
Am 10.12.19 um 14:00 schrieb Christian König:
Am 10.12.19 um 13:53 schrieb Nirmoy Das:
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
Am 10.12.19 um 13:53 schrieb Nirmoy Das:
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/scheduler/sched_entity.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git
Am 10.12.19 um 13:52 schrieb Nirmoy Das:
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113
Yeah, but you are to fast for me. I was still looking into comments for
patch #4 :)
Christian.
Am 10.12.19 um 13:55 schrieb Nirmoy:
Thanks Christian. That make sense, resent modified patches.
On 12/10/19 12:28 PM, Christian König wrote:
Am 09.12.19 um 22:53 schrieb Nirmoy Das:
This sched
Thanks Christian. That make sense, resent modified patches.
On 12/10/19 12:28 PM, Christian König wrote:
Am 09.12.19 um 22:53 schrieb Nirmoy Das:
This sched list can be passed on to entity creation routine
instead of manually creating such sched list on every context creation.
Please drop
Am 09.12.19 um 22:53 schrieb Nirmoy Das:
This sched list can be passed on to entity creation routine
instead of manually creating such sched list on every context creation.
Please drop the "_list" from the names here. A list usually means a
linked list and those are actually arrays.
Am 10.12.19 um 12:03 schrieb Zhu, Changfeng:
[AMD Official Use Only - Internal Distribution Only]
OK, Chris.
What's about SRIOV?
Should we skip using semaphore registers for SRIOV now?
I add REG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM, i, 0x0);
in mmhub_v1_0_program_invalidation.
[AMD Official Use Only - Internal Distribution Only]
OK, Chris.
What's about SRIOV?
Should we skip using semaphore registers for SRIOV now?
I add REG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM, i, 0x0);
in mmhub_v1_0_program_invalidation.
However, the problem still happens.
BR,
Am 10.12.19 um 03:55 schrieb Changfeng.Zhu:
From: changzhu
It may cause timeout waiting for sem acquire in VM flush when using
invalidate semaphore for picasso. So it needs to avoid using invalidate
semaphore for piasso.
It would probably be better to add a small helper function to decide if
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between
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