Reviewed-by : Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Yintian Tao
Sent: Tuesday, December 17, 2019 11:47 AM
To: Deucher, Alexander ; Feng, Kenneth
; Quan, Evan
Cc:
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, December 17, 2019 4:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu/smu: fix spelling
>
> s/dispaly/display/g
>
> Signed-off-by:
Under sriov pp one vf mode, there is no need to set
soc clk under pp one vf because smu firmware will depend
on the mclk to set the appropriate soc clk for it.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 ++-
1 file changed, 2 insertions(+), 1
On Mon, Dec 16, 2019 at 4:29 PM Nirmoy Das wrote:
>
> Fixes: 8c066a8c7a9ac9a66 (amd/amdgpu: add sched array to IPs with multiple
> run-queues)
>
> Signed-off-by: Nirmoy Das
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
Fixes: 8c066a8c7a9ac9a66 (amd/amdgpu: add sched array to IPs with multiple
run-queues)
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
[AMD Official Use Only - Internal Distribution Only]
Regards,
Oak
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Monday, December 16, 2019 3:25 PM
To: Alex Deucher ; Koenig, Christian
Cc: Deucher, Alexander ; amd-gfx list
Subject: Re: [PATCH 2/3]
Am 16.12.19 um 21:22 schrieb Alex Deucher:
On Mon, Dec 16, 2019 at 3:19 PM Christian König
wrote:
Am 16.12.19 um 18:18 schrieb Alex Deucher:
Increment the usage count in emit fence, and decrement in
process fence to make sure the GPU is always considered in
use while there are fences
Am 16.12.19 um 21:13 schrieb Felix Kuehling:
On 2019-12-16 3:06 p.m., Zhao, Yong wrote:
[AMD Official Use Only - Internal Distribution Only]
The problem happens when we want to reuse the same function for ASICs
which have fewer SDMA engines. Some pointers on which
SOC15_REG_OFFSET depends
On Mon, Dec 16, 2019 at 3:19 PM Christian König
wrote:
>
> Am 16.12.19 um 18:18 schrieb Alex Deucher:
> > Increment the usage count in emit fence, and decrement in
> > process fence to make sure the GPU is always considered in
> > use while there are fences outstanding. We always wait for
> >
Am 16.12.19 um 18:18 schrieb Alex Deucher:
Increment the usage count in emit fence, and decrement in
process fence to make sure the GPU is always considered in
use while there are fences outstanding. We always wait for
the engines to drain in runtime suspend, but in practice
that only covers
On Mon, Dec 16, 2019 at 3:15 PM Leo Liu wrote:
>
> Esp. VCN1.0 headers should not be here
>
> v2: add back the to keep consistent.
>
> Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git
Esp. VCN1.0 headers should not be here
v2: add back the to keep consistent.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index
On 2019-12-16 3:06 p.m., Zhao, Yong wrote:
[AMD Official Use Only - Internal Distribution Only]
The problem happens when we want to reuse the same function for ASICs
which have fewer SDMA engines. Some pointers on which SOC15_REG_OFFSET
depends for some higher index SDMA engines are 0,
Hi Alex,
I searched and found why it get built okay:
amdgpu.h includes amdgpu_mode.h, and that include linux/i2c.h.
And linux/i2c.h includes linux/acpi.h and that includes linux/modules.h.
Tested it by commenting out linux/modules.h from linux/acpi.h, then the
build for amdgpu.ko would fail
s/dispaly/display/g
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++--
drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 ++--
[AMD Official Use Only - Internal Distribution Only]
The problem happens when we want to reuse the same function for ASICs which
have fewer SDMA engines. Some pointers on which SOC15_REG_OFFSET depends for
some higher index SDMA engines are 0, causing NULL pointer.
I will fix the default case
On 2019-12-13 8:38, Yong Zhao wrote:
This prevents the NULL pointer access when there are fewer than 8 sdma
engines.
I don't see where you got a NULL pointer in the old code. Also this
change is in an Arcturus-specific source file. AFAIK Arcturus always has
8 SDMA engines.
The new code is
[AMD Official Use Only - Internal Distribution Only]
The patch looks good.
Reviewed-by: Hersen Wu
-Original Message-
From: Liu, Zhan
Sent: Friday, December 13, 2019 11:50 AM
To: amd-gfx@lists.freedesktop.org; Wu, Hersen ; Deucher,
Alexander ; Wang, Kevin(Yang) ;
Quan, Evan ; Yin,
Ping...
> -Original Message-
> From: Liu, Zhan
> Sent: 2019/December/13, Friday 11:50 AM
> To: amd-gfx@lists.freedesktop.org; Wu, Hersen ;
> Deucher, Alexander ; Wang, Kevin(Yang)
> ; Quan, Evan ; Yin, Tianci
> (Rico)
> Cc: Liu, Zhan
> Subject: [PATCH] drm/amd/powerplay: Add SMU
Applied the series. Thanks!
Alex
On Sat, Dec 14, 2019 at 9:44 AM zhengbin wrote:
>
> zhengbin (3):
> drm/amdgpu: Remove unneeded semicolon in amdgpu_pmu.c
> drm/amdgpu: Remove unneeded semicolon in gfx_v10_0.c
> drm/amdgpu: Remove unneeded semicolon in amdgpu_ras.c
>
>
On Mon, Dec 16, 2019 at 9:32 AM Harry Wentland wrote:
>
> On 2019-12-14 4:12 a.m., zhengbin wrote:
> > Fixes coccicheck warning:
> >
> > drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c:412:90-91:
> > Unneeded semicolon
> >
> > Reported-by: Hulk Robot
> > Signed-off-by: zhengbin
>
>
From: Andrey Grodzovsky
CRTC in DPMS state off calls for low power state entry.
Support both atomic mode setting and pre-atomic mode setting.
v2: move comment
Signed-off-by: Andrey Grodzovsky
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 45
Increment the usage count in emit fence, and decrement in
process fence to make sure the GPU is always considered in
use while there are fences outstanding. We always wait for
the engines to drain in runtime suspend, but in practice
that only covers short lived jobs for gfx. This should
cover us
Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend. Doesn't fix any known issue.
We already do this via the fence driver suspend function, but we
just force completion rather than bailing. This bails on runtime
suspend so we can try again
On 2019-12-16 11:36 a.m., Alex Deucher wrote:
On Mon, Dec 16, 2019 at 11:06 AM Leo Liu wrote:
Esp. VCN1.0 headers should not be here
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ---
1 file changed, 7 deletions(-)
diff --git
Ping on unreviewed V2s...
Andrey
On 12/13/19 11:54 AM, Andrey Grodzovsky wrote:
In preparation for doing XGMI reset synchronization using task barrier.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 -
On Mon, Dec 16, 2019 at 11:06 AM Leo Liu wrote:
>
> Esp. VCN1.0 headers should not be here
>
> Signed-off-by: Leo Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>
Esp. VCN1.0 headers should not be here
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e522025430c7..371f55de42dc 100644
---
On 2019-12-14 4:12 a.m., zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c:412:90-91: Unneeded
> semicolon
>
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
Reviewed-by: Harry Wentland
Harry
> ---
>
Hi Christian,
On 12/16/19 3:03 PM, Nirmoy Das wrote:
Reviewed-by: Christian König
I am keeping Reviewed-by again :) I had to minor rebase related change.
Regards,
Nirmoy
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
v2 Changes: rebased
0003-amd-amdgpu-add-sched-array-to-IPs-with-multiple-run-.patch because of
a5c191e9cd09a8fa697865882619692b4dba8417(drm/amdgpu: fix JPEG instance checking
when ctx init)
Nirmoy Das (4):
drm/scheduler: rework entity creation
drm/amdgpu: replace vm_pte's run-queue list
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 114 +
Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chen, Guchun
Sent: Friday, December 13, 2019 16:54
To: Zhang, Hawking ; Ma, Le ; Zhou1, Tao
; Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun
On Fri, Dec 13, 2019 at 11:24:00AM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> When smu version is larger than 0x41e2b, it will load
> raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it
> needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads
>
Reviewd-by Yintian Tao
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: 2019年12月16日 17:17
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/sriov: Tonga sriov also need load firmware with smu
Fix Tonga sriov load driver fail issue.
Fix Tonga sriov load driver fail issue.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 3 ++-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
Hi Alex,
On Mon, Nov 25, 2019 at 1:17 PM Daniel Drake wrote:
> Unfortunately not. The original issue still exists (dead gfx after
> resume from s2idle) and also when I trigger execution of the suspend
> or runtime suspend routines the power usage increases around 1.5W as
> before.
>
> Have you
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