[AMD Public Use]
Series is:
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Hawking Zhang
Sent: Monday, March 2, 2020 6:34 PM
To: amd-gfx@lists.freedesktop.org; Clements, John ; Li,
Dennis ; Chen, Guchun ; Zhou1, Tao
; Deucher, Alexander
Cc: Zhang, Hawking
[AMD Official Use Only - Internal Distribution Only]
Could anyone help to review the patch?
Thanks
Jacob
From: He, Jacob
Sent: Monday, March 2, 2020 1:35:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: He, Jacob
Subject: [PATCH] drm/amdgpu: Update SPM_VMID with
[AMD Official Use Only - Internal Distribution Only]
The series is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Hawking Zhang
> Sent: 2020年3月2日 18:34
> To: amd-gfx@lists.freedesktop.org; Clements, John
> ; Li, Dennis ; Chen,
> Guchun ; Zhou1, Tao ;
> Deucher, Alexander
> Cc:
On 2020-03-02 4:51 p.m., Andrey Grodzovsky wrote:
>
> On 3/2/20 4:19 PM, Luben Tuikov wrote:
>> On 2020-03-02 2:24 p.m., Andrey Grodzovsky wrote:
>>> Add the programming sequence.
>>>
>>> Signed-off-by: Andrey Grodzovsky
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 76
>>>
Clang warns:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.c:147:31: warning:
address of 'pipe_ctx->plane_res' will always evaluate to 'true'
[-Wpointer-bool-conversion]
if (!pipe_ctx || !_ctx->plane_res || !_ctx->stream_res)
~ ~~^
On Thu, Jan 23, 2020 at 2:59 PM Thomas Zimmermann wrote:
>
> The new callback get_scanout_position() reads the current location
> of the scanout process. The operation is currently located in struct
> drm_driver, but really belongs to the CRTC. Drivers will be converted
> in separate patches.
>
>
On 3/2/20 4:19 PM, Luben Tuikov wrote:
On 2020-03-02 2:24 p.m., Andrey Grodzovsky wrote:
Add the programming sequence.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 76 ++
1 file changed, 76 insertions(+)
diff --git
Thanks Christian. I'll take a look and play with it.
Regards,
Luben
On 2020-03-02 7:17 a.m., Christian König wrote:
> Because of a shift in priorities I won't work on TMZ this week.
>
> So attached are a few smaller patches I already prepared, but the bounce copy
> for system eviction is still
On 2020-03-02 2:24 p.m., Andrey Grodzovsky wrote:
> Starts USBC PD FW download and reads back the latest FW version.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 94
> +
> 1 file changed, 94 insertions(+)
>
> diff --git
The dpp2_get_optimal_number_of_taps function is never used. Removing just for
code cleaning up.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 78 ---
1 file changed, 78 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
On Mon, Mar 2, 2020 at 7:18 AM Christian König
wrote:
>
> Swapping out encrypted BOs doesn't work because they can't change
> their physical location without going through a bounce copy.
>
> As a workaround disable evicting encrypted BOs to the system
> domain for now.
>
> Signed-off-by:
On Mon, Mar 2, 2020 at 2:24 PM Andrey Grodzovsky
wrote:
>
> Starts USBC PD FW download and reads back the latest FW version.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 94
> +
> 1 file changed, 94 insertions(+)
>
>
On Mon, Mar 2, 2020 at 2:24 PM Andrey Grodzovsky
wrote:
>
> Add the programming sequence.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 76
> ++
> 1 file changed, 76 insertions(+)
>
> diff --git
On 2020-03-02 2:24 p.m., Andrey Grodzovsky wrote:
> Add the programming sequence.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 76
> ++
> 1 file changed, 76 insertions(+)
>
> diff --git
On Mon, Mar 2, 2020 at 2:24 PM Andrey Grodzovsky
wrote:
>
> Used to load PD FW to PSP.
Might want to define PD = Power Delivery. With that fixed:
Reviewed-by: Alex Deucher
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 10 ++
> 1 file changed,
On 2020-03-02 2:24 p.m., Andrey Grodzovsky wrote:
> Add the programming sequence.
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 76
> ++
> 1 file changed, 76 insertions(+)
>
> diff --git
On Mon, Mar 2, 2020 at 3:25 PM Luben Tuikov wrote:
>
> On 2020-02-28 2:38 a.m., Christian König wrote:
> > Am 28.02.20 um 04:29 schrieb Luben Tuikov:
> >> On 2020-02-26 3:37 p.m., Nirmoy Das wrote:
> >>> init_priority will set second compute queue(gfx8 and gfx9) of a pipe to
> >>> high priority
On 2020-02-28 2:47 a.m., Christian König wrote:
> Am 28.02.20 um 06:08 schrieb Luben Tuikov:
>> On 2020-02-27 4:40 p.m., Nirmoy Das wrote:
>>> implement drm_sched_entity_modify_sched() which can modify existing
>>> sched_list with a different one. This is going to be helpful when
>>> userspace
On 2020-02-28 2:38 a.m., Christian König wrote:
> Am 28.02.20 um 04:29 schrieb Luben Tuikov:
>> On 2020-02-26 3:37 p.m., Nirmoy Das wrote:
>>> init_priority will set second compute queue(gfx8 and gfx9) of a pipe to
>>> high priority
>>> and 1st queue to normal priority.
>>>
>>> Signed-off-by:
Used to load PD FW to PSP.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 37fa184..297435c 100644
---
Starts USBC PD FW download and reads back the latest FW version.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 94 +
1 file changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
Add the programming sequence.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index
This patchset adds the kernel driver part of supporting USBC power delivery
firmware downloading to USBC chip on the ASIC. The FW is placed in DMA buffer
visible to PSP which then proceeds and copies the FW over I2C to the USBC chip.
Andrey Grodzovsky (3):
drm/amdgpu: Add USBC PD FW load
This is a note to let you know that I've just added the patch titled
drm/radeon: Inline drm_get_pci_dev
to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
This is a note to let you know that I've just added the patch titled
drm/radeon: Inline drm_get_pci_dev
to the 5.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
[AMD Official Use Only - Internal Distribution Only]
Ported from Vega10. SDMA stress tests sometimes see IRQ lost.
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 36 ++
1 file changed, 36 insertions(+)
diff --git
Am 02.03.20 um 15:20 schrieb Nirmoy:
Hi Christian
On 3/2/20 2:10 PM, Christian König wrote:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 24caff085d00..201c6ac7bf9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++
From: Josip Pavic
[Why]
Swath sizes are being calculated incorrectly. The horizontal swath size
should be the product of block height, viewport width, and bytes per
element, but the calculation uses viewport height instead of width. The
vertical swath size is similarly incorrectly calculated.
From: Joseph Gravenor
[why]
When we have single channel memory, we can not light up 2 4k displays
with a 1080p edp, because we don't have enough bw by a small margin.
this small margin comes from dcc meta being too large. We however don't
have this dcc meta when we create fake planes so, before
From: Wyatt Wood
[Why]
We want to be able to enable PSR on DMCUB, and fallback to
DMCU when necessary.
[How]
Move psr_on_dmub flag from dc_debug_options to dc_config.
Signed-off-by: Wyatt Wood
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Improvements on link training
* fixes on odm, dcc, and logger
* Improvements on DMCUB
Aric Cyr (1):
drm/amd/display: 3.2.75
Bhawanpreet Lakha (1):
drm/amd/display: Clear link settings on MST disable
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Martin Leung
[Why]
Previously implemented early_cr_pattern we mistook dp_hw_link_settings
for a redundant call of dpcd_set_link_settings
[How]
revert the changes to dpcd_set_link_settings calls for this workaround.
Do not need to revert the entire change since it only affects patched
case
From: Sung Lee
[WHY]
We see an issue that caused clk_optimized_required to be set true in
certain cases, causing passive flips to fail. This is because of a typo
where wm_optimized_required was set twice.
[HOW]
Set clk_optimized_required to false after updating clocks.
Signed-off-by: Sung Lee
From: George Shen
[Why]
When transitioning from SST to MST, the HDCP repeater in some MST
displays will enter a bad state. The HDCP repeater is recovered after
failing and performing authentication again.
[How]
Add monitor patch to trigger HDCP authentication failure after
encryption is enabled
From: Bhawanpreet Lakha
[Why]
If we have a single MST display and we disconnect it, we dont disable that
link. This causes the old link settings to still exist
Now on a replug for MST we think its a link loss and will try to reallocate
mst payload which will fail, throwing warning below.
[
From: Sung Lee
[WHY & HOW]
In order to correctly intepret clock table, num_states is also needed.
This field did not get moved with clock_table but should next to it for
easier access/viewing.
Signed-off-by: Sung Lee
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
---
From: Wenjing Liu
[how]
Allow vsc info packet if vsc is supported. Update vsc based on test
pattern request. Remove dpg_is_blanked polling, apply hardware global
lock instead to ensure double buffered dpg is updated with vsc in one
frame
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
From: Wenjing Liu
[why]
Some asics don't support FEC but FEC overhead is added into link
bandwidth calculation by mistake. This causes certain timing cannot be
validated.
[how]
Only include FEC overhead if both asic and display support FEC.
Signed-off-by: Wenjing Liu
Reviewed-by: Ashley
From: Nikola Cornij
Disabling FEC for specific monitors is sometimes required for debugging
while in the monitor bringup phase
Signed-off-by: Nikola Cornij
Reviewed-by: Alvin Lee
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +++
From: Isabel Zhang
[Why]
Reset connection is called before remove display in mod_hdcp. When
remove display is called, the display structure has been zeroed from
reset connection. Since no displays can be found, remove display does
not properly reset the hardware. This causes validation errors
From: Wenjing Liu
[why]
When combining two or more pipes in DSC mode, there will always be more
than 1 slice per line. In this case, as per DSC rules, the sink device
is expecting that the ICH is reset at the end of each slice line (i.e.
ICH_RESET_AT_END_OF_LINE must be configured based on the
From: Wenjing Liu
[why]
When test pattern is enabled with ODM combine, test pattern is generated
by piecing multiple DPGs image together. The current code will program
all DPGs with horizontal offset of 0. This will cause all DPGs to output
the beginning of the pattern. Instead each DPG should
From: Yongqiang Sun
[Why]
vstartup calculation is incorrect due to use 2 number of cursors and
result in an underflow when playing video in full screen mode and
combines graphic plane and video plane.
[How]
Apply new policy for dml calculation.
1 cursor for graphic plane, 0 cursor for video
From: Sung Lee
[WHY]
SMU FW previously had an issue with lowering display clock to below 100
MHz, and a workaround was put in to limit it. Newest SMU FW does not
have this issue, and no longer needs the 100MHz cap.
[HOW]
Remove the 100MHz cap based on the SMU FW version.
Signed-off-by: Sung
From: Roman Li
[Why]
Typo in amdgpu_dm error message:
"Failed to found connector for link!"
[How]
1. Replace with:
"Failed to find connector for link!"
2. Fix indentation checkpatch warnings.
Signed-off-by: Roman Li
Reviewed-by: Zhan Liu
Acked-by: Rodrigo Siqueira
---
From: Wyatt Wood
[Why]
Moving ABM from DMCU to DMCUB.
[How]
Add ABM command structs.
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 52 +++
.../drm/amd/display/dmub/inc/dmub_cmd_dal.h | 9
From: Michael Strauss
[WHY]
Freesync borderless is not meant to be enabled on any APUs
[HOW]
Add is_apu cap to dcn21_resource_construct for correct recognition
Signed-off-by: Michael Strauss
Reviewed-by: Yongqiang Sun
Acked-by: Rodrigo Siqueira
---
From: Eric Bernstein
[Why]
Logger mask was updated to uint64_t, however default mask definition was
not updated for unsigned long long
[How]
Update DC_DEFAULT_LOG_MASK to support uint64_t type
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
---
From: abdoulaye berthe
[Why]
Some lttpr devices do not work properly when lttpr mode is configured
after link settings.
[How]
Move lttpr configuration before lane settings.
Signed-off-by: abdoulaye berthe
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
---
Hello,
I'm having difficulty getting OpenCL to see an ASRock 5700 XT GPU. I have
gotten this to work with a Sapphire card, which I have been using as a point of
comparison on a different system.
With amdgpu-19.50 and kernel 5.5.6 or 5.6rc3, clinfo (either via amdgpu or
standard) reports zero
[AMD Public Use]
Series is:
Reviewed-by: Alex Deucher
From: Hawking Zhang
Sent: Monday, March 2, 2020 5:33 AM
To: amd-gfx@lists.freedesktop.org ; Clements,
John ; Li, Dennis ; Chen, Guchun
; Zhou1, Tao ; Deucher, Alexander
Cc: Zhang, Hawking
Subject: [PATCH
On Fri, Feb 28, 2020 at 3:59 PM Wu, Hersen wrote:
>
> Follow Evan's review, add smu->mutex.
>
>
> This interface is for dGPU Navi1x. Linux dc-pplib interface depends
> on window driver dc implementation.
>
> For Navi1x, clock settings of dcn watermarks are fixed. the settings
> should be
Hi Christian
On 3/2/20 2:10 PM, Christian König wrote:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 24caff085d00..201c6ac7bf9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@
On 2020-03-02 1:17 a.m., Mario Kleiner wrote:
Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
events at vsartup for DCN")' introduces a new way of pageflip
completion handling for DCN, and some trouble.
The current implementation introduces a race condition, which
can cause
Applied!
Thanks
On 02/28, Melissa Wen wrote:
> This patchset solves some coding style issues on dc_link for readability
> and cleaning up warnings. Change suggested by checkpatch.pl.
>
> Changes in v2:
> - Apply patches to the right amdgpu repository.
> - Remove unnecessary {} added in the
Am 02.03.20 um 13:58 schrieb Nirmoy Das:
We were changing compute ring priority while rings were being used
before every job submission which is not recommended. This patch
sets compute queue priority at mqd initialization for gfx8, gfx9 and
gfx10.
Policy: make queue 0 of each pipe as high
Hi Christian,
The 3 patches are:
Tested-by: Pierre-Eric Pelloux-Prayer
Regards,
Pierre-Eric
On 02/03/2020 13:17, Christian König wrote:
> Because of a shift in priorities I won't work on TMZ this week.
>
> So attached are a few smaller patches I already prepared, but the bounce copy
> for
amdgpu statically set priority for compute queues
at initialization so remove all the functions
responsible changing compute queue priority dynamically
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 70
implement drm_sched_entity_modify_sched() which can modify existing
sched_list with a different one. This is going to be helpful when
userspace changes priority of a ctx/entity then driver can switch to
corresponding hw shced list for that priority
Signed-off-by: Nirmoy Das
Reviewed-by:
Switch to appropriate sched list for an entity on priority override.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32 +
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
We were changing compute ring priority while rings were being used
before every job submission which is not recommended. This patch
sets compute queue priority at mqd initialization for gfx8, gfx9 and
gfx10.
Policy: make queue 0 of each pipe as high priority compute queue
High/normal priority
+
+ switch (hw_ip) {
+ case AMDGPU_HW_IP_COMPUTE:
+ compute_priority =
+ amdgpu_ctx_sched_prio_to_compute_prio(priority);
+ scheds = adev->gfx.compute_prio_sched[compute_priority];
+ num_scheds = adev->gfx.num_compute_sched[compute_priority];
+ break;
+
Am 02.03.20 um 13:27 schrieb Nirmoy:
On 3/2/20 1:10 PM, Christian König wrote:
Am 02.03.20 um 10:52 schrieb Nirmoy Das:
Switch to appropriate sched list for an entity on priority override.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30
On 3/2/20 1:06 PM, Christian König wrote:
#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
+enum gfx_pipe_priority {
+ AMDGPU_GFX_PIPE_PRIO_LOW = 0,
That is not used as far as I can see.
Okay I will remove it.
+
On 3/2/20 1:10 PM, Christian König wrote:
Am 02.03.20 um 10:52 schrieb Nirmoy Das:
Switch to appropriate sched list for an entity on priority override.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 +
1 file changed, 26 insertions(+), 4
Swapping out encrypted BOs doesn't work because they can't change
their physical location without going through a bounce copy.
As a workaround disable evicting encrypted BOs to the system
domain for now.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
1 file
Because of a shift in priorities I won't work on TMZ this week.
So attached are a few smaller patches I already prepared, but the bounce copy
for system eviction is still missing.
Patches are totally untested, but I anybody find them useful feel free to test
and review them.
Regards,
This way we should be at least able to move buffers from VRAM to GTT.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 28 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +-
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git
This is necessary for TMZ handling during buffer moves and scanout.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index
Am 02.03.20 um 10:52 schrieb Nirmoy Das:
Switch to appropriate sched list for an entity on priority override.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 +
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git
Am 02.03.20 um 10:52 schrieb Nirmoy Das:
amdgpu statically set priority for compute queues
at initialization so remove all the functions
responsible changing compute queue priority dynamically
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
Am 02.03.20 um 10:52 schrieb Nirmoy Das:
implement drm_sched_entity_modify_sched() which can modify existing
sched_list with a different one. This is going to be helpful when
userspace changes priority of a ctx/entity then driver can switch to
corresponding hw shced list for that priority
Am 02.03.20 um 10:52 schrieb Nirmoy Das:
We were changing compute ring priority while rings were being used
before every job submission which is not recommended. This patch
sets compute queue priority at mqd initialization for gfx8, gfx9 and
gfx10.
Policy: make queue 0 of each pipe as high
GFX ras error counters are dirty ones after cold reboot
Read operation is needed to reset them to 0
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c |
HDP ras error counters are dirty ones after cold reboot
Read operation is needed to reset them to 0
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/soc15.c| 14 ++
3 files
The RAS hw error counters in most IP blocks could be dirty ones
after cold reboot. Read operation is required to reset those regs
to 0 so that user won't get random value when query those counters
via sysfs nodes.
In addition, the reset_ras_error_counter is also important interface
for amdgpu ras
MMHUB ras error counters are dirty ones after cold reboot
Read operation is needed to reset them to 0
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 12
SDMA ras error counters are dirty ones after cold reboot
Read operation is needed to reset them to 0
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 ++--
2 files changed, 15 insertions(+), 6
Switch to appropriate sched list for an entity on priority override.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 +
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
We were changing compute ring priority while rings were being used
before every job submission which is not recommended. This patch
sets compute queue priority at mqd initialization for gfx8, gfx9 and
gfx10.
Policy: make queue 0 of each pipe as high priority compute queue
High/normal priority
implement drm_sched_entity_modify_sched() which can modify existing
sched_list with a different one. This is going to be helpful when
userspace changes priority of a ctx/entity then driver can switch to
corresponding hw shced list for that priority
Signed-off-by: Nirmoy Das
---
amdgpu statically set priority for compute queues
at initialization so remove all the functions
responsible changing compute queue priority dynamically
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 70
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 7
Am 02.03.20 um 10:39 schrieb Liu, Monk:
- if (!(ib->flags & AMDGPU_IB_FLAG_CE))
+ if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
Kernel copies also don't use a VMID, so I think that this won't work correctly.
Do you have the job available as well? That would probably
Thanks Feifei and Monk!
From: Liu, Monk
Sent: Monday, March 2, 2020 17:35
To: Xu, Feifei ; Yin, Tianci (Rico) ;
amd-gfx@lists.freedesktop.org
Cc: Long, Gang ; Li, Pauline ; Yin,
Tianci (Rico) ; Gao, Likun ; Zhang,
Hawking ; Yuan, Xiaojie
Subject: RE: [PATCH]
> - if (!(ib->flags & AMDGPU_IB_FLAG_CE))
> + if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
Kernel copies also don't use a VMID, so I think that this won't work correctly.
Do you have the job available as well? That would probably be better to test
for since only IB
Am 02.03.20 um 10:22 schrieb Monk Liu:
1)for gfx IB test we shouldn't insert DE meta data
2)we should make sure IB test finished before we
send event 3 to hypervisor otherwise the IDLE from
event 3 will preempt IB test, which is not designed
as a compatible structure for MCBP
Signed-off-by:
Reviewed-by: Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Xu, Feifei
Sent: Monday, March 2, 2020 5:32 PM
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Long, Gang ; Li, Pauline ; Yin,
Hi Hawking
I didn't see tianci's patch merged to drm-next, is it passed our review yet ?
Please ignore my patch then
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Zhang, Hawking
Sent: Monday, March 2, 2020 5:30 PM
To: Liu, Monk
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: Tianci Yin
Sent: 2020年3月2日 9:57
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ;
Gao, Likun ; Yuan, Xiaojie ; Long,
Gang ; Li, Pauline ; Yin, Tianci (Rico)
[AMD Official Use Only - Internal Distribution Only]
This has already done by Tianchi.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Monk Liu
Sent: Monday, March 2, 2020 17:22
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk
Subject: [PATCH 2/3] drm/amdgpu: don't use
Am 02.03.20 um 10:22 schrieb Monk Liu:
scratch_reg0 is used by RLCG for register access usage
in SRIOV case.
both CP firmware and driver can invoke RLCG to do
certain register access (through scratch_reg0/1/2/3)
but rlcg now dosen't have race concern so if two
clients are in parallel doing the
what:
we found sometimes IDLE fail after vf guest finished IB test
on GFX ring1 (pipe1)
why:
below is what CP team stated (Manu):
GFX Pipe 1 is there in HW, but as part of optimization all driver
decided not to use pipe 1 at all, otherwise driver has to sacrifice
context so all 7 context will not
scratch_reg0 is used by RLCG for register access usage
in SRIOV case.
both CP firmware and driver can invoke RLCG to do
certain register access (through scratch_reg0/1/2/3)
but rlcg now dosen't have race concern so if two
clients are in parallel doing the RLCG reg access
then we are colliding,
1)for gfx IB test we shouldn't insert DE meta data
2)we should make sure IB test finished before we
send event 3 to hypervisor otherwise the IDLE from
event 3 will preempt IB test, which is not designed
as a compatible structure for MCBP
Signed-off-by: Monk Liu
---
On Sat, 2020-02-29 at 14:46 -0500, Nicolas Dufresne wrote:
> >
> > 1. I think we should completely disable running the CI on MRs which
> > are
> > marked WIP. Speaking from personal experience, I usually make a lot
> > of
> > changes to my MRs before they are merged, so it is a waste of CI
> >
Le samedi 29 février 2020 à 19:14 +0100, Timur Kristóf a écrit :
> On Fri, 2020-02-28 at 10:43 +, Daniel Stone wrote:
> > On Fri, 28 Feb 2020 at 10:06, Erik Faye-Lund
> > wrote:
> > > On Fri, 2020-02-28 at 11:40 +0200, Lionel Landwerlin wrote:
> > > > Yeah, changes on vulkan drivers or
Hi Jason,
I personally think the suggestion are still a relatively good
brainstorm data for those implicated. Of course, those not implicated
in the CI scripting itself, I'd say just keep in mind that nothing is
black and white and every changes end-up being time consuming.
Le dimanche 01 mars
Le samedi 29 février 2020 à 15:54 -0600, Jason Ekstrand a écrit :
> On Sat, Feb 29, 2020 at 3:47 PM Timur Kristóf wrote:
> > On Sat, 2020-02-29 at 14:46 -0500, Nicolas Dufresne wrote:
> > > > 1. I think we should completely disable running the CI on MRs which
> > > > are
> > > > marked WIP.
On Fri, 2020-02-28 at 10:43 +, Daniel Stone wrote:
> On Fri, 28 Feb 2020 at 10:06, Erik Faye-Lund
> wrote:
> > On Fri, 2020-02-28 at 11:40 +0200, Lionel Landwerlin wrote:
> > > Yeah, changes on vulkan drivers or backend compilers should be
> > > fairly
> > > sandboxed.
> > >
> > > We also
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