RE: [PATCH] SWDEV-227226 [AWS][Linux]ReallyQuick test failed, guest dmesg and host dmesg have error

[Gu, JiaWei (Will)]

[AMD Official Use Only - Internal Distribution Only]

Ping..

-Original Message-
From: Jiawei  
Sent: Wednesday, March 25, 2020 4:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gu, JiaWei (Will) 
Subject: [PATCH] SWDEV-227226 [AWS][Linux]ReallyQuick test failed, guest dmesg 
and host dmesg have error

root cause: compute job timeout for sriov/passthrough is 1 ms, which is too 
short for some compute benchmark

solution: extend the default compute lockup timeout to 6 ms

Signed-off-by: Jiawei 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3607a63f48bb..88360b220a8f 100755
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2680,12 +2680,12 @@ static int 
amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
 * By default timeout for non compute jobs is 1.
 * And there is no timeout enforced on compute jobs.
 * In SR-IOV or passthrough mode, timeout for compute
-* jobs are 1 by default.
+* jobs are 6 by default.
 */
adev->gfx_timeout = msecs_to_jiffies(1);
adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
-   adev->compute_timeout = adev->gfx_timeout;
+   adev->compute_timeout =  msecs_to_jiffies(6);
else
adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
 
--
2.20.1
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Re: [RFC PATCH 1/2] drm/amdgpu: add direct ib pool

[Koenig, Christian]

Yeah that's on my TODO list for quite a while as well.

But we even need three IB pools. One very small for the IB tests, one for 
direct VM updates and one for the rest.

So please make the pool a parameter to ib_get() and not the hack you have below.

Thanks,
Christian.

Am 26.03.2020 03:02 schrieb "Pan, Xinhui" :
Another ib poll for direct submit.
Any jobs schedule IBs without dependence on gpu scheduler should use
this pool firstly.

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  3 ++-
 5 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7dd74253e7b6..c01423ffb8ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -849,6 +849,7 @@ struct amdgpu_device {
 struct amdgpu_ring  *rings[AMDGPU_MAX_RINGS];
 boolib_pool_ready;
 struct amdgpu_sa_managerring_tmp_bo;
+   struct amdgpu_sa_managerring_tmp_bo_direct;

 /* interrupts */
 struct amdgpu_irq   irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8304d0c87899..28be4efb3d5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -920,7 +920,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 parser->entity = entity;

 ring = to_amdgpu_ring(entity->rq->sched);
-   r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
+   r =  amdgpu_ib_get(adev, (unsigned long )vm|0x1, 
ring->funcs->parse_cs ?
chunk_ib->ib_bytes : 0, ib);
 if (r) {
 DRM_ERROR("Failed to get ib !\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index bece01f1cf09..f2e08c372d57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -66,7 +66,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 int r;

 if (size) {
-   r = amdgpu_sa_bo_new(>ring_tmp_bo,
+   r = amdgpu_sa_bo_new(vm ? >ring_tmp_bo : 
>ring_tmp_bo_direct,
   >sa_bo, size, 256);
 if (r) {
 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
@@ -75,7 +75,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,

 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);

-   if (!vm)
+   if (!((unsigned long)vm & ~0x1))
 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 }

@@ -310,6 +310,13 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
 return r;
 }

+   r = amdgpu_sa_bo_manager_init(adev, >ring_tmp_bo_direct,
+ AMDGPU_IB_POOL_SIZE*64*1024,
+ AMDGPU_GPU_PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT);
+   if (r) {
+   return r;
+   }
 adev->ib_pool_ready = true;

 return 0;
@@ -327,6 +334,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
 {
 if (adev->ib_pool_ready) {
 amdgpu_sa_bo_manager_fini(adev, >ring_tmp_bo);
+   amdgpu_sa_bo_manager_fini(adev, >ring_tmp_bo_direct);
 adev->ib_pool_ready = false;
 }
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 4981e443a884..6a63826c6760 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -88,6 +88,12 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned 
num_ibs,

 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
  struct amdgpu_job **job)
+{
+   return amdgpu_job_alloc_with_ib_direct(adev, size, job, 0);
+}
+
+int amdgpu_job_alloc_with_ib_direct(struct amdgpu_device *adev, unsigned size,
+struct amdgpu_job **job, int direct)
 {
 int r;

@@ -95,7 +101,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 
unsigned size,
 if (r)
 return r;

-   r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
+   r = amdgpu_ib_get(adev, direct ? NULL : 0x1, size, &(*job)->ibs[0]);
 if (r)
 kfree(*job);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 2e2110dddb76..be9dd72b9912 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ 

RE: [RFC PATCH 0/2] add direct IB pool

[Liu, Monk]

That sounds a roughly doable plan to me , although we didn't hit this issue in 
our virtualization stress test but like a possible issue.

>>> So the ring test above got stuck if no ib to alloc.
Why there is IB alloc happened in ring test ? I remember there is no IB 
allocated for ring test, are you referring to IB test ?



_
Monk Liu|GPU Virtualization Team |AMD


-Original Message-
From: amd-gfx  On Behalf Of xinhui pan
Sent: Thursday, March 26, 2020 10:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kuehling, Felix 
; Pan, Xinhui ; Koenig, Christian 

Subject: [RFC PATCH 0/2] add direct IB pool

druing gpu recovery, we alloc ibs for ring tests to test if recovery succeed or 
not.

As gpu recovery parked the gpu scheduler thread, any pending jobs hold the ib 
resource has no chance to free. So the ring test above got stuck if no ib to 
alloc.

If we schedule IBs directly in job_submit_direct, we can alloc ibs in the new 
ib pool. It should have less contention.

If the IB could be freed in time, IOW, not depending on any scheduler, nor any 
other blocking code. It is better to alloc ibs in direct pool.

xinhui pan (2):
  drm/amdgpu: add direct ib pool
  drm/amdgpu: use new job alloc variation if possible

 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   |  4 ++--
 13 files changed, 35 insertions(+), 18 deletions(-)

--
2.17.1

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RE: [PATCH 2/4] SWDEV-227334 - No need support vcn decode

[Liu, Monk]

Reviewed-by: Monk Liu 

_
Monk Liu|GPU Virtualization Team |AMD


-Original Message-
From: amd-gfx  On Behalf Of Deng, Emily
Sent: Thursday, March 26, 2020 11:16 AM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/4] SWDEV-227334 - No need support vcn decode

[AMD Official Use Only - Internal Distribution Only]

Ping.

Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx  On Behalf Of 
>Emily Deng
>Sent: Wednesday, March 25, 2020 4:33 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily 
>Subject: [PATCH 2/4] SWDEV-227334 - No need support vcn decode
>
>As no need to support vcn decode feature, so diable the ring.
>
>Signed-off-by: Emily Deng 
>---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>index ec8091a..febd4c2 100644
>--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>@@ -223,6 +223,10 @@ static int vcn_v2_0_hw_init(void *handle)
>   if (r)
>   goto done;
>
>+  //Disable vcn decode for sriov
>+  if (amdgpu_sriov_vf(adev))
>+  ring->sched.ready = false;
>+
>   for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>   ring = >vcn.inst->ring_enc[i];
>   r = amdgpu_ring_test_helper(ring);
>--
>2.7.4
>
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RE: [PATCH 2/4] SWDEV-227334 - No need support vcn decode

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Ping.

Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx  On Behalf Of Emily
>Deng
>Sent: Wednesday, March 25, 2020 4:33 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily 
>Subject: [PATCH 2/4] SWDEV-227334 - No need support vcn decode
>
>As no need to support vcn decode feature, so diable the ring.
>
>Signed-off-by: Emily Deng 
>---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>index ec8091a..febd4c2 100644
>--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>@@ -223,6 +223,10 @@ static int vcn_v2_0_hw_init(void *handle)
>   if (r)
>   goto done;
>
>+  //Disable vcn decode for sriov
>+  if (amdgpu_sriov_vf(adev))
>+  ring->sched.ready = false;
>+
>   for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>   ring = >vcn.inst->ring_enc[i];
>   r = amdgpu_ring_test_helper(ring);
>--
>2.7.4
>
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Re: [PATCH] drm/amdgpu: fix the missing braces

[Huang Rui]

On Wed, Mar 25, 2020 at 11:47:08PM +0800, Das, Nirmoy wrote:
> Hi Ray,
> 
> I pushed a fix few minutes ago :)
> 

No problem, that's fine. I should have looked at the mail list firstly.

Thanks,
Ray

> 
> Regards,
> 
> Nirmoy
> 
> On 3/25/20 4:39 PM, Huang Rui wrote:
> > The braces are missed around amdgpu_ttm_training_reserve_vram_init().
> >
> > Signed-off-by: Huang Rui 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > index b397148..8afe62a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > @@ -1938,10 +1938,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
> >  *The reserved vram for memory training must be pinned to the specified
> >  *place on the VRAM, so reserve it early.
> >  */
> > -   if (!amdgpu_sriov_vf(adev))
> > +   if (!amdgpu_sriov_vf(adev)) {
> > r = amdgpu_ttm_training_reserve_vram_init(adev);
> > if (r)
> > return r;
> > +   }
> >   
> > /* allocate memory as required for VGA
> >  * This is used for VGA emulation and pre-OS scanout buffers to
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Re: [PATCH] drm/ttm: clean up the inteface which is not used

[Huang Rui]

On Thu, Mar 26, 2020 at 01:30:31AM +0800, Christian König wrote:
> Am 25.03.20 um 18:27 schrieb Alex Deucher:
> > On Wed, Mar 25, 2020 at 1:20 PM Christian König
> >  wrote:
> >> Am 25.03.20 um 16:34 schrieb Huang Rui:
> >>> invalidate_caches is actually not used, so clean it up.
> >>>
> >>> Signed-off-by: Huang Rui 
> >> Already had the same patch around for a while, looks like I've just
> >> forgot to commit it.
> >>
> >> Reviewed-by: Christian König 
> >>
> > Is it already in drm-misc and just hasn't made it into
> > amd-staging-drm-next yet?  I can try and rebase next week if so.
> 
> Ah! Yeah there it is:
> 
> > commit 5e791166d377c539db0f889e7793204912c374da
> > Author: Christian König 
> > Date:   Fri Jan 10 16:09:54 2020 +0100
> >
> >     drm/ttm: nuke invalidate_caches callback
> >
> >     Another completely unused feature.
> >
> >     Signed-off-by: Christian König 
> >     Reviewed-by: Huang Rui 
> >     Link: 
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fpatch%2F348265%2Fdata=02%7C01%7Cray.huang%40amd.com%7C544ea2a584b94dd75d8808d7d0e23993%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637207542363429381sdata=j9xr%2B%2F0apX3fcSVWRfljfRD%2BJVDzMe7tZ1%2FKVqZysjo%3Dreserved=0
> 
> Looks like we haven't merged that into amd-staging-drm-next yet.

I also forgot to look at this patch before. :-)
OK, let's use your orignal patch.

Thanks,
Ray

> 
> Christian.
> 
> >
> > Alex
> >
> >
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 --
> >>>drivers/gpu/drm/nouveau/nouveau_bo.c   |  7 ---
> >>>drivers/gpu/drm/qxl/qxl_ttm.c  |  6 --
> >>>drivers/gpu/drm/radeon/radeon_ttm.c|  6 --
> >>>drivers/gpu/drm/ttm/ttm_bo.c   |  8 +---
> >>>drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c |  6 --
> >>>include/drm/ttm/ttm_bo_driver.h| 13 -
> >>>7 files changed, 1 insertion(+), 51 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >>> index cd2bde6..b397148 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >>> @@ -62,11 +62,6 @@
> >>>
> >>>#define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
> >>>
> >>> -static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t 
> >>> flags)
> >>> -{
> >>> - return 0;
> >>> -}
> >>> -
> >>>/**
> >>> * amdgpu_init_mem_type - Initialize a memory manager for a specific 
> >>> type of
> >>> * memory request.
> >>> @@ -1746,7 +1741,6 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
> >>>.ttm_tt_create = _ttm_tt_create,
> >>>.ttm_tt_populate = _ttm_tt_populate,
> >>>.ttm_tt_unpopulate = _ttm_tt_unpopulate,
> >>> - .invalidate_caches = _invalidate_caches,
> >>>.init_mem_type = _init_mem_type,
> >>>.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
> >>>.evict_flags = _evict_flags,
> >>> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
> >>> b/drivers/gpu/drm/nouveau/nouveau_bo.c
> >>> index 1b62ccc..7dd94e6 100644
> >>> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> >>> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> >>> @@ -647,13 +647,6 @@ nouveau_ttm_tt_create(struct ttm_buffer_object *bo, 
> >>> uint32_t page_flags)
> >>>}
> >>>
> >>>static int
> >>> -nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
> >>> -{
> >>> - /* We'll do this from user space. */
> >>> - return 0;
> >>> -}
> >>> -
> >>> -static int
> >>>nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
> >>> struct ttm_mem_type_manager *man)
> >>>{
> >>> diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
> >>> index 16a5e90..62a5e42 100644
> >>> --- a/drivers/gpu/drm/qxl/qxl_ttm.c
> >>> +++ b/drivers/gpu/drm/qxl/qxl_ttm.c
> >>> @@ -48,11 +48,6 @@ static struct qxl_device *qxl_get_qdev(struct 
> >>> ttm_bo_device *bdev)
> >>>return qdev;
> >>>}
> >>>
> >>> -static int qxl_invalidate_caches(struct ttm_bo_device *bdev, uint32_t 
> >>> flags)
> >>> -{
> >>> - return 0;
> >>> -}
> >>> -
> >>>static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
> >>> struct ttm_mem_type_manager *man)
> >>>{
> >>> @@ -256,7 +251,6 @@ static void qxl_bo_move_notify(struct 
> >>> ttm_buffer_object *bo,
> >>>
> >>>static struct ttm_bo_driver qxl_bo_driver = {
> >>>.ttm_tt_create = _ttm_tt_create,
> >>> - .invalidate_caches = _invalidate_caches,
> >>>.init_mem_type = _init_mem_type,
> >>>.eviction_valuable = ttm_bo_eviction_valuable,
> >>>.evict_flags = _evict_flags,
> >>> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
> >>> b/drivers/gpu/drm/radeon/radeon_ttm.c
> >>> index f4af6703..40282bf 100644
> >>> --- 

[RFC PATCH 2/2] drm/amdgpu: use new job alloc variation if possible

[xinhui pan]

If we scheduler IB directly, then alloc job ibs in direct ib pool.

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   | 4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   | 4 ++--
 8 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
index 5727f00afc8e..75458f15f032 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
@@ -144,7 +144,7 @@ static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring 
*ring, uint32_t handle,
const unsigned ib_size_dw = 16;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib_direct(ring->adev, ib_size_dw * 4, , 
1);
if (r)
return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 54cfa3a12135..3360f5eaf19f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2123,7 +2123,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t 
src_offset,
num_loops = DIV_ROUND_UP(byte_count, max_bytes);
num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
 
-   r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, );
+   r = amdgpu_job_alloc_with_ib_direct(adev, num_dw * 4, , 
direct_submit);
if (r)
return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 5fd32ad1c575..a301f8f49997 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -1056,7 +1056,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, 
struct amdgpu_bo *bo,
goto err;
}
 
-   r = amdgpu_job_alloc_with_ib(adev, 64, );
+   r = amdgpu_job_alloc_with_ib_direct(adev, 64, , direct);
if (r)
goto err;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 59ddba137946..80b750e15c67 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -446,7 +446,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring 
*ring, uint32_t handle,
uint64_t addr;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib_direct(ring->adev, ib_size_dw * 4, , 
1);
if (r)
return r;
 
@@ -524,7 +524,7 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring 
*ring, uint32_t handle,
struct dma_fence *f = NULL;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib_direct(ring->adev, ib_size_dw * 4, , 
direct);
if (r)
return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index a41272fbcba2..7a9d917f9704 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -390,7 +390,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
uint64_t addr;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(adev, 64, );
+   r = amdgpu_job_alloc_with_ib_direct(adev, 64, , 1);
if (r)
goto err;
 
@@ -557,7 +557,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring 
*ring, uint32_t hand
uint64_t addr;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib_direct(ring->adev, ib_size_dw * 4, , 
1);
if (r)
return r;
 
@@ -610,7 +610,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t han
uint64_t addr;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib_direct(ring->adev, ib_size_dw * 4, , 
1);
if (r)
return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index d30d103e48a2..65e920892884 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -64,7 +64,8 @@ static int amdgpu_vm_sdma_prepare(struct 
amdgpu_vm_update_params *p,
unsigned int ndw = AMDGPU_VM_SDMA_MIN_NUM_DW;
int r;
 
-   r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, >job);
+   r = amdgpu_job_alloc_with_ib_direct(p->adev, ndw * 4, >job,
+   

[RFC PATCH 0/2] add direct IB pool

[xinhui pan]

druing gpu recovery, we alloc ibs for ring tests to test if recovery
succeed or not.

As gpu recovery parked the gpu scheduler thread, any pending jobs hold the ib
resource has no chance to free. So the ring test above got stuck if no
ib to alloc.

If we schedule IBs directly in job_submit_direct, we can alloc ibs in
the new ib pool. It should have less contention.

If the IB could be freed in time, IOW, not depending on any scheduler,
nor any other blocking code. It is better to alloc ibs in direct pool.

xinhui pan (2):
  drm/amdgpu: add direct ib pool
  drm/amdgpu: use new job alloc variation if possible

 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   |  4 ++--
 13 files changed, 35 insertions(+), 18 deletions(-)

-- 
2.17.1

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[RFC PATCH 1/2] drm/amdgpu: add direct ib pool

[xinhui pan]

Another ib poll for direct submit.
Any jobs schedule IBs without dependence on gpu scheduler should use
this pool firstly.

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  3 ++-
 5 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7dd74253e7b6..c01423ffb8ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -849,6 +849,7 @@ struct amdgpu_device {
struct amdgpu_ring  *rings[AMDGPU_MAX_RINGS];
boolib_pool_ready;
struct amdgpu_sa_managerring_tmp_bo;
+   struct amdgpu_sa_managerring_tmp_bo_direct;
 
/* interrupts */
struct amdgpu_irq   irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8304d0c87899..28be4efb3d5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -920,7 +920,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
parser->entity = entity;
 
ring = to_amdgpu_ring(entity->rq->sched);
-   r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
+   r =  amdgpu_ib_get(adev, (unsigned long )vm|0x1, 
ring->funcs->parse_cs ?
   chunk_ib->ib_bytes : 0, ib);
if (r) {
DRM_ERROR("Failed to get ib !\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index bece01f1cf09..f2e08c372d57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -66,7 +66,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
int r;
 
if (size) {
-   r = amdgpu_sa_bo_new(>ring_tmp_bo,
+   r = amdgpu_sa_bo_new(vm ? >ring_tmp_bo : 
>ring_tmp_bo_direct,
  >sa_bo, size, 256);
if (r) {
dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
@@ -75,7 +75,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 
ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
 
-   if (!vm)
+   if (!((unsigned long)vm & ~0x1))
ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
}
 
@@ -310,6 +310,13 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
return r;
}
 
+   r = amdgpu_sa_bo_manager_init(adev, >ring_tmp_bo_direct,
+ AMDGPU_IB_POOL_SIZE*64*1024,
+ AMDGPU_GPU_PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT);
+   if (r) {
+   return r;
+   }
adev->ib_pool_ready = true;
 
return 0;
@@ -327,6 +334,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
 {
if (adev->ib_pool_ready) {
amdgpu_sa_bo_manager_fini(adev, >ring_tmp_bo);
+   amdgpu_sa_bo_manager_fini(adev, >ring_tmp_bo_direct);
adev->ib_pool_ready = false;
}
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 4981e443a884..6a63826c6760 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -88,6 +88,12 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned 
num_ibs,
 
 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
 struct amdgpu_job **job)
+{
+   return amdgpu_job_alloc_with_ib_direct(adev, size, job, 0);
+}
+
+int amdgpu_job_alloc_with_ib_direct(struct amdgpu_device *adev, unsigned size,
+struct amdgpu_job **job, int direct)
 {
int r;
 
@@ -95,7 +101,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 
unsigned size,
if (r)
return r;
 
-   r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
+   r = amdgpu_ib_get(adev, direct ? NULL : 0x1, size, &(*job)->ibs[0]);
if (r)
kfree(*job);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 2e2110dddb76..be9dd72b9912 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -67,7 +67,8 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned 
num_ibs,
 struct amdgpu_job **job, struct amdgpu_vm *vm);
 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
 struct amdgpu_job **job);
-
+int 

Re: rv200 video corruption caused by what? kernel? Xserver? DDX? Mesa?

[Felix Miata]

Felix Miata composed on 2020-03-25 19:30 (UTC-0400):

> Alex Deucher composed on 2020-03-25 13:22 (UTC-0400):

>> Felix Miata wrote:

>>> 01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. 
>>> [AMD/ATI] RV200 [Radeon 7500/7500 LE] [1002:5157]

>>> Debian Buster and Mageia 7 are OK, but with Fedora 30 and Tumbleweed with
>>> kernels newer than 5.3.x, solid background and mouse pointer are all that
>>> paint properly: http://fm.no-ip.com/SS/rv200corrupt.png

>>> Is this a known problem? If not, whose bug tracker do I file this on, and
>>> which component?

>> Can you bisect?  The relevant radeon code in all of these components
>> hasn't really been touched in ages.  Maybe related to this:
>> https://lkml.org/lkml/2019/12/14/263
>> but that was kernel 5.4 not 5.3.

> I spent a bunch of time looking for in between kernels to try. In the process 
> I
> tried also with RV250 and RV380 without being able to repro. Eventually I 
> stumbled
> onto radeon.agpmode=-1, which worked around the corruption well enough on 
> Fedora
> and Tumbleweed.

> I got luckier and found after reading your lkml URL
> https://bugs.mageia.org/show_bug.cgi?id=26237
> reported against kernel-desktop-5.5.4-1.mga7-1-1.mga7 to produce corrupt Xorg
> video described much like observed here. That bug reports fixed with
> kernel-desktop-5.5.6-1.mga7. I found and installed 5.5.4 and confirm it's 
> broken,
> and that it's fixed in 5.5.6-2.mga7, which explains why I failed to experience
> this in Mageia, where I had jumped from 5.3.13 to 5.4.17.

> Apparently whatever Mageia did should be upstreamed if it hasn't been lately.
> Fedora's 5.5.10 remains bad.

>From Mageia kernel-desktop changelogs:
update to 5.5.6 20200312:
- work around radeon regression introduced in 5.4 series (mga#26237)
  * Revert "drm/radeon: simplify and cleanup setting the dma mask"
  * Revert "drm/radeon: handle PCIe root ports with addressing limitations"
update to 5.4.6 20200215:
- Revert "drm/radeon: simplify and cleanup setting the dma mask"
- Revert "drm/radeon: handle PCIe root ports with addressing limitations"
-- 
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Felix Miata  ***  http://fm.no-ip.com/
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Re: rv200 video corruption caused by what? kernel? Xserver? DDX? Mesa?

[Felix Miata]

Alex Deucher composed on 2020-03-25 13:22 (UTC-0400):

> Felix Miata wrote:

>> 01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. 
>> [AMD/ATI] RV200 [Radeon 7500/7500 LE] [1002:5157]

>> Debian Buster and Mageia 7 are OK, but with Fedora 30 and Tumbleweed with
>> kernels newer than 5.3.x, solid background and mouse pointer are all that
>> paint properly: http://fm.no-ip.com/SS/rv200corrupt.png

>> Is this a known problem? If not, whose bug tracker do I file this on, and
>> which component?

> Can you bisect?  The relevant radeon code in all of these components
> hasn't really been touched in ages.  Maybe related to this:
> https://lkml.org/lkml/2019/12/14/263
> but that was kernel 5.4 not 5.3.
I spent a bunch of time looking for in between kernels to try. In the process I
tried also with RV250 and RV380 without being able to repro. Eventually I 
stumbled
onto radeon.agpmode=-1, which worked around the corruption well enough on Fedora
and Tumbleweed.

I got luckier and found after reading your lkml URL
https://bugs.mageia.org/show_bug.cgi?id=26237
reported against kernel-desktop-5.5.4-1.mga7-1-1.mga7 to produce corrupt Xorg
video described much like observed here. That bug reports fixed with
kernel-desktop-5.5.6-1.mga7. I found and installed 5.5.4 and confirm it's 
broken,
and that it's fixed in 5.5.6-2.mga7, which explains why I failed to experience
this in Mageia, where I had jumped from 5.3.13 to 5.4.17.

Apparently whatever Mageia did should be upstreamed if it hasn't been lately.
Fedora's 5.5.10 remains bad.
-- 
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Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

[Alex Deucher]

On Wed, Mar 25, 2020 at 3:22 PM Tom St Denis  wrote:
>
> The PWR block was merged into the SMUIO block by revision 12 so we add
> that to the smuio_12_0_0 headers.
>
> (v2): Drop nonsensical smuio_10_0_0 header
>
> Signed-off-by: Tom St Denis 

Reviewed-by: Alex Deucher 

> ---
>  .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
>  .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h| 5 +
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
> b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> index 327b4d09f66d..9bf73284ad73 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> @@ -24,4 +24,7 @@
>  #define mmSMUIO_GFX_MISC_CNTL
>   0x00c8
>  #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX   
>   0
>
> +#define mmPWR_MISC_CNTL_STATUS   
>   0x0183
> +#define mmPWR_MISC_CNTL_STATUS_BASE_IDX  
>   1
> +
>  #endif
> diff --git 
> a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h 
> b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> index d815452cfd15..26556fa3d054 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> @@ -24,5 +24,10 @@
>  //SMUIO_GFX_MISC_CNTL
>  #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK  
>  0x0006L
>  #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT
>  0x1
> +//PWR_MISC_CNTL_STATUS
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 
>  0x0
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT   
>  0x1
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK   
>  0x0001L
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 
>  0x0006L
>
>  #endif
> --
> 2.25.1
>
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Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

[Tom St Denis]

  


On 2020-03-25 3:28 p.m., Deucher,
  Alexander wrote:


  
  
  
[AMD Public Use]
  
  
  

  While you are at it, can you clean up the local defines of
  these registers in

  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

  drivers/gpu/drm/amd/powerplay/smu_v12_0.c

  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

  and verify that the appropriate offset is used for both Renoir
  and raven?
  



I can absolutely do that tomorrow.  I'd like to get my (v2) patch
  out though since it's gating an update to umr which an internal
  team is waiting on.


As for the PWR register through um how shall I say "sheer luck"
  it actually pans out fine.  The Renoir code paths use the vega10
  IP offsets and the PWR block's offset.  Segment 0 of the PWR block
  from vega10 matches segment 1 of the SMUIO (v12) block.  So on the
  face of it the CGCG code for renoir is "wrong" but because it's
  using the wrong IP table (which happens to have the right offsets)
  it works out alright.


int soc15_set_ip_blocks(struct amdgpu_device *adev)
  {
      /* Set IP register base before any HW register access */
      switch (adev->asic_type) {
      case CHIP_VEGA10:
      case CHIP_VEGA12:
      case CHIP_RAVEN:
      case CHIP_RENOIR:
          vega10_reg_base_init(adev);
          break;
  

Strictly speaking this is wrong since renoir has its own IP
  offset table but because it reuses a lot of the KGD
  implementations from earlier hardware (and the registers happen to
  be at the same locations) this works out fine.


Tom






  

  


  Alex


  


From:
amd-gfx  on
behalf of Tom St Denis 
Sent: Wednesday, March 25, 2020 3:22 PM
To: amd-gfx@lists.freedesktop.org

Cc: StDenis, Tom 
Subject: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR
Confusion (v2)
   


  The PWR block was merged into the
SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header

Signed-off-by: Tom St Denis 
---
 .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
 .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h    | 5 +
 2 files changed, 8 insertions(+)

diff --git
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
---
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define
mmSMUIO_GFX_MISC_CNTL 
0x00c8
 #define
mmSMUIO_GFX_MISC_CNTL_BASE_IDX
0
 
+#define
mmPWR_MISC_CNTL_STATUS
0x0183
+#define
mmPWR_MISC_CNTL_STATUS_BASE_IDX   
1
+
 #endif
diff --git
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
---
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
 //SMUIO_GFX_MISC_CNTL
 #define
SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK  
0x0006L
 #define
SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT
0x1
+//PWR_MISC_CNTL_STATUS
+#define
PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 
0x0
+#define
PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT

Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

[Deucher, Alexander]

[AMD Public Use]

While you are at it, can you clean up the local defines of these registers in
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
and verify that the appropriate offset is used for both Renoir and raven?

Alex


From: amd-gfx  on behalf of Tom St Denis 

Sent: Wednesday, March 25, 2020 3:22 PM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom 
Subject: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header

Signed-off-by: Tom St Denis 
---
 .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
 .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h| 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define mmSMUIO_GFX_MISC_CNTL  
0x00c8
 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0

+#define mmPWR_MISC_CNTL_STATUS 
0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX
1
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
 //SMUIO_GFX_MISC_CNTL
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
   0x0006L
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  
   0x1
+//PWR_MISC_CNTL_STATUS
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT   
   0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 
   0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 
   0x0001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK   
   0x0006L

 #endif
--
2.25.1

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[PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

[Tom St Denis]

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header

Signed-off-by: Tom St Denis 
---
 .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
 .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h| 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define mmSMUIO_GFX_MISC_CNTL  
0x00c8
 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
 
+#define mmPWR_MISC_CNTL_STATUS 
0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX
1
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
 //SMUIO_GFX_MISC_CNTL
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
   0x0006L
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  
   0x1
+//PWR_MISC_CNTL_STATUS
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT   
   0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 
   0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 
   0x0001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK   
   0x0006L
 
 #endif
-- 
2.25.1

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rv200 video corruption caused by what? kernel? Xserver? DDX? Mesa?

[Felix Miata]

01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. 
[AMD/ATI] RV200 [Radeon 7500/7500 LE] [1002:5157]

Debian Buster and Mageia 7 are OK, but with Fedora 30 and Tumbleweed with
kernels newer than 5.3.x, solid background and mouse pointer are all that
paint properly: http://fm.no-ip.com/SS/rv200corrupt.png

Is this a known problem? If not, whose bug tracker do I file this on, and
which component?

# Debian 10 Buster
ii libdrm-amdgpu1:i386   2.4.97-1i386
ii libdrm-common 2.4.97-1all 
ii libdrm-radeon1:i386   2.4.97-1i386
ii libdrm2:i386  2.4.97-1i386
ii libgl1-mesa-dri:i386 18.3.6-2+deb10u1 i386
ii libva-drm2:i386   2.4.0-1 i386
ii libdrm-radeon1:i386   2.4.97-1i386
ii xserver-xorg-core 2:1.20.4-1  i386
ii xserver-xorg-video-radeon 1:19.0.1-1  i386
ii linux-image-4.19.0-8-686  4.19.98-1   i386  # OK Xorg video
# Mageia 7
libdricore1-9.2.4-1.mga4
libdri-drivers-20.0.1-1.mga7
libdrm2-2.4.100-1.mga7
libdrm_amdgpu1-2.4.100-1.mga7
libdrm_radeon1-2.4.100-1.mga7
libmesaegl1-20.0.1-1.mga7
libmesagl1-20.0.1-1.mga7
libmesaglu1-9.0.0-8.mga7
mesa-20.0.1-1.mga7
radeontool-1.6.3-9.mga7
x11-driver-video-ati-19.1.0-1.mga7
x11-server-xorg-1.20.7-1.mga7
kernel-desktop-5.3.13-2.mga7-1-1.mga7   # OK
kernel-desktop-5.4.17-1.mga7-1-1.mga7   # OK Xorg video
# Fedora 30
libdrm-2.4.100-1.fc30.i686
mesa-dri-drivers-19.1.8-1.fc30.i686
mesa-libEGL-19.1.8-1.fc30.i686
mesa-libgbm-19.1.8-1.fc30.i686
mesa-libGL-19.1.8-1.fc30.i686
mesa-libglapi-19.1.8-1.fc30.i686
mesa-libGLU-9.0.0-17.fc30.i686
xorg-x11-drv-ati-19.0.1-2.fc30.i686
xorg-x11-server-Xorg-1.20.6-1.fc30.i686
kernel-core-5.3.7-200.fc30.i686 # OK
kernel-core-5.4.19-100.fc30.i686# Corrupt Xorg video
# openSUSE Tumbleweed 2020030322
Mesa-20.0.1-245.1.i586
Mesa-dri-20.0.1-245.1.i586
Mesa-gallium-20.0.1-245.1.i586
Mesa-libEGL1-20.0.1-245.1.i586
Mesa-libGL1-20.0.1-245.1.i586
Mesa-libglapi0-20.0.1-245.1.i586
libdrm2-2.4.100-2.2.i586
libdrm_amdgpu1-2.4.100-2.2.i586
libdrm_radeon1-2.4.100-2.2.i586
xf86-video-ati-19.1.0-2.2.i586
xorg-x11-server-1.20.7+0-3.1.i586
kernel-default-5.3.12-2.2.i586  # OK
kernel-default-5.4.14-2.1.i586  # corrupt Xorg video
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[PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion

[Tom St Denis]

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers and then create a new smio_10_0_0 that
raven1 can use in conjunction with the pwr_10_0 headers.

Signed-off-by: Tom St Denis 
---
 .../asic_reg/smuio/smuio_10_0_0_offset.h  | 27 ++
 .../asic_reg/smuio/smuio_10_0_0_sh_mask.h | 28 +++
 .../asic_reg/smuio/smuio_12_0_0_offset.h  |  3 ++
 .../asic_reg/smuio/smuio_12_0_0_sh_mask.h |  5 
 4 files changed, 63 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h
new file mode 100644
index ..cad22fe8134b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_10_0_0_OFFSET_HEADER
+#define _smuio_10_0_0_OFFSET_HEADER
+
+#define mmSMUIO_GFX_MISC_CNTL  
0x00c8
+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h
new file mode 100644
index ..f4cddb9a16b0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_10_0_0_SH_MASK_HEADER
+#define _smuio_10_0_0_SH_MASK_HEADER
+
+//SMUIO_GFX_MISC_CNTL
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
   0x0006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  
   0x1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define mmSMUIO_GFX_MISC_CNTL  
0x00c8
 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
 
+#define mmPWR_MISC_CNTL_STATUS 
0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX   

Re: [PATCH 2/2] drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header

[Alex Deucher]

On Wed, Mar 25, 2020 at 2:08 PM Tom St Denis  wrote:
>
> The register is part of the PWR block not the GC block.  Move to
> its own header.
>
> Signed-off-by: Tom St Denis 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  .../amd/include/asic_reg/gc/gc_9_1_offset.h   |  2 --
>  .../amd/include/asic_reg/gc/gc_9_1_sh_mask.h  |  5 
>  .../include/asic_reg/pwr/pwr_10_0_offset.h| 27 +
>  .../include/asic_reg/pwr/pwr_10_0_sh_mask.h   | 30 +++
>  4 files changed, 57 insertions(+), 7 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
>  create mode 100644 
> drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h 
> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
> index ad61ffb0fd97..030e0020902b 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
> @@ -159,8 +159,6 @@
>  #define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX
>   0
>  #define mmCP_DE_DE_COUNT 
>   0x00c4
>  #define mmCP_DE_DE_COUNT_BASE_IDX
>   0
> -#define mmPWR_MISC_CNTL_STATUS   
>   0x0183
> -#define mmPWR_MISC_CNTL_STATUS_BASE_IDX  
>   0
>  #define mmCP_STALLED_STAT3   
>   0x019c
>  #define mmCP_STALLED_STAT3_BASE_IDX  
>   0
>  #define mmCP_STALLED_STAT1   
>   0x019d
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h 
> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
> index 6cc63562fd55..13bfc2e6e16f 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
> @@ -801,11 +801,6 @@
>  //CP_DE_DE_COUNT
>  #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 
>  0x0
>  #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK   
>  0xL
> -//PWR_MISC_CNTL_STATUS
> -#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 
>  0x0
> -#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT   
>  0x1
> -#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK   
>  0x0001L
> -#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 
>  0x0006L
>  //CP_STALLED_STAT3
>  #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT
>  0x0
>  #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT   
>  0x1
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h 
> b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
> new file mode 100644
> index ..e87c359ea1fe
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright (C) 2020  Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> + * in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
> LIABILITY, WHETHER IN
> + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#ifndef _pwr_10_0_OFFSET_HEADER
> +#define _pwr_10_0_OFFSET_HEADER
> +
> +#define mmPWR_MISC_CNTL_STATUS   
>   0x0183
> 

[PATCH 1/2] drm/amd/amdgpu: Add missing SMUIO v12 register to headers

[Tom St Denis]

This register is needed by umr.

Signed-off-by: Tom St Denis 
---
 .../asic_reg/smuio/smuio_12_0_0_offset.h  | 27 ++
 .../asic_reg/smuio/smuio_12_0_0_sh_mask.h | 28 +++
 2 files changed, 55 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
new file mode 100644
index ..327b4d09f66d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_12_0_0_OFFSET_HEADER
+#define _smuio_12_0_0_OFFSET_HEADER
+
+#define mmSMUIO_GFX_MISC_CNTL  
0x00c8
+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
new file mode 100644
index ..d815452cfd15
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_12_0_0_SH_MASK_HEADER
+#define _smuio_12_0_0_SH_MASK_HEADER
+
+//SMUIO_GFX_MISC_CNTL
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
   0x0006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  
   0x1
+
+#endif
-- 
2.25.1

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[PATCH 2/2] drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header

[Tom St Denis]

The register is part of the PWR block not the GC block.  Move to
its own header.

Signed-off-by: Tom St Denis 
---
 .../amd/include/asic_reg/gc/gc_9_1_offset.h   |  2 --
 .../amd/include/asic_reg/gc/gc_9_1_sh_mask.h  |  5 
 .../include/asic_reg/pwr/pwr_10_0_offset.h| 27 +
 .../include/asic_reg/pwr/pwr_10_0_sh_mask.h   | 30 +++
 4 files changed, 57 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index ad61ffb0fd97..030e0020902b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -159,8 +159,6 @@
 #define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX  
0
 #define mmCP_DE_DE_COUNT   
0x00c4
 #define mmCP_DE_DE_COUNT_BASE_IDX  
0
-#define mmPWR_MISC_CNTL_STATUS 
0x0183
-#define mmPWR_MISC_CNTL_STATUS_BASE_IDX
0
 #define mmCP_STALLED_STAT3 
0x019c
 #define mmCP_STALLED_STAT3_BASE_IDX
0
 #define mmCP_STALLED_STAT1 
0x019d
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
index 6cc63562fd55..13bfc2e6e16f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
@@ -801,11 +801,6 @@
 //CP_DE_DE_COUNT
 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT   
   0x0
 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 
   0xL
-//PWR_MISC_CNTL_STATUS
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT   
   0x0
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 
   0x1
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 
   0x0001L
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK   
   0x0006L
 //CP_STALLED_STAT3
 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT  
   0x0
 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 
   0x1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
new file mode 100644
index ..e87c359ea1fe
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _pwr_10_0_OFFSET_HEADER
+#define _pwr_10_0_OFFSET_HEADER
+
+#define mmPWR_MISC_CNTL_STATUS 
0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX
0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h
new file mode 100644
index 

Re: [PATCH -next] drm/amdgpu/uvd7: remove unnecessary conversion to bool

[Alex Deucher]

On Wed, Mar 25, 2020 at 4:17 AM Chen Zhou  wrote:
>
> The conversion to bool is not needed, remove it.
>
> Signed-off-by: Chen Zhou 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 0995378..20f10a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1694,7 +1694,7 @@ static int uvd_v7_0_set_clockgating_state(void *handle,
>   enum amd_clockgating_state state)
>  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -   bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> +   bool enable = (state == AMD_CG_STATE_GATE);
>
> uvd_v7_0_set_bypass_mode(adev, enable);
>
> --
> 2.7.4
>
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH] drm/ttm: clean up the inteface which is not used

[Christian König]

Am 25.03.20 um 18:27 schrieb Alex Deucher:

On Wed, Mar 25, 2020 at 1:20 PM Christian König
 wrote:

Am 25.03.20 um 16:34 schrieb Huang Rui:

invalidate_caches is actually not used, so clean it up.

Signed-off-by: Huang Rui 

Already had the same patch around for a while, looks like I've just
forgot to commit it.

Reviewed-by: Christian König 


Is it already in drm-misc and just hasn't made it into
amd-staging-drm-next yet?  I can try and rebase next week if so.


Ah! Yeah there it is:


commit 5e791166d377c539db0f889e7793204912c374da
Author: Christian König 
Date:   Fri Jan 10 16:09:54 2020 +0100

    drm/ttm: nuke invalidate_caches callback

    Another completely unused feature.

    Signed-off-by: Christian König 
    Reviewed-by: Huang Rui 
    Link: https://patchwork.freedesktop.org/patch/348265/


Looks like we haven't merged that into amd-staging-drm-next yet.

Christian.



Alex



---
   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 --
   drivers/gpu/drm/nouveau/nouveau_bo.c   |  7 ---
   drivers/gpu/drm/qxl/qxl_ttm.c  |  6 --
   drivers/gpu/drm/radeon/radeon_ttm.c|  6 --
   drivers/gpu/drm/ttm/ttm_bo.c   |  8 +---
   drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c |  6 --
   include/drm/ttm/ttm_bo_driver.h| 13 -
   7 files changed, 1 insertion(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index cd2bde6..b397148 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -62,11 +62,6 @@

   #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128

-static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
- return 0;
-}
-
   /**
* amdgpu_init_mem_type - Initialize a memory manager for a specific type of
* memory request.
@@ -1746,7 +1741,6 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
   .ttm_tt_create = _ttm_tt_create,
   .ttm_tt_populate = _ttm_tt_populate,
   .ttm_tt_unpopulate = _ttm_tt_unpopulate,
- .invalidate_caches = _invalidate_caches,
   .init_mem_type = _init_mem_type,
   .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
   .evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 1b62ccc..7dd94e6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -647,13 +647,6 @@ nouveau_ttm_tt_create(struct ttm_buffer_object *bo, 
uint32_t page_flags)
   }

   static int
-nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
- /* We'll do this from user space. */
- return 0;
-}
-
-static int
   nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
struct ttm_mem_type_manager *man)
   {
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index 16a5e90..62a5e42 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -48,11 +48,6 @@ static struct qxl_device *qxl_get_qdev(struct ttm_bo_device 
*bdev)
   return qdev;
   }

-static int qxl_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
- return 0;
-}
-
   static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
struct ttm_mem_type_manager *man)
   {
@@ -256,7 +251,6 @@ static void qxl_bo_move_notify(struct ttm_buffer_object *bo,

   static struct ttm_bo_driver qxl_bo_driver = {
   .ttm_tt_create = _ttm_tt_create,
- .invalidate_caches = _invalidate_caches,
   .init_mem_type = _init_mem_type,
   .eviction_valuable = ttm_bo_eviction_valuable,
   .evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index f4af6703..40282bf 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -66,11 +66,6 @@ static struct radeon_device *radeon_get_rdev(struct 
ttm_bo_device *bdev)
   return rdev;
   }

-static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
- return 0;
-}
-
   static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
   struct ttm_mem_type_manager *man)
   {
@@ -774,7 +769,6 @@ static struct ttm_bo_driver radeon_bo_driver = {
   .ttm_tt_create = _ttm_tt_create,
   .ttm_tt_populate = _ttm_tt_populate,
   .ttm_tt_unpopulate = _ttm_tt_unpopulate,
- .invalidate_caches = _invalidate_caches,
   .init_mem_type = _init_mem_type,
   .eviction_valuable = ttm_bo_eviction_valuable,
   .evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2445e2b..fd09bbb 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -343,14 +343,8 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object 
*bo,
   }

   moved:
- 

Re: [PATCH] drm/ttm: clean up the inteface which is not used

[Alex Deucher]

On Wed, Mar 25, 2020 at 1:20 PM Christian König
 wrote:
>
> Am 25.03.20 um 16:34 schrieb Huang Rui:
> > invalidate_caches is actually not used, so clean it up.
> >
> > Signed-off-by: Huang Rui 
>
> Already had the same patch around for a while, looks like I've just
> forgot to commit it.
>
> Reviewed-by: Christian König 
>

Is it already in drm-misc and just hasn't made it into
amd-staging-drm-next yet?  I can try and rebase next week if so.

Alex


> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 --
> >   drivers/gpu/drm/nouveau/nouveau_bo.c   |  7 ---
> >   drivers/gpu/drm/qxl/qxl_ttm.c  |  6 --
> >   drivers/gpu/drm/radeon/radeon_ttm.c|  6 --
> >   drivers/gpu/drm/ttm/ttm_bo.c   |  8 +---
> >   drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c |  6 --
> >   include/drm/ttm/ttm_bo_driver.h| 13 -
> >   7 files changed, 1 insertion(+), 51 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > index cd2bde6..b397148 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > @@ -62,11 +62,6 @@
> >
> >   #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
> >
> > -static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t 
> > flags)
> > -{
> > - return 0;
> > -}
> > -
> >   /**
> >* amdgpu_init_mem_type - Initialize a memory manager for a specific type 
> > of
> >* memory request.
> > @@ -1746,7 +1741,6 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
> >   .ttm_tt_create = _ttm_tt_create,
> >   .ttm_tt_populate = _ttm_tt_populate,
> >   .ttm_tt_unpopulate = _ttm_tt_unpopulate,
> > - .invalidate_caches = _invalidate_caches,
> >   .init_mem_type = _init_mem_type,
> >   .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
> >   .evict_flags = _evict_flags,
> > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
> > b/drivers/gpu/drm/nouveau/nouveau_bo.c
> > index 1b62ccc..7dd94e6 100644
> > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> > @@ -647,13 +647,6 @@ nouveau_ttm_tt_create(struct ttm_buffer_object *bo, 
> > uint32_t page_flags)
> >   }
> >
> >   static int
> > -nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
> > -{
> > - /* We'll do this from user space. */
> > - return 0;
> > -}
> > -
> > -static int
> >   nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
> >struct ttm_mem_type_manager *man)
> >   {
> > diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
> > index 16a5e90..62a5e42 100644
> > --- a/drivers/gpu/drm/qxl/qxl_ttm.c
> > +++ b/drivers/gpu/drm/qxl/qxl_ttm.c
> > @@ -48,11 +48,6 @@ static struct qxl_device *qxl_get_qdev(struct 
> > ttm_bo_device *bdev)
> >   return qdev;
> >   }
> >
> > -static int qxl_invalidate_caches(struct ttm_bo_device *bdev, uint32_t 
> > flags)
> > -{
> > - return 0;
> > -}
> > -
> >   static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
> >struct ttm_mem_type_manager *man)
> >   {
> > @@ -256,7 +251,6 @@ static void qxl_bo_move_notify(struct ttm_buffer_object 
> > *bo,
> >
> >   static struct ttm_bo_driver qxl_bo_driver = {
> >   .ttm_tt_create = _ttm_tt_create,
> > - .invalidate_caches = _invalidate_caches,
> >   .init_mem_type = _init_mem_type,
> >   .eviction_valuable = ttm_bo_eviction_valuable,
> >   .evict_flags = _evict_flags,
> > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
> > b/drivers/gpu/drm/radeon/radeon_ttm.c
> > index f4af6703..40282bf 100644
> > --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> > @@ -66,11 +66,6 @@ static struct radeon_device *radeon_get_rdev(struct 
> > ttm_bo_device *bdev)
> >   return rdev;
> >   }
> >
> > -static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t 
> > flags)
> > -{
> > - return 0;
> > -}
> > -
> >   static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
> >   struct ttm_mem_type_manager *man)
> >   {
> > @@ -774,7 +769,6 @@ static struct ttm_bo_driver radeon_bo_driver = {
> >   .ttm_tt_create = _ttm_tt_create,
> >   .ttm_tt_populate = _ttm_tt_populate,
> >   .ttm_tt_unpopulate = _ttm_tt_unpopulate,
> > - .invalidate_caches = _invalidate_caches,
> >   .init_mem_type = _init_mem_type,
> >   .eviction_valuable = ttm_bo_eviction_valuable,
> >   .evict_flags = _evict_flags,
> > diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> > index 2445e2b..fd09bbb 100644
> > --- a/drivers/gpu/drm/ttm/ttm_bo.c
> > +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> > @@ -343,14 +343,8 @@ static int ttm_bo_handle_move_mem(struct 
> > ttm_buffer_object *bo,
> >   }
> >
> >   moved:
> > - if (bo->evicted) 

Re: rv200 video corruption caused by what? kernel? Xserver? DDX? Mesa?

[Alex Deucher]

On Wed, Mar 25, 2020 at 11:36 AM Felix Miata  wrote:
>
> 01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. 
> [AMD/ATI] RV200 [Radeon 7500/7500 LE] [1002:5157]
>
> Debian Buster and Mageia 7 are OK, but with Fedora 30 and Tumbleweed with
> kernels newer than 5.3.x, solid background and mouse pointer are all that
> paint properly: http://fm.no-ip.com/SS/rv200corrupt.png
>
> Is this a known problem? If not, whose bug tracker do I file this on, and
> which component?

Can you bisect?  The relevant radeon code in all of these components
hasn't really been touched in ages.  Maybe related to this:
https://lkml.org/lkml/2019/12/14/263
but that was kernel 5.4 not 5.3.

Alex


Alex

>
> # Debian 10 Buster
> ii libdrm-amdgpu1:i386   2.4.97-1i386
> ii libdrm-common 2.4.97-1all ii libdrm-radeon1:i386   
> 2.4.97-1i386
> ii libdrm2:i386  2.4.97-1i386
> ii libgl1-mesa-dri:i386 18.3.6-2+deb10u1 i386
> ii libva-drm2:i386   2.4.0-1 i386
> ii libdrm-radeon1:i386   2.4.97-1i386
> ii xserver-xorg-core 2:1.20.4-1  i386
> ii xserver-xorg-video-radeon 1:19.0.1-1  i386
> ii linux-image-4.19.0-8-686  4.19.98-1   i386  # OK Xorg video
> # Mageia 7
> libdricore1-9.2.4-1.mga4
> libdri-drivers-20.0.1-1.mga7
> libdrm2-2.4.100-1.mga7
> libdrm_amdgpu1-2.4.100-1.mga7
> libdrm_radeon1-2.4.100-1.mga7
> libmesaegl1-20.0.1-1.mga7
> libmesagl1-20.0.1-1.mga7
> libmesaglu1-9.0.0-8.mga7
> mesa-20.0.1-1.mga7
> radeontool-1.6.3-9.mga7
> x11-driver-video-ati-19.1.0-1.mga7
> x11-server-xorg-1.20.7-1.mga7
> kernel-desktop-5.3.13-2.mga7-1-1.mga7   # OK
> kernel-desktop-5.4.17-1.mga7-1-1.mga7   # OK Xorg video
> # Fedora 30
> libdrm-2.4.100-1.fc30.i686
> mesa-dri-drivers-19.1.8-1.fc30.i686
> mesa-libEGL-19.1.8-1.fc30.i686
> mesa-libgbm-19.1.8-1.fc30.i686
> mesa-libGL-19.1.8-1.fc30.i686
> mesa-libglapi-19.1.8-1.fc30.i686
> mesa-libGLU-9.0.0-17.fc30.i686
> xorg-x11-drv-ati-19.0.1-2.fc30.i686
> xorg-x11-server-Xorg-1.20.6-1.fc30.i686
> kernel-core-5.3.7-200.fc30.i686 # OK
> kernel-core-5.4.19-100.fc30.i686# Corrupt Xorg video
> # openSUSE Tumbleweed 2020030322
> Mesa-20.0.1-245.1.i586
> Mesa-dri-20.0.1-245.1.i586
> Mesa-gallium-20.0.1-245.1.i586
> Mesa-libEGL1-20.0.1-245.1.i586
> Mesa-libGL1-20.0.1-245.1.i586
> Mesa-libglapi0-20.0.1-245.1.i586
> libdrm2-2.4.100-2.2.i586
> libdrm_amdgpu1-2.4.100-2.2.i586
> libdrm_radeon1-2.4.100-2.2.i586
> xf86-video-ati-19.1.0-2.2.i586
> xorg-x11-server-1.20.7+0-3.1.i586
> kernel-default-5.3.12-2.2.i586  # OK
> kernel-default-5.4.14-2.1.i586  # corrupt Xorg video
> --
> Evolution as taught in public schools is religion, not science.
>
>  Team OS/2 ** Reg. Linux User #211409 ** a11y rocks!
>
> Felix Miata  ***  http://fm.no-ip.com/
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH] drm/ttm: clean up the inteface which is not used

[Christian König]

Am 25.03.20 um 16:34 schrieb Huang Rui:

invalidate_caches is actually not used, so clean it up.

Signed-off-by: Huang Rui 


Already had the same patch around for a while, looks like I've just 
forgot to commit it.


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 --
  drivers/gpu/drm/nouveau/nouveau_bo.c   |  7 ---
  drivers/gpu/drm/qxl/qxl_ttm.c  |  6 --
  drivers/gpu/drm/radeon/radeon_ttm.c|  6 --
  drivers/gpu/drm/ttm/ttm_bo.c   |  8 +---
  drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c |  6 --
  include/drm/ttm/ttm_bo_driver.h| 13 -
  7 files changed, 1 insertion(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index cd2bde6..b397148 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -62,11 +62,6 @@
  
  #define AMDGPU_TTM_VRAM_MAX_DW_READ	(size_t)128
  
-static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)

-{
-   return 0;
-}
-
  /**
   * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
   * memory request.
@@ -1746,7 +1741,6 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
.ttm_tt_create = _ttm_tt_create,
.ttm_tt_populate = _ttm_tt_populate,
.ttm_tt_unpopulate = _ttm_tt_unpopulate,
-   .invalidate_caches = _invalidate_caches,
.init_mem_type = _init_mem_type,
.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
.evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 1b62ccc..7dd94e6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -647,13 +647,6 @@ nouveau_ttm_tt_create(struct ttm_buffer_object *bo, 
uint32_t page_flags)
  }
  
  static int

-nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
-   /* We'll do this from user space. */
-   return 0;
-}
-
-static int
  nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 struct ttm_mem_type_manager *man)
  {
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index 16a5e90..62a5e42 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -48,11 +48,6 @@ static struct qxl_device *qxl_get_qdev(struct ttm_bo_device 
*bdev)
return qdev;
  }
  
-static int qxl_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)

-{
-   return 0;
-}
-
  static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 struct ttm_mem_type_manager *man)
  {
@@ -256,7 +251,6 @@ static void qxl_bo_move_notify(struct ttm_buffer_object *bo,
  
  static struct ttm_bo_driver qxl_bo_driver = {

.ttm_tt_create = _ttm_tt_create,
-   .invalidate_caches = _invalidate_caches,
.init_mem_type = _init_mem_type,
.eviction_valuable = ttm_bo_eviction_valuable,
.evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index f4af6703..40282bf 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -66,11 +66,6 @@ static struct radeon_device *radeon_get_rdev(struct 
ttm_bo_device *bdev)
return rdev;
  }
  
-static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)

-{
-   return 0;
-}
-
  static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
struct ttm_mem_type_manager *man)
  {
@@ -774,7 +769,6 @@ static struct ttm_bo_driver radeon_bo_driver = {
.ttm_tt_create = _ttm_tt_create,
.ttm_tt_populate = _ttm_tt_populate,
.ttm_tt_unpopulate = _ttm_tt_unpopulate,
-   .invalidate_caches = _invalidate_caches,
.init_mem_type = _init_mem_type,
.eviction_valuable = ttm_bo_eviction_valuable,
.evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2445e2b..fd09bbb 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -343,14 +343,8 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object 
*bo,
}
  
  moved:

-   if (bo->evicted) {
-   if (bdev->driver->invalidate_caches) {
-   ret = bdev->driver->invalidate_caches(bdev, 
bo->mem.placement);
-   if (ret)
-   pr_err("Can not flush read caches\n");
-   }
+   if (bo->evicted)
bo->evicted = false;
-   }
  
  	if (bo->mem.mm_node)

bo->offset = (bo->mem.start << PAGE_SHIFT) +
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index d8ea3dd..3f3b2c7 100644
--- 

Re: [PATCH 1/4] drm/radeon: remove unneeded header include path

[Alex Deucher]

On Tue, Mar 24, 2020 at 9:14 PM Masahiro Yamada  wrote:
>
> On Wed, Mar 25, 2020 at 4:42 AM Alex Deucher  wrote:
> >
> > On Tue, Mar 24, 2020 at 12:48 PM Masahiro Yamada  
> > wrote:
> > >
> > > Hi,
> > >
> > > I think this series is a good clean-up.
> > >
> > > Could you take a look at this please?
> >
> > Can you resend?  I don't seem to have gotten it.  Must have ended up
> > getting flagged a spam or something.
>
>
> Can you take it from patchwork ?  (4 patches)
>
> https://lore.kernel.org/patchwork/project/lkml/list/?series=429491


Applied.  thanks!

Alex

>
>
> Thanks.
>
>
>
>
>
>
> > Alex
> >
> > >
> > >
> > >
> > > On Fri, Feb 14, 2020 at 12:40 AM Masahiro Yamada  
> > > wrote:
> > > >
> > > > A header include path without $(srctree)/ is suspicious because it does
> > > > not work with O= builds.
> > > >
> > > > You can build drivers/gpu/drm/radeon/ without this include path.
> > > >
> > > > Signed-off-by: Masahiro Yamada 
> > > > ---
> > > >
> > > >  drivers/gpu/drm/radeon/Makefile | 2 --
> > > >  1 file changed, 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/radeon/Makefile 
> > > > b/drivers/gpu/drm/radeon/Makefile
> > > > index c693b2ca0329..9d5d3dc1011f 100644
> > > > --- a/drivers/gpu/drm/radeon/Makefile
> > > > +++ b/drivers/gpu/drm/radeon/Makefile
> > > > @@ -3,8 +3,6 @@
> > > >  # Makefile for the drm device driver.  This driver provides support 
> > > > for the
> > > >  # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
> > > >
> > > > -ccflags-y := -Idrivers/gpu/drm/amd/include
> > > > -
> > > >  hostprogs := mkregtable
> > > >  clean-files := rn50_reg_safe.h r100_reg_safe.h r200_reg_safe.h 
> > > > rv515_reg_safe.h r300_reg_safe.h r420_reg_safe.h rs600_reg_safe.h 
> > > > r600_reg_safe.h evergreen_reg_safe.h cayman_reg_safe.h
> > > >
> > > > --
> > > > 2.17.1
> > > >
> > >
> > >
> > > --
> > > Best Regards
> > > Masahiro Yamada
> > > ___
> > > dri-devel mailing list
> > > dri-de...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
>
> --
> Best Regards
> Masahiro Yamada
> ___
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH] drm/amdgpu: fix the missing braces

[Nirmoy]

Hi Ray,

I pushed a fix few minutes ago :)


Regards,

Nirmoy

On 3/25/20 4:39 PM, Huang Rui wrote:

The braces are missed around amdgpu_ttm_training_reserve_vram_init().

Signed-off-by: Huang Rui 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b397148..8afe62a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1938,10 +1938,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 *The reserved vram for memory training must be pinned to the specified
 *place on the VRAM, so reserve it early.
 */
-   if (!amdgpu_sriov_vf(adev))
+   if (!amdgpu_sriov_vf(adev)) {
r = amdgpu_ttm_training_reserve_vram_init(adev);
if (r)
return r;
+   }
  
  	/* allocate memory as required for VGA

 * This is used for VGA emulation and pre-OS scanout buffers to

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Re: [PATCH 4/4] SWDEV-226663 - Ignore the not supported error from psp

[Luben Tuikov]

On 2020-03-25 04:33, Emily Deng wrote:
> As the VCN firmware will not use
> vf vmr now. And new psp policy won't support set tmr
> now.
> For driver compatible issue, ignore the not support error.

The line wrap is a bit off here.

> 
> Signed-off-by: Emily Deng 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index c2bf2d9..1a46050 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -205,6 +205,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
>   int index;
>   int timeout = 2000;
>   bool ras_intr = false;
> + bool skip_unsupport = false;

I'd name this "skip_unsupported", or "skip_unsupp".

You shouldn't have to initialize "skip_unsupport" to a value.
Leave it uninitialized. You want the compiler to warn you
if you're using it uninitialized, and show you the path(s)
where this happens, so you can check the logic of the patch.

>  
>   mutex_lock(>mutex);
>  
> @@ -236,6 +237,9 @@ psp_cmd_submit_buf(struct psp_context *psp,
>   amdgpu_asic_invalidate_hdp(psp->adev, NULL);
>   }
>  
> + /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command in SRIOV */
> + skip_unsupport = (psp->cmd_buf_mem->resp.status == 0x000a) && 
> amdgpu_sriov_vf(psp->adev);
> +

It's unconditionally set here, so you don't need to initialize it when you 
define it.

Regards,
Luben

>   /* In some cases, psp response status is not 0 even there is no
>* problem while the command is submitted. Some version of PSP FW
>* doesn't write 0 to that field.
> @@ -243,7 +247,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
>* during psp initialization to avoid breaking hw_init and it doesn't
>* return -EINVAL.
>*/
> - if ((psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
> + if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && 
> !ras_intr) {
>   if (ucode)
>   DRM_WARN("failed to load ucode id (%d) ",
> ucode->ucode_id);
> 

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[PATCH] drm/amdgpu: fix the missing braces

[Huang Rui]

The braces are missed around amdgpu_ttm_training_reserve_vram_init().

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b397148..8afe62a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1938,10 +1938,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 *The reserved vram for memory training must be pinned to the specified
 *place on the VRAM, so reserve it early.
 */
-   if (!amdgpu_sriov_vf(adev))
+   if (!amdgpu_sriov_vf(adev)) {
r = amdgpu_ttm_training_reserve_vram_init(adev);
if (r)
return r;
+   }
 
/* allocate memory as required for VGA
 * This is used for VGA emulation and pre-OS scanout buffers to
-- 
2.7.4

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rv200 video corruption caused by what? kernel? Xserver? DDX? Mesa?

[Felix Miata]

01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. 
[AMD/ATI] RV200 [Radeon 7500/7500 LE] [1002:5157]

Debian Buster and Mageia 7 are OK, but with Fedora 30 and Tumbleweed with
kernels newer than 5.3.x, solid background and mouse pointer are all that
paint properly: http://fm.no-ip.com/SS/rv200corrupt.png

Is this a known problem? If not, whose bug tracker do I file this on, and
which component?

# Debian 10 Buster
ii libdrm-amdgpu1:i386   2.4.97-1i386
ii libdrm-common 2.4.97-1all ii libdrm-radeon1:i386   
2.4.97-1i386
ii libdrm2:i386  2.4.97-1i386
ii libgl1-mesa-dri:i386 18.3.6-2+deb10u1 i386
ii libva-drm2:i386   2.4.0-1 i386
ii libdrm-radeon1:i386   2.4.97-1i386
ii xserver-xorg-core 2:1.20.4-1  i386
ii xserver-xorg-video-radeon 1:19.0.1-1  i386
ii linux-image-4.19.0-8-686  4.19.98-1   i386  # OK Xorg video
# Mageia 7
libdricore1-9.2.4-1.mga4
libdri-drivers-20.0.1-1.mga7
libdrm2-2.4.100-1.mga7
libdrm_amdgpu1-2.4.100-1.mga7
libdrm_radeon1-2.4.100-1.mga7
libmesaegl1-20.0.1-1.mga7
libmesagl1-20.0.1-1.mga7
libmesaglu1-9.0.0-8.mga7
mesa-20.0.1-1.mga7
radeontool-1.6.3-9.mga7
x11-driver-video-ati-19.1.0-1.mga7
x11-server-xorg-1.20.7-1.mga7
kernel-desktop-5.3.13-2.mga7-1-1.mga7   # OK
kernel-desktop-5.4.17-1.mga7-1-1.mga7   # OK Xorg video
# Fedora 30
libdrm-2.4.100-1.fc30.i686
mesa-dri-drivers-19.1.8-1.fc30.i686
mesa-libEGL-19.1.8-1.fc30.i686
mesa-libgbm-19.1.8-1.fc30.i686
mesa-libGL-19.1.8-1.fc30.i686
mesa-libglapi-19.1.8-1.fc30.i686
mesa-libGLU-9.0.0-17.fc30.i686
xorg-x11-drv-ati-19.0.1-2.fc30.i686
xorg-x11-server-Xorg-1.20.6-1.fc30.i686
kernel-core-5.3.7-200.fc30.i686 # OK
kernel-core-5.4.19-100.fc30.i686# Corrupt Xorg video
# openSUSE Tumbleweed 2020030322
Mesa-20.0.1-245.1.i586
Mesa-dri-20.0.1-245.1.i586
Mesa-gallium-20.0.1-245.1.i586
Mesa-libEGL1-20.0.1-245.1.i586
Mesa-libGL1-20.0.1-245.1.i586
Mesa-libglapi0-20.0.1-245.1.i586
libdrm2-2.4.100-2.2.i586
libdrm_amdgpu1-2.4.100-2.2.i586
libdrm_radeon1-2.4.100-2.2.i586
xf86-video-ati-19.1.0-2.2.i586
xorg-x11-server-1.20.7+0-3.1.i586
kernel-default-5.3.12-2.2.i586  # OK
kernel-default-5.4.14-2.1.i586  # corrupt Xorg video
-- 
Evolution as taught in public schools is religion, not science.

 Team OS/2 ** Reg. Linux User #211409 ** a11y rocks!

Felix Miata  ***  http://fm.no-ip.com/
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[PATCH] drm/ttm: clean up the inteface which is not used

[Huang Rui]

invalidate_caches is actually not used, so clean it up.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 --
 drivers/gpu/drm/nouveau/nouveau_bo.c   |  7 ---
 drivers/gpu/drm/qxl/qxl_ttm.c  |  6 --
 drivers/gpu/drm/radeon/radeon_ttm.c|  6 --
 drivers/gpu/drm/ttm/ttm_bo.c   |  8 +---
 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c |  6 --
 include/drm/ttm/ttm_bo_driver.h| 13 -
 7 files changed, 1 insertion(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index cd2bde6..b397148 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -62,11 +62,6 @@
 
 #define AMDGPU_TTM_VRAM_MAX_DW_READ(size_t)128
 
-static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
-   return 0;
-}
-
 /**
  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  * memory request.
@@ -1746,7 +1741,6 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
.ttm_tt_create = _ttm_tt_create,
.ttm_tt_populate = _ttm_tt_populate,
.ttm_tt_unpopulate = _ttm_tt_unpopulate,
-   .invalidate_caches = _invalidate_caches,
.init_mem_type = _init_mem_type,
.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
.evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 1b62ccc..7dd94e6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -647,13 +647,6 @@ nouveau_ttm_tt_create(struct ttm_buffer_object *bo, 
uint32_t page_flags)
 }
 
 static int
-nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
-   /* We'll do this from user space. */
-   return 0;
-}
-
-static int
 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 struct ttm_mem_type_manager *man)
 {
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index 16a5e90..62a5e42 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -48,11 +48,6 @@ static struct qxl_device *qxl_get_qdev(struct ttm_bo_device 
*bdev)
return qdev;
 }
 
-static int qxl_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
-   return 0;
-}
-
 static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 struct ttm_mem_type_manager *man)
 {
@@ -256,7 +251,6 @@ static void qxl_bo_move_notify(struct ttm_buffer_object *bo,
 
 static struct ttm_bo_driver qxl_bo_driver = {
.ttm_tt_create = _ttm_tt_create,
-   .invalidate_caches = _invalidate_caches,
.init_mem_type = _init_mem_type,
.eviction_valuable = ttm_bo_eviction_valuable,
.evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index f4af6703..40282bf 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -66,11 +66,6 @@ static struct radeon_device *radeon_get_rdev(struct 
ttm_bo_device *bdev)
return rdev;
 }
 
-static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
-{
-   return 0;
-}
-
 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
struct ttm_mem_type_manager *man)
 {
@@ -774,7 +769,6 @@ static struct ttm_bo_driver radeon_bo_driver = {
.ttm_tt_create = _ttm_tt_create,
.ttm_tt_populate = _ttm_tt_populate,
.ttm_tt_unpopulate = _ttm_tt_unpopulate,
-   .invalidate_caches = _invalidate_caches,
.init_mem_type = _init_mem_type,
.eviction_valuable = ttm_bo_eviction_valuable,
.evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 2445e2b..fd09bbb 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -343,14 +343,8 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object 
*bo,
}
 
 moved:
-   if (bo->evicted) {
-   if (bdev->driver->invalidate_caches) {
-   ret = bdev->driver->invalidate_caches(bdev, 
bo->mem.placement);
-   if (ret)
-   pr_err("Can not flush read caches\n");
-   }
+   if (bo->evicted)
bo->evicted = false;
-   }
 
if (bo->mem.mm_node)
bo->offset = (bo->mem.start << PAGE_SHIFT) +
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index d8ea3dd..3f3b2c7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
@@ -736,11 +736,6 @@ static struct ttm_tt *vmw_ttm_tt_create(struct 
ttm_buffer_object *bo,
return NULL;
 }
 
-static int 

Re: [PATCH 2/4] SWDEV-227334 - No need support vcn decode

[Luben Tuikov]

On 2020-03-25 04:32, Emily Deng wrote:
> As no need to support vcn decode feature, so diable the
> ring.

"diable" --> "disable"

> 
> Signed-off-by: Emily Deng 
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index ec8091a..febd4c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -223,6 +223,10 @@ static int vcn_v2_0_hw_init(void *handle)
>   if (r)
>   goto done;
>  
> + //Disable vcn decode for sriov
> + if (amdgpu_sriov_vf(adev))
> + ring->sched.ready = false;
> +

This is really just,

ring->sched.ready = !amdgpu_sriov_vf(adev);

But I think the compiler is already optimizing it.

Regards,
Luben

>   for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>   ring = >vcn.inst->ring_enc[i];
>   r = amdgpu_ring_test_helper(ring);
> 

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Re: [PATCH 1/1] drm/amdgpu: add missing if clause guard

[Deucher, Alexander]

[AMD Public Use]

Reviewed-by: Alex Deucher 

From: Nirmoy Das 
Sent: Wednesday, March 25, 2020 11:24 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Liu, Monk ; Koenig, Christian ; 
Deucher, Alexander ; Das, Nirmoy 
Subject: [PATCH 1/1] drm/amdgpu: add missing if clause guard

Fixes: 635f3790ac964 (drm/amdgpu: don't try to reserve training bo for sriov)

compilation warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c: In function ‘amdgpu_ttm_init’:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1862:2: warning: this ‘if’ clause does 
not guard... [-Wmisleading-indentation]
 1862 |  if (!amdgpu_sriov_vf(adev))

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 54cfa3a12135..e192557db421 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1859,10 +1859,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
  *The reserved vram for memory training must be pinned to the specified
  *place on the VRAM, so reserve it early.
  */
-   if (!amdgpu_sriov_vf(adev))
+   if (!amdgpu_sriov_vf(adev)) {
 r = amdgpu_ttm_training_reserve_vram_init(adev);
 if (r)
 return r;
+   }

 /* allocate memory as required for VGA
  * This is used for VGA emulation and pre-OS scanout buffers to
--
2.25.1

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[PATCH 1/1] drm/amdgpu: add missing if clause guard

[Nirmoy Das]

Fixes: 635f3790ac964 (drm/amdgpu: don't try to reserve training bo for sriov)

compilation warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c: In function ‘amdgpu_ttm_init’:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1862:2: warning: this ‘if’ clause does 
not guard... [-Wmisleading-indentation]
 1862 |  if (!amdgpu_sriov_vf(adev))

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 54cfa3a12135..e192557db421 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1859,10 +1859,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 *The reserved vram for memory training must be pinned to the specified
 *place on the VRAM, so reserve it early.
 */
-   if (!amdgpu_sriov_vf(adev))
+   if (!amdgpu_sriov_vf(adev)) {
r = amdgpu_ttm_training_reserve_vram_init(adev);
if (r)
return r;
+   }
 
/* allocate memory as required for VGA
 * This is used for VGA emulation and pre-OS scanout buffers to
-- 
2.25.1

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Re: [PATCH 4/4] SWDEV-226663 - Ignore the not supported error from psp

[Alex Deucher]

On Wed, Mar 25, 2020 at 4:33 AM Emily Deng  wrote:
>
> As the VCN firmware will not use
> vf vmr now. And new psp policy won't support set tmr
> now.
> For driver compatible issue, ignore the not support error.
>
> Signed-off-by: Emily Deng 

Please fix the patch title.  With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index c2bf2d9..1a46050 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -205,6 +205,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
> int index;
> int timeout = 2000;
> bool ras_intr = false;
> +   bool skip_unsupport = false;
>
> mutex_lock(>mutex);
>
> @@ -236,6 +237,9 @@ psp_cmd_submit_buf(struct psp_context *psp,
> amdgpu_asic_invalidate_hdp(psp->adev, NULL);
> }
>
> +   /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command in SRIOV */
> +   skip_unsupport = (psp->cmd_buf_mem->resp.status == 0x000a) && 
> amdgpu_sriov_vf(psp->adev);
> +
> /* In some cases, psp response status is not 0 even there is no
>  * problem while the command is submitted. Some version of PSP FW
>  * doesn't write 0 to that field.
> @@ -243,7 +247,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
>  * during psp initialization to avoid breaking hw_init and it doesn't
>  * return -EINVAL.
>  */
> -   if ((psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
> +   if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && 
> !ras_intr) {
> if (ucode)
> DRM_WARN("failed to load ucode id (%d) ",
>   ucode->ucode_id);
> --
> 2.7.4
>
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Re: [PATCH 2/4] SWDEV-227334 - No need support vcn decode

[Alex Deucher]

On Wed, Mar 25, 2020 at 4:33 AM Emily Deng  wrote:
>
> As no need to support vcn decode feature, so diable the
> ring.
>
> Signed-off-by: Emily Deng 

Please fix the patch title prefix to drm/amdgpu.  An additional comment below.

> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index ec8091a..febd4c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -223,6 +223,10 @@ static int vcn_v2_0_hw_init(void *handle)
> if (r)
> goto done;
>
> +   //Disable vcn decode for sriov

Please use C style comments.

With those fixed, the patch is:
Reviewed-by: Alex Deucher 


> +   if (amdgpu_sriov_vf(adev))
> +   ring->sched.ready = false;
> +
> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> ring = >vcn.inst->ring_enc[i];
> r = amdgpu_ring_test_helper(ring);
> --
> 2.7.4
>
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Re: [PATCH 3/4] SWDEV-227979 - Add 4k resolution for virtual display

[Alex Deucher]

On Wed, Mar 25, 2020 at 4:33 AM Emily Deng  wrote:
>
> Add 4k resolution for virtual connector.
>
> Signed-off-by: Emily Deng 

Please fix the patch title.  With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 10 +++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 3c9f2d2..8656cb7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -281,7 +281,7 @@ static int dce_virtual_get_modes(struct drm_connector 
> *connector)
> static const struct mode_size {
> int w;
> int h;
> -   } common_modes[17] = {
> +   } common_modes[21] = {
> { 640,  480},
> { 720,  480},
> { 800,  600},
> @@ -298,10 +298,14 @@ static int dce_virtual_get_modes(struct drm_connector 
> *connector)
> {1680, 1050},
> {1600, 1200},
> {1920, 1080},
> -   {1920, 1200}
> +   {1920, 1200},
> +   {4096, 3112},
> +   {3656, 2664},
> +   {3840, 2160},
> +   {4096, 2160},
> };
>
> -   for (i = 0; i < 17; i++) {
> +   for (i = 0; i < 21; i++) {
> mode = drm_cvt_mode(dev, common_modes[i].w, 
> common_modes[i].h, 60, false, false, false);
> drm_mode_probed_add(connector, mode);
> }
> --
> 2.7.4
>
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Re: [PATCH 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync

[Alex Deucher]

On Wed, Mar 25, 2020 at 10:30 AM Andrey Grodzovsky
 wrote:
>
> This flag used to avoid calling mem_sync without need.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 3 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 +++
>  include/uapi/drm/amdgpu_drm.h   | 2 ++
>  4 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 8304d0c..d9ad841 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -238,6 +238,9 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser 
> *p, union drm_amdgpu_cs
>
> if (p->uf_entry.tv.bo)
> p->job->uf_addr = uf_offset;
> +
> +   p->job->sync_mem = cs->in.sync_mem;
> +
> kfree(chunk_array);
>
> /* Use this opportunity to fill in task info for the vm */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index bece01f..9168150 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -182,6 +182,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
> unsigned num_ibs,
> dma_fence_put(tmp);
> }
>
> +   if (job && job->sync_mem && ring->funcs->mem_sync)
> +   ring->funcs->mem_sync(ring);
> +
> if (ring->funcs->insert_start)
> ring->funcs->insert_start(ring);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> index 2e2110d..7b08a04 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> @@ -61,6 +61,9 @@ struct amdgpu_job {
> /* user fence handling */
> uint64_tuf_addr;
> uint64_tuf_sequence;
> +
> +   /** UMD flag to flush and invalidate caches */
> +   boolsync_mem;
>  };
>
>  int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index cfbec27..f04998d 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -566,6 +566,8 @@ struct drm_amdgpu_cs_in {
> __u32   flags;
> /** this points to __u64 * which point to cs chunks */
> __u64   chunks;
> +   /** Tell KMD to flush and invalidate caches */
> +   boolsync_mem;
>  };

I think it would be better to add this to drm_amdgpu_cs_chunk_ib.flags
or drm_amdgpu_cs_in.flags.

Alex

>
>  struct drm_amdgpu_cs_out {
> --
> 2.7.4
>
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Re: [PATCH 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion

[Luben Tuikov]

On 2020-03-25 10:29, Andrey Grodzovsky wrote:
> Add this for gfx10 and gfx9.
> 
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/nvd.h| 48 
> +
>  drivers/gpu/drm/amd/amdgpu/soc15d.h | 25 ++-
>  2 files changed, 72 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h 
> b/drivers/gpu/drm/amd/amdgpu/nvd.h
> index f3d8771..7785ea5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nvd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nvd.h
> @@ -256,6 +256,54 @@
>  #define  PACKET3_BLK_CNTX_UPDATE 0x53
>  #define  PACKET3_INCR_UPDT_STATE 0x55
>  #define  PACKET3_ACQUIRE_MEM 0x58
> +/* 1.  HEADER
> + * 2.  COHER_CNTL [30:0]
> + * 2.1 ENGINE_SEL [31:31]
> + * 2.  COHER_SIZE [31:0]
> + * 3.  COHER_SIZE_HI [7:0]
> + * 4.  COHER_BASE_LO [31:0]
> + * 5.  COHER_BASE_HI [23:0]
> + * 7.  POLL_INTERVAL [15:0]
> + * 8.  GCR_CNTL [18:0]
> + */
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0)

I think it's visually better to not break up the "#" and "define" and
to not bunch up "define" and the macro name, to intead look like this:

#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x)((x) << 0)

Which creates visual cadence, for the eyes to follow. It also creates
a vertical visual separation (reading down) since then the left column
is not just white space reading down, but breaks at the definition of
each register field. (once changed for all, you'll see it)

> + /*
> +  * 0:NOP
> +  * 1:ALL
> +  * 2:RANGE
> +  * 3:FIRST_LAST
> +  */
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2)
> + /*
> +  * 0:ALL
> +  * 1:reserved
> +  * 2:RANGE
> +  * 3:FIRST_LAST
> +  */
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11)
> + /*
> +  * 0:ALL
> +  * 1:VOL
> +  * 2:RANGE
> +  * 3:FIRST_LAST
> +  */
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x)  ((x) << 
> 13)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15)
> +#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16)
> + /*
> +  * 0: PARALLEL
> +  * 1: FORWARD
> +  * 2: REVERSE
> +  */
> +#  define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA  (1 << 18)
>  #define  PACKET3_REWIND  0x59
>  #define  PACKET3_INTERRUPT   0x5A
>  #define  PACKET3_GEN_PDEPTE  0x5B
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h 
> b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> index 295d68c..8983871 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> @@ -253,7 +253,30 @@
>  #  define PACKET3_DMA_DATA_CMD_SAIC(1 << 28)
>  #  define PACKET3_DMA_DATA_CMD_DAIC(1 << 29)
>  #  define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
> -#define  PACKET3_AQUIRE_MEM  0x58
> +#define  PACKET3_ACQUIRE_MEM 0x58
> +/* 1.  HEADER
> + * 2.  COHER_CNTL [30:0]
> + * 2.1 ENGINE_SEL [31:31]
> + * 3.  COHER_SIZE [31:0]
> + * 4.  COHER_SIZE_HI [7:0]
> + * 5.  COHER_BASE_LO [31:0]
> + * 6.  COHER_BASE_HI [23:0]
> + * 7.  POLL_INTERVAL [15:0]
> + */
> +/* COHER_CNTL fields for CP_COHER_CNTL */
> +#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) 
> ((x) << 3)
> +#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) 
> ((x) << 4)
> +#  define 
> PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)
> +#  define 
> PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)
> +#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) 
> ((x) << 18)
> +#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) 
> ((x) << 22)
> +#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) 
> ((x) << 23)
> +#  define 

Re: [PATCH] drm/amdgpu: fix hpd bo size calculation error

[Deucher, Alexander]

[AMD Public Use]

Reviewed-by: Alex Deucher 

From: Wang, Kevin(Yang) 
Sent: Wednesday, March 25, 2020 6:44 AM
To: Koenig, Christian ; Deucher, Alexander 
; Zhang, Hawking 
Cc: amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH] drm/amdgpu: fix hpd bo size calculation error


[AMD Official Use Only - Internal Distribution Only]

thanks chris.

@Deucher, Alexander @Zhang, 
Hawking
from the view of driver, could you help me review it, then give me a RB.
thanks.

Best Regards,
Kevin


From: Koenig, Christian 
Sent: Wednesday, March 25, 2020 6:28 PM
To: Wang, Kevin(Yang) 
Cc: amd-gfx@lists.freedesktop.org ; Feng, 
Kenneth ; Deucher, Alexander 
Subject: Re: [PATCH] drm/amdgpu: fix hpd bo size calculation error

Good catch! mem.size is actually the backing store size (usually in pages).

Patch is Acked-by: Christian König 

Am 25.03.2020 11:19 schrieb "Wang, Kevin(Yang)" :
the HPD bo size calculation error.
the "mem.size" can't present actual BO size all time.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7f9ac1a14e6f..91c82383b016 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1113,7 +1113,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
 return r;
 }

-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);

 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fb567cf5671b..01b22dad52fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1946,7 +1946,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 return r;
 }

-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);

 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
--
2.17.1

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[PATCH 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion

[Andrey Grodzovsky]

Add this for gfx10 and gfx9.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/nvd.h| 48 +
 drivers/gpu/drm/amd/amdgpu/soc15d.h | 25 ++-
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h
index f3d8771..7785ea5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/nvd.h
@@ -256,6 +256,54 @@
 #definePACKET3_BLK_CNTX_UPDATE 0x53
 #definePACKET3_INCR_UPDT_STATE 0x55
 #definePACKET3_ACQUIRE_MEM 0x58
+/* 1.  HEADER
+ * 2.  COHER_CNTL [30:0]
+ * 2.1 ENGINE_SEL [31:31]
+ * 2.  COHER_SIZE [31:0]
+ * 3.  COHER_SIZE_HI [7:0]
+ * 4.  COHER_BASE_LO [31:0]
+ * 5.  COHER_BASE_HI [23:0]
+ * 7.  POLL_INTERVAL [15:0]
+ * 8.  GCR_CNTL [18:0]
+ */
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0)
+   /*
+* 0:NOP
+* 1:ALL
+* 2:RANGE
+* 3:FIRST_LAST
+*/
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2)
+   /*
+* 0:ALL
+* 1:reserved
+* 2:RANGE
+* 3:FIRST_LAST
+*/
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11)
+   /*
+* 0:ALL
+* 1:VOL
+* 2:RANGE
+* 3:FIRST_LAST
+*/
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x)  ((x) << 13)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15)
+#  define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16)
+   /*
+* 0: PARALLEL
+* 1: FORWARD
+* 2: REVERSE
+*/
+#  define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA  (1 << 18)
 #definePACKET3_REWIND  0x59
 #definePACKET3_INTERRUPT   0x5A
 #definePACKET3_GEN_PDEPTE  0x5B
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h 
b/drivers/gpu/drm/amd/amdgpu/soc15d.h
index 295d68c..8983871 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
@@ -253,7 +253,30 @@
 #  define PACKET3_DMA_DATA_CMD_SAIC(1 << 28)
 #  define PACKET3_DMA_DATA_CMD_DAIC(1 << 29)
 #  define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
-#definePACKET3_AQUIRE_MEM  0x58
+#definePACKET3_ACQUIRE_MEM 0x58
+/* 1.  HEADER
+ * 2.  COHER_CNTL [30:0]
+ * 2.1 ENGINE_SEL [31:31]
+ * 3.  COHER_SIZE [31:0]
+ * 4.  COHER_SIZE_HI [7:0]
+ * 5.  COHER_BASE_LO [31:0]
+ * 6.  COHER_BASE_HI [23:0]
+ * 7.  POLL_INTERVAL [15:0]
+ */
+/* COHER_CNTL fields for CP_COHER_CNTL */
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) 
((x) << 3)
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) 
((x) << 4)
+#  define 
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) 
((x) << 15)
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) 
((x) << 18)
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) 
((x) << 22)
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) 
<< 23)
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) 
<< 25)
+#  define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) 
<< 26)
+#  define 
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)
+#  define 
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)
+#  define 
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)
+#  define 
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)
 #definePACKET3_REWIND  0x59
 #definePACKET3_LOAD_UCONFIG_REG0x5E
 #definePACKET3_LOAD_SH_REG

[PATCH 0/4] Invalidate and flush caches at the beginning of every gfx IB

[Andrey Grodzovsky]

This patchset introduces AQUIRE_MEM packet submission at the begining of each 
gfx IB
if requested by user mode client. This is helpful in solving issues with cache 
coherency
during amdgpu_test and Vulkan CTS tests.


Andrey Grodzovsky (4):
  drm/amdgpu: Add new ring callback to insert memory sync
  drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion
  drm/amdgpu: Add mem_sync implementation for all the ASICs.
  drm/amdgpu: Add a UAPI flag for user to call mem_sync

 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   |  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  4 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h  |  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 27 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 16 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 16 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 17 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 22 ++-
 drivers/gpu/drm/amd/amdgpu/nvd.h | 48 
 drivers/gpu/drm/amd/amdgpu/soc15d.h  | 25 -
 include/uapi/drm/amdgpu_drm.h|  2 ++
 12 files changed, 178 insertions(+), 6 deletions(-)

-- 
2.7.4

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[PATCH 1/4] drm/amdgpu: Add new ring callback to insert memory sync

[Andrey Grodzovsky]

Used to flush and invalidate various caches.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 448c76c..ef9c444 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -171,6 +171,7 @@ struct amdgpu_ring_funcs {
/* Try to soft recover the ring to make the fence signal */
void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
int (*preempt_ib)(struct amdgpu_ring *ring);
+   void (*mem_sync)(struct amdgpu_ring *ring);
 };
 
 struct amdgpu_ring {
-- 
2.7.4

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[PATCH 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync

[Andrey Grodzovsky]

This flag used to avoid calling mem_sync without need.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 +++
 include/uapi/drm/amdgpu_drm.h   | 2 ++
 4 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8304d0c..d9ad841 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -238,6 +238,9 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser 
*p, union drm_amdgpu_cs
 
if (p->uf_entry.tv.bo)
p->job->uf_addr = uf_offset;
+
+   p->job->sync_mem = cs->in.sync_mem;
+
kfree(chunk_array);
 
/* Use this opportunity to fill in task info for the vm */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index bece01f..9168150 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -182,6 +182,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
dma_fence_put(tmp);
}

+   if (job && job->sync_mem && ring->funcs->mem_sync)
+   ring->funcs->mem_sync(ring);
+
if (ring->funcs->insert_start)
ring->funcs->insert_start(ring);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 2e2110d..7b08a04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -61,6 +61,9 @@ struct amdgpu_job {
/* user fence handling */
uint64_tuf_addr;
uint64_tuf_sequence;
+
+   /** UMD flag to flush and invalidate caches */
+   boolsync_mem;
 };
 
 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index cfbec27..f04998d 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -566,6 +566,8 @@ struct drm_amdgpu_cs_in {
__u32   flags;
/** this points to __u64 * which point to cs chunks */
__u64   chunks;
+   /** Tell KMD to flush and invalidate caches */
+   boolsync_mem;
 };
 
 struct drm_amdgpu_cs_out {
-- 
2.7.4

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Re: [PATCH 1/4] SWDEV-227605 - Virtual display need to support multiple ctrcs

[Alex Deucher]

Please fix the subject to be "drm/amdgpu: " rather than SWDEV-

Alex

On Wed, Mar 25, 2020 at 4:24 AM Emily Deng  wrote:
>
> The crtc num is determined by virtual_display parameter.
>
> Signed-off-by: Emily Deng 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 43a1ee3..d791bfe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -38,7 +38,8 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
>  void amdgpu_virt_init_setting(struct amdgpu_device *adev)
>  {
> /* enable virtual display */
> -   adev->mode_info.num_crtc = 1;
> +   if (adev->mode_info.num_crtc == 0)
> +   adev->mode_info.num_crtc = 1;
> adev->enable_virtual_display = true;
> adev->ddev->driver->driver_features &= ~DRIVER_ATOMIC;
> adev->cg_flags = 0;
> --
> 2.7.4
>
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Re: [RFC PATCH 1/1] drm/amdgpu: rework sched_list generation

[Huang Rui]

On Tue, Mar 24, 2020 at 07:40:10PM +0800, Nirmoy Das wrote:
> Generate HW IP's sched_list in amdgpu_ring_init() instead of
> amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
> ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
> This patch also stores sched_list for all HW IPs in one big
> array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
> much more leaner.
> 
> Signed-off-by: Nirmoy Das 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|   4 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 148 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h|   3 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c|   3 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   5 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |   2 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  11 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  28 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |   2 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   4 -
>  drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |   3 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |  13 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |   5 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |   5 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  11 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  13 +-
>  drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c |   3 +-
>  drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c |   3 +-
>  drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c |   3 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |   3 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |   3 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |   6 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |   3 +-
>  drivers/gpu/drm/amd/amdgpu/si_dma.c|   3 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c  |   3 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c  |   3 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |   7 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   6 +-
>  drivers/gpu/drm/amd/amdgpu/vce_v2_0.c  |   2 +-
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c  |   3 +-
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |   3 +-
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |   6 +-
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c  |   6 +-
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  |   6 +-
>  35 files changed, 131 insertions(+), 203 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 7dd74253e7b6..ac2ab2933e12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -984,6 +984,10 @@ struct amdgpu_device {
>   charproduct_number[16];
>   charproduct_name[32];
>   charserial[16];
> +
> + /* drm scheduler list */
> + struct drm_gpu_scheduler
> *ctx_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX][AMDGPU_MAX_COMPUTE_RINGS];
> + uint32_t
> ctx_num_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];

Using the static arrays in device instance to represent the scheduler is
better than per-ring based design. But we might need more testing for the
change.

Acked-by: Huang Rui 

>  };
>  
>  static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device 
> *bdev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index 6ed36a2c5f73..24e98d674570 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -72,6 +72,15 @@ static enum gfx_pipe_priority 
> amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sch
>   }
>  }
>  
> +static unsigned int amdgpu_ctx_sched_prio_to_hw_prio(enum drm_sched_priority 
> prio,
> +  const int hw_ip)
> +{
> + if (hw_ip == AMDGPU_HW_IP_COMPUTE)
> + return amdgpu_ctx_sched_prio_to_compute_prio(prio);
> +
> + return AMDGPU_RING_PRIO_DEFAULT;
> +}
> +
>  static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, 
> const u32 ring)
>  {
>   struct amdgpu_device *adev = ctx->adev;
> @@ -90,52 +99,19 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, 
> const u32 hw_ip, const
>   entity->sequence = 1;
>   priority = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ?
>   ctx->init_priority : ctx->override_priority;
> - switch (hw_ip) {
> - case AMDGPU_HW_IP_GFX:
> - sched = >gfx.gfx_ring[0].sched;
> - scheds = 
> - num_scheds = 1;
> - break;
> - case AMDGPU_HW_IP_COMPUTE:
> - hw_prio = amdgpu_ctx_sched_prio_to_compute_prio(priority);
> - scheds = adev->gfx.compute_prio_sched[hw_prio];
> - num_scheds = adev->gfx.num_compute_sched[hw_prio];
> - break;
> - case 

Re: [PATCH 2/2] drm/amdgpu: add full TMZ support into amdgpu_ttm_map_buffer v2

[Huang Rui]

On Mon, Mar 23, 2020 at 08:24:03PM +0800, Christian König wrote:
> Am 23.03.20 um 09:29 schrieb Huang Rui:
> > On Sun, Mar 22, 2020 at 04:48:35PM +0100, Christian König wrote:
> >> This should allow us to also support VRAM->GTT moves.
> >>
> >> v2: fix missing vram_base_adjustment
> >>
> >> Signed-off-by: Christian König 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 38 
> >> ++---
> >>   1 file changed, 30 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >> index 53de99dbaead..e15a343a944b 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >> @@ -309,21 +309,21 @@ static int amdgpu_ttm_map_buffer(struct 
> >> ttm_buffer_object *bo,
> >> unsigned window, struct amdgpu_ring *ring,
> >> bool tmz, uint64_t *addr)
> >>   {
> >> -  struct ttm_dma_tt *dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
> >>struct amdgpu_device *adev = ring->adev;
> >>struct amdgpu_job *job;
> >>unsigned num_dw, num_bytes;
> >> -  dma_addr_t *dma_address;
> >>struct dma_fence *fence;
> >>uint64_t src_addr, dst_addr;
> >> +  void *cpu_addr;
> >>uint64_t flags;
> >> +  unsigned int i;
> >>int r;
> >>   
> >>BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
> >>   AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
> >>   
> >>/* Map only what can't be accessed directly */
> >> -  if (mem->start != AMDGPU_BO_INVALID_OFFSET) {
> >> +  if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
> >>*addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
> >>return 0;
> >>}
> >> @@ -351,15 +351,37 @@ static int amdgpu_ttm_map_buffer(struct 
> >> ttm_buffer_object *bo,
> >>amdgpu_ring_pad_ib(ring, >ibs[0]);
> >>WARN_ON(job->ibs[0].length_dw > num_dw);
> >>   
> >> -  dma_address = >dma_address[offset >> PAGE_SHIFT];
> >>flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
> >>if (tmz)
> >>flags |= AMDGPU_PTE_TMZ;
> >>   
> >> -  r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
> >> -  >ibs[0].ptr[num_dw]);
> >> -  if (r)
> >> -  goto error_free;
> >> +  cpu_addr = >ibs[0].ptr[num_dw];
> >> +
> >> +  if (mem->mem_type == TTM_PL_TT) {
> >> +  struct ttm_dma_tt *dma;
> >> +  dma_addr_t *dma_address;
> >> +
> >> +  dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
> >> +  dma_address = >dma_address[offset >> PAGE_SHIFT];
> >> +  r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
> >> +  cpu_addr);
> >> +  if (r)
> >> +  goto error_free;
> >> +  } else {
> >> +  dma_addr_t dma_address;
> >> +
> >> +  dma_address = (mm_node->start << PAGE_SHIFT) + offset;
> >> +  dma_address += adev->vm_manager.vram_base_offset;
> >> +
> >> +  for (i = 0; i < num_pages; ++i) {
> >> +  r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
> >> +  _address, flags, cpu_addr);
> > May I know why do we need map the page one by one here? Is it because if
> > not PL_TT, the buffer might not be continuous?
> 
> The problem is actually the other way around.
> 
> amdgpu_gart_map() expects an array with not continuous addresses for 
> PL_TT, but we have an continuous address here we want to map.
> 
> At some point we should probably switch that to using sg_tables or some 
> other better structure, but for now this should be sufficient.
> 

Got it, that makes sense, it should be vram in this path with continuous
address. Thanks!

Series are Reviewed-by: Huang Rui 

> Regards,
> Christian.
> 
> >
> > Thanks,
> > Ray
> >
> >> +  if (r)
> >> +  goto error_free;
> >> +
> >> +  dma_address += PAGE_SIZE;
> >> +  }
> >> +  }
> >>   
> >>r = amdgpu_job_submit(job, >mman.entity,
> >>  AMDGPU_FENCE_OWNER_UNDEFINED, );
> >> -- 
> >> 2.14.1
> >>
> >> ___
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cray.huang%40amd.com%7C98ca56599adf4bdc84f808d7cf2514af%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637205630497521290sdata=nDt56svLaMkectwRV4TdJ8pilHycs3wGPIPCnHvCUx4%3Dreserved=0
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Check entity rq

[Pan, Xinhui]

well, submit job with HW disabled shluld be no harm.

The only concern is that we might use up IBs if we park scheduler thread during 
recovery. 
I have saw recovery stuck in sa new functuon. 
ring test alloc IBs to test if recovery succeed or not. But if there is no 
enough IBs it will wait fences to signal. 
However we have parked the scheduler thread,  the job will never run and no 
fences will be signaled.

see, deadlock indeed. Now we are allowing job submission here. it is more 
likely that IBs might be used up.

deadlock calltrace. 
271384 [27069.375047] INFO: task gnome-shell:2507 blocked for more than 120 
seconds.
271385 [27069.382510]   Tainted: GW 5.4.0-rc7+ #1
271386 [27069.388207] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" 
disables this message.
271387 [27069.396221] gnome-shell D0  2507   2487 0x
271388 [27069.401869] Call Trace:
271389 [27069.404404]  __schedule+0x2ab/0x860
271390 [27069.408009]  ? dma_fence_wait_any_timeout+0x1a4/0x2b0
271391 [27069.413198]  schedule+0x3a/0xc0
271392 [27069.416432]  schedule_timeout+0x21d/0x3c0
271393 [27069.420583]  ? trace_hardirqs_on+0x3b/0xf0
271394 [27069.424815]  ? dma_fence_add_callback+0x6e/0xe0
271395 [27069.429449]  ? dma_fence_wait_any_timeout+0x1a4/0x2b0
271396 [27069.434640]  dma_fence_wait_any_timeout+0x205/0x2b0
271397 [27069.439633]  ? dma_fence_wait_any_timeout+0x238/0x2b0
271398 [27069.444944]  amdgpu_sa_bo_new+0x4d7/0x5c0 [amdgpu]
271399 [27069.449949]  amdgpu_ib_get+0x36/0xa0 [amdgpu]
271400 [27069.454534]  amdgpu_job_alloc_with_ib+0x4d/0x70 [amdgpu]
271401 [27069.460057]  amdgpu_vm_sdma_prepare+0x28/0x60 [amdgpu]
271402 [27069.465370]  amdgpu_vm_bo_update_mapping+0xd7/0x1f0 [amdgpu]
271403 [27069.471171]  ? mark_held_locks+0x4d/0x80
271404 [27069.475281]  amdgpu_vm_bo_update+0x3b7/0x960 [amdgpu]
271405 [27069.480538]  amdgpu_gem_va_ioctl+0x4f3/0x510 [amdgpu]
271406 [27069.485838]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
271407 [27069.491380]  drm_ioctl_kernel+0xb0/0x100 [drm]
271408 [27069.496045]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
271409 [27069.501569]  ? drm_ioctl_kernel+0xb0/0x100 [drm]
271410 [27069.506353]  drm_ioctl+0x389/0x450 [drm]
271411 [27069.510458]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
271412 [27069.516000]  ? trace_hardirqs_on+0x3b/0xf0
271413 [27069.520305]  amdgpu_drm_ioctl+0x4f/0x80 [amdgpu]
271414 [27069.525048]  do_vfs_ioctl+0xa9/0x6f0
271415 [27069.528753]  ? tomoyo_file_ioctl+0x19/0x20
271416 [27069.532972]  ksys_ioctl+0x75/0x80
271417 [27069.536396]  ? do_syscall_64+0x17/0x230
271418 [27069.540357]  __x64_sys_ioctl+0x1a/0x20
271419 [27069.544239]  do_syscall_64+0x5f/0x230


> 2020年3月25日 19:13，Koenig, Christian  写道：
> 
> Hi guys,
> 
> thanks for pointing this out Nirmoy.
> 
> Yeah, could be that I forgot to commit the patch. Currently I don't know at 
> which end of the chaos I should start to clean up.
> 
> Christian.
> 
> Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
> Hi Xinhui,
> 
> 
> Can you please check if you can reproduce the crash with 
> https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html
> 
> Christian fix it earlier, I think he forgot to push it.
> 
> 
> Regards,
> 
> Nirmoy
> 
> On 3/25/20 12:07 PM, xinhui pan wrote:
> > gpu recover will call sdma suspend/resume. In this period, ring will be
> > disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> > be false.
> >
> > If we submit any jobs in this ring-disabled period. We fail to pick up
> > a rq for vm entity and entity->rq will set to NULL.
> > amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
> > hit panic.
> >
> > Cc: Christian König 
> > Cc: Alex Deucher 
> > Cc: Felix Kuehling 
> > Signed-off-by: xinhui pan 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
> >   1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> > index cf96c335b258..d30d103e48a2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> > @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
> > amdgpu_vm_update_params *p,
> >int r;
> >   
> >entity = p->direct ? >vm->direct : >vm->delayed;
> > + if (!entity->rq)
> > + return -ENOENT;
> >ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
> >   
> >WARN_ON(ib->length_dw == 0);
> 
> 
> Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
> Hi Xinhui,
> 
> 
> Can you please check if you can reproduce the crash with 
> https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html
> 
> Christian fix it earlier, I think he forgot to push it.
> 
> 
> Regards,
> 
> Nirmoy
> 
> On 3/25/20 12:07 PM, xinhui pan wrote:
> > gpu recover will call sdma suspend/resume. In this period, ring will be
> > disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> 

Re: [PATCH] drm/amdgpu: Check entity rq

[Pan, Xinhui]

[AMD Official Use Only - Internal Distribution Only]

well, submit job with HW disabled shluld be no harm.

The only concern is that we might use up IBs if we park scheduler during 
recovery. I have saw recovery stuck in sa new functuon.

ring test alloc IBs to test if recovery succeed or not. But if there is no 
enough IBs it will wait fences to signal. However we have parked the scheduler 
thread,  the job will never run and no fences will be signaled.

see, deadlock indeed. Now we are allowing job submission here. it is more 
likely that IBs might be used up.


From: Koenig, Christian 
Sent: Wednesday, March 25, 2020 7:13:13 PM
To: Das, Nirmoy 
Cc: Pan, Xinhui ; amd-gfx@lists.freedesktop.org 
; Deucher, Alexander 
; Kuehling, Felix 
Subject: Re: [PATCH] drm/amdgpu: Check entity rq

Hi guys,

thanks for pointing this out Nirmoy.

Yeah, could be that I forgot to commit the patch. Currently I don't know at 
which end of the chaos I should start to clean up.

Christian.

Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
Hi Xinhui,


Can you please check if you can reproduce the crash with
https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html

Christian fix it earlier, I think he forgot to push it.


Regards,

Nirmoy

On 3/25/20 12:07 PM, xinhui pan wrote:
> gpu recover will call sdma suspend/resume. In this period, ring will be
> disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> be false.
>
> If we submit any jobs in this ring-disabled period. We fail to pick up
> a rq for vm entity and entity->rq will set to NULL.
> amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
> hit panic.
>
> Cc: Christian König 
> Cc: Alex Deucher 
> Cc: Felix Kuehling 
> Signed-off-by: xinhui pan 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index cf96c335b258..d30d103e48a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
> amdgpu_vm_update_params *p,
>int r;
>
>entity = p->direct ? >vm->direct : >vm->delayed;
> + if (!entity->rq)
> + return -ENOENT;
>ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
>
>WARN_ON(ib->length_dw == 0);


Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
Hi Xinhui,


Can you please check if you can reproduce the crash with
https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html

Christian fix it earlier, I think he forgot to push it.


Regards,

Nirmoy

On 3/25/20 12:07 PM, xinhui pan wrote:
> gpu recover will call sdma suspend/resume. In this period, ring will be
> disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> be false.
>
> If we submit any jobs in this ring-disabled period. We fail to pick up
> a rq for vm entity and entity->rq will set to NULL.
> amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
> hit panic.
>
> Cc: Christian König 
> Cc: Alex Deucher 
> Cc: Felix Kuehling 
> Signed-off-by: xinhui pan 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index cf96c335b258..d30d103e48a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
> amdgpu_vm_update_params *p,
>int r;
>
>entity = p->direct ? >vm->direct : >vm->delayed;
> + if (!entity->rq)
> + return -ENOENT;
>ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
>
>WARN_ON(ib->length_dw == 0);


Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
Hi Xinhui,


Can you please check if you can reproduce the crash with
https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html

Christian fix it earlier, I think he forgot to push it.


Regards,

Nirmoy

On 3/25/20 12:07 PM, xinhui pan wrote:
> gpu recover will call sdma suspend/resume. In this period, ring will be
> disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> be false.
>
> If we submit any jobs in this ring-disabled period. We fail to pick up
> a rq for vm entity and entity->rq will set to NULL.
> amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
> hit panic.
>
> Cc: Christian König 
> Cc: Alex Deucher 
> Cc: Felix Kuehling 
> Signed-off-by: xinhui pan 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index cf96c335b258..d30d103e48a2 100644
> --- 

Re: [PATCH] drm/amdgpu: Check entity rq

[Koenig, Christian]

Hi guys,

thanks for pointing this out Nirmoy.

Yeah, could be that I forgot to commit the patch. Currently I don't know at 
which end of the chaos I should start to clean up.

Christian.

Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
Hi Xinhui,


Can you please check if you can reproduce the crash with
https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html

Christian fix it earlier, I think he forgot to push it.


Regards,

Nirmoy

On 3/25/20 12:07 PM, xinhui pan wrote:
> gpu recover will call sdma suspend/resume. In this period, ring will be
> disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> be false.
>
> If we submit any jobs in this ring-disabled period. We fail to pick up
> a rq for vm entity and entity->rq will set to NULL.
> amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
> hit panic.
>
> Cc: Christian König 
> Cc: Alex Deucher 
> Cc: Felix Kuehling 
> Signed-off-by: xinhui pan 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index cf96c335b258..d30d103e48a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
> amdgpu_vm_update_params *p,
>int r;
>
>entity = p->direct ? >vm->direct : >vm->delayed;
> + if (!entity->rq)
> + return -ENOENT;
>ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
>
>WARN_ON(ib->length_dw == 0);


Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
Hi Xinhui,


Can you please check if you can reproduce the crash with
https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html

Christian fix it earlier, I think he forgot to push it.


Regards,

Nirmoy

On 3/25/20 12:07 PM, xinhui pan wrote:
> gpu recover will call sdma suspend/resume. In this period, ring will be
> disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> be false.
>
> If we submit any jobs in this ring-disabled period. We fail to pick up
> a rq for vm entity and entity->rq will set to NULL.
> amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
> hit panic.
>
> Cc: Christian König 
> Cc: Alex Deucher 
> Cc: Felix Kuehling 
> Signed-off-by: xinhui pan 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index cf96c335b258..d30d103e48a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
> amdgpu_vm_update_params *p,
>int r;
>
>entity = p->direct ? >vm->direct : >vm->delayed;
> + if (!entity->rq)
> + return -ENOENT;
>ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
>
>WARN_ON(ib->length_dw == 0);


Am 25.03.2020 12:09 schrieb "Das, Nirmoy" :
Hi Xinhui,


Can you please check if you can reproduce the crash with
https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html

Christian fix it earlier, I think he forgot to push it.


Regards,

Nirmoy

On 3/25/20 12:07 PM, xinhui pan wrote:
> gpu recover will call sdma suspend/resume. In this period, ring will be
> disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
> be false.
>
> If we submit any jobs in this ring-disabled period. We fail to pick up
> a rq for vm entity and entity->rq will set to NULL.
> amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
> hit panic.
>
> Cc: Christian König 
> Cc: Alex Deucher 
> Cc: Felix Kuehling 
> Signed-off-by: xinhui pan 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index cf96c335b258..d30d103e48a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
> amdgpu_vm_update_params *p,
>int r;
>
>entity = p->direct ? >vm->direct : >vm->delayed;
> + if (!entity->rq)
> + return -ENOENT;
>ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
>
>WARN_ON(ib->length_dw == 0);
___
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Re: [PATCH] drm/amdgpu: Check entity rq

[Nirmoy]

Hi Xinhui,


Can you please check if you can reproduce the crash with 
https://lists.freedesktop.org/archives/amd-gfx/2020-February/046414.html


Christian fix it earlier, I think he forgot to push it.


Regards,

Nirmoy

On 3/25/20 12:07 PM, xinhui pan wrote:

gpu recover will call sdma suspend/resume. In this period, ring will be
disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
be false.

If we submit any jobs in this ring-disabled period. We fail to pick up
a rq for vm entity and entity->rq will set to NULL.
amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
hit panic.

Cc: Christian König 
Cc: Alex Deucher 
Cc: Felix Kuehling 
Signed-off-by: xinhui pan 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index cf96c335b258..d30d103e48a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
amdgpu_vm_update_params *p,
int r;
  
  	entity = p->direct ? >vm->direct : >vm->delayed;

+   if (!entity->rq)
+   return -ENOENT;
ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
  
  	WARN_ON(ib->length_dw == 0);

___
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[PATCH] drm/amdgpu: Check entity rq

[xinhui pan]

gpu recover will call sdma suspend/resume. In this period, ring will be
disabled. So the vm_pte_scheds(sdma.instance[X].ring.sched)->ready will
be false.

If we submit any jobs in this ring-disabled period. We fail to pick up
a rq for vm entity and entity->rq will set to NULL.
amdgpu_vm_sdma_commit did not check the entity->rq, so fix it. Otherwise
hit panic.

Cc: Christian König 
Cc: Alex Deucher 
Cc: Felix Kuehling 
Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index cf96c335b258..d30d103e48a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
amdgpu_vm_update_params *p,
int r;
 
entity = p->direct ? >vm->direct : >vm->delayed;
+   if (!entity->rq)
+   return -ENOENT;
ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
 
WARN_ON(ib->length_dw == 0);
-- 
2.17.1

___
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Re: [PATCH] drm/amdgpu: Check entity rq

[Nirmoy]

On 3/25/20 10:23 AM, Pan, Xinhui wrote:



2020年3月25日 15:48，Koenig, Christian  写道：

Am 25.03.20 um 06:47 schrieb xinhui pan:

Hit panic during GPU recovery test. drm_sched_entity_select_rq might
set NULL to rq. So add a check like drm_sched_job_init does.

NAK, the rq should never be set to NULL in the first place.

How did that happened?

well, I have not check the details.
but just got the call trace below.
looks like sched is not ready, and drm_sched_entity_select_rq set entity->rq to 
NULL.
in the next amdgpu_vm_sdma_commit, hit panic when we deference entity->rq.


"drm/amdgpu: stop disable the scheduler during HW fini" from Christian 
should've fix it already. But


I can't find that commit in brahma/amd-staging-drm-next.

Regards,

Nirmoy



297567 [   44.667677] amdgpu :03:00.0: GPU reset begin!
297568 [   44.929047] [drm] scheduler sdma0 is not ready, skipping
297569 [   44.929048] [drm] scheduler sdma1 is not ready, skipping
297570 [   44.934608] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
297571 [   44.947941] BUG: kernel NULL pointer dereference, address: 
0038
297572 [   44.955132] #PF: supervisor read access in kernel mode
297573 [   44.960451] #PF: error_code(0x) - not-present page
297574 [   44.965714] PGD 0 P4D 0
297575 [   44.968331] Oops:  [#1] SMP PTI
297576 [   44.971911] CPU: 7 PID: 2496 Comm: gnome-shell Tainted: GW
 5.4.0-rc7+ #1
297577 [   44.980221] Hardware name: System manufacturer System Product 
Name/Z170-A, BIOS 1702 01/28/2016
297578 [   44.989177] RIP: 0010:amdgpu_vm_sdma_commit+0x55/0x190 [amdgpu]
297579 [   44.995242] Code: 47 20 80 7f 10 00 4c 8b a0 88 01 00 00 48 8b 47 08 4c 8d 
a8 70 01 00 00 75 07 4c 8d a8 88 02 00 00 49 8b 45 10 41 8b 54 24 08 <48> 8b 40 
38 85 d2 48 8d b8 30 ff ff f   f 0f 84 06 01 00 00 48 8b 80
297580 [   45.014931] RSP: 0018:b66e008839d0 EFLAGS: 00010246
297581 [   45.020504] RAX:  RBX: b66e00883a30 RCX: 
00100400
297582 [   45.028062] RDX: 003c RSI: 8df123662138 RDI: 
b66e00883a30
297583 [   45.035662] RBP: b66e00883a00 R08: b66e0088395c R09: 
b66e00883960
297584 [   45.043298] R10: 00100240 R11: 0035 R12: 
8df1425385e8
297585 [   45.050916] R13: 8df13cfd1288 R14: 8df123662138 R15: 
8df13cfd1000
297586 [   45.058524] FS:  7fcc8f6b2100() GS:8df15e38() 
knlGS:
297587 [   45.067114] CS:  0010 DS:  ES:  CR0: 80050033
297588 [   45.073206] CR2: 0038 CR3: 000641fb6006 CR4: 
003606e0
297589 [   45.080791] DR0:  DR1:  DR2: 

297590 [   45.088277] DR3:  DR6: fffe0ff0 DR7: 
0400
297591 [   45.095773] Call Trace:
297592 [   45.098354]  amdgpu_vm_bo_update_mapping+0x1c1/0x1f0 [amdgpu]
297593 [   45.104427]  ? mark_held_locks+0x4d/0x80
297594 [   45.108682]  amdgpu_vm_bo_update+0x3b7/0x960 [amdgpu]
297595 [   45.114049]  ? rcu_read_lock_sched_held+0x4f/0x80
297596 [   45.119111]  amdgpu_gem_va_ioctl+0x4f3/0x510 [amdgpu]
297597 [   45.124495]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
297598 [   45.130250]  drm_ioctl_kernel+0xb0/0x100 [drm]
297599 [   45.134988]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
297600 [   45.140742]  ? drm_ioctl_kernel+0xb0/0x100 [drm]
297601 [   45.145622]  drm_ioctl+0x389/0x450 [drm]
297602 [   45.149804]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
297603 [   45.11]  ? trace_hardirqs_on+0x3b/0xf0
297604 [   45.159892]  amdgpu_drm_ioctl+0x4f/0x80 [amdgpu]
297605 [   45.172104]  do_vfs_ioctl+0xa9/0x6f0
297606 [   45.175909]  ? tomoyo_file_ioctl+0x19/0x20
297607 [   45.180241]  ksys_ioctl+0x75/0x80
297608 [   45.183760]  ? do_syscall_64+0x17/0x230
297609 [   45.187833]  __x64_sys_ioctl+0x1a/0x20
297610 [   45.191846]  do_syscall_64+0x5f/0x230
297611 [   45.195764]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
297612 [   45.201126] RIP: 0033:0x7fcc8c7725d7


Regards,
Christian.


Cc: Christian König 
Cc: Alex Deucher 
Cc: Felix Kuehling 
Signed-off-by: xinhui pan 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index cf96c335b258..d30d103e48a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
amdgpu_vm_update_params *p,
int r;
entity = p->direct ? >vm->direct : >vm->delayed;
+   if (!entity->rq)
+   return -ENOENT;
ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
WARN_ON(ib->length_dw == 0);

___
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Re: [PATCH] drm/amdgpu: Check entity rq

[Pan, Xinhui]

> 2020年3月25日 17:23，Pan, Xinhui  写道：
> 
> 
> 
>> 2020年3月25日 15:48，Koenig, Christian  写道：
>> 
>> Am 25.03.20 um 06:47 schrieb xinhui pan:
>>> Hit panic during GPU recovery test. drm_sched_entity_select_rq might
>>> set NULL to rq. So add a check like drm_sched_job_init does.
>> 
>> NAK, the rq should never be set to NULL in the first place.
>> 
>> How did that happened?
> 
> well, I have not check the details.

so recovery will disable sdma ring. the sched->ready will be false then. 
any job submitted during suspend and resume will meet this issue.

[   99.011614] amdgpu :03:00.0: GPU reset begin!
[   99.265504] CPU: 5 PID: 163 Comm: kworker/5:1 Tainted: GW 
5.4.0-rc7+ #1
[   99.273659] Hardware name: System manufacturer System Product Name/Z170-A, 
BIOS 1702 01/28/2016
[   99.282522] Workqueue: events drm_sched_job_timedout [gpu_sched]
[   99.288682] Call Trace:
[   99.291193]  dump_stack+0x98/0xd5
[   99.294629]  sdma_v5_0_enable+0x1ab/0x1d0 [amdgpu]
[   99.299563]  sdma_v5_0_suspend+0x2a/0x30 [amdgpu]
[   99.304360]  amdgpu_device_ip_suspend_phase2+0xa3/0x110 [amdgpu]
[   99.310504]  ? amdgpu_device_ip_suspend_phase1+0x5b/0xe0 [amdgpu]
[   99.316727]  amdgpu_device_ip_suspend+0x37/0x60 [amdgpu]
[   99.322159]  amdgpu_device_pre_asic_reset+0x81/0x1f0 [amdgpu]
[   99.328054]  amdgpu_device_gpu_recover+0x27f/0xc60 [amdgpu]
[   99.333767]  amdgpu_job_timedout+0x123/0x140 [amdgpu]
[   99.338898]  drm_sched_job_timedout+0x85/0xe0 [gpu_sched]
[   99.35]  ? amdgpu_cgs_destroy_device+0x10/0x10 [amdgpu]
[   99.350145]  ? drm_sched_job_timedout+0x85/0xe0 [gpu_sched]
[   99.355834]  process_one_work+0x231/0x5c0
[   99.359927]  worker_thread+0x3f/0x3b0
[   99.363641]  ? __kthread_parkme+0x61/0x90
[   99.367701]  kthread+0x12c/0x150
[   99.371010]  ? process_one_work+0x5c0/0x5c0
[   99.375318]  ? kthread_park+0x90/0x90
[   99.379042]  ret_from_fork+0x3a/0x50


> but just got the call trace below.
> looks like sched is not ready, and drm_sched_entity_select_rq set entity->rq 
> to NULL.
> in the next amdgpu_vm_sdma_commit, hit panic when we deference entity->rq.
> 
> 297567 [   44.667677] amdgpu :03:00.0: GPU reset begin!
> 297568 [   44.929047] [drm] scheduler sdma0 is not ready, skipping
> 297569 [   44.929048] [drm] scheduler sdma1 is not ready, skipping
> 297570 [   44.934608] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
> update BO_VA (-2)
> 297571 [   44.947941] BUG: kernel NULL pointer dereference, address: 
> 0038
> 297572 [   44.955132] #PF: supervisor read access in kernel mode
> 297573 [   44.960451] #PF: error_code(0x) - not-present page
> 297574 [   44.965714] PGD 0 P4D 0
> 297575 [   44.968331] Oops:  [#1] SMP PTI
> 297576 [   44.971911] CPU: 7 PID: 2496 Comm: gnome-shell Tainted: GW  
>5.4.0-rc7+ #1
> 297577 [   44.980221] Hardware name: System manufacturer System Product 
> Name/Z170-A, BIOS 1702 01/28/2016
> 297578 [   44.989177] RIP: 0010:amdgpu_vm_sdma_commit+0x55/0x190 [amdgpu]
> 297579 [   44.995242] Code: 47 20 80 7f 10 00 4c 8b a0 88 01 00 00 48 8b 47 
> 08 4c 8d a8 70 01 00 00 75 07 4c 8d a8 88 02 00 00 49 8b 45 10 41 8b 54 24 08 
> <48> 8b 40 38 85 d2 48 8d b8 30 ff ff f   f 0f 84 06 01 00 00 48 8b 80
> 297580 [   45.014931] RSP: 0018:b66e008839d0 EFLAGS: 00010246
> 297581 [   45.020504] RAX:  RBX: b66e00883a30 RCX: 
> 00100400
> 297582 [   45.028062] RDX: 003c RSI: 8df123662138 RDI: 
> b66e00883a30
> 297583 [   45.035662] RBP: b66e00883a00 R08: b66e0088395c R09: 
> b66e00883960
> 297584 [   45.043298] R10: 00100240 R11: 0035 R12: 
> 8df1425385e8
> 297585 [   45.050916] R13: 8df13cfd1288 R14: 8df123662138 R15: 
> 8df13cfd1000
> 297586 [   45.058524] FS:  7fcc8f6b2100() GS:8df15e38() 
> knlGS:
> 297587 [   45.067114] CS:  0010 DS:  ES:  CR0: 80050033
> 297588 [   45.073206] CR2: 0038 CR3: 000641fb6006 CR4: 
> 003606e0
> 297589 [   45.080791] DR0:  DR1:  DR2: 
> 
> 297590 [   45.088277] DR3:  DR6: fffe0ff0 DR7: 
> 0400
> 297591 [   45.095773] Call Trace:
> 297592 [   45.098354]  amdgpu_vm_bo_update_mapping+0x1c1/0x1f0 [amdgpu]
> 297593 [   45.104427]  ? mark_held_locks+0x4d/0x80
> 297594 [   45.108682]  amdgpu_vm_bo_update+0x3b7/0x960 [amdgpu]
> 297595 [   45.114049]  ? rcu_read_lock_sched_held+0x4f/0x80
> 297596 [   45.119111]  amdgpu_gem_va_ioctl+0x4f3/0x510 [amdgpu]
> 297597 [   45.124495]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
> 297598 [   45.130250]  drm_ioctl_kernel+0xb0/0x100 [drm]
> 297599 [   45.134988]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
> 297600 [   45.140742]  ? drm_ioctl_kernel+0xb0/0x100 [drm]
> 297601 [   45.145622]  drm_ioctl+0x389/0x450 [drm]
> 297602 [   45.149804]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
> 297603 [   

RE: [PATCH 4/4] SWDEV-226663 - Ignore the not supported error from psp

[Liu, Monk]

Reviewed-by: Monk Liu < monk@amd.com>

_
Monk Liu|GPU Virtualization Team |AMD


-Original Message-
From: amd-gfx  On Behalf Of Emily Deng
Sent: Wednesday, March 25, 2020 4:33 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily 
Subject: [PATCH 4/4] SWDEV-226663 - Ignore the not supported error from psp

As the VCN firmware will not use
vf vmr now. And new psp policy won't support set tmr now.
For driver compatible issue, ignore the not support error.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c2bf2d9..1a46050 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -205,6 +205,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
int index;
int timeout = 2000;
bool ras_intr = false;
+   bool skip_unsupport = false;
 
mutex_lock(>mutex);
 
@@ -236,6 +237,9 @@ psp_cmd_submit_buf(struct psp_context *psp,
amdgpu_asic_invalidate_hdp(psp->adev, NULL);
}
 
+   /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command in SRIOV */
+   skip_unsupport = (psp->cmd_buf_mem->resp.status == 0x000a) && 
+amdgpu_sriov_vf(psp->adev);
+
/* In some cases, psp response status is not 0 even there is no
 * problem while the command is submitted. Some version of PSP FW
 * doesn't write 0 to that field.
@@ -243,7 +247,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
 * during psp initialization to avoid breaking hw_init and it doesn't
 * return -EINVAL.
 */
-   if ((psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
+   if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && 
+!ras_intr) {
if (ucode)
DRM_WARN("failed to load ucode id (%d) ",
  ucode->ucode_id);
--
2.7.4

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RE: [PATCH 3/4] SWDEV-227979 - Add 4k resolution for virtual display

[Liu, Monk]

Reviewed-by: Monk Liu < monk@amd.com>

_
Monk Liu|GPU Virtualization Team |AMD


-Original Message-
From: amd-gfx  On Behalf Of Emily Deng
Sent: Wednesday, March 25, 2020 4:33 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily 
Subject: [PATCH 3/4] SWDEV-227979 - Add 4k resolution for virtual display

Add 4k resolution for virtual connector.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 3c9f2d2..8656cb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -281,7 +281,7 @@ static int dce_virtual_get_modes(struct drm_connector 
*connector)
static const struct mode_size {
int w;
int h;
-   } common_modes[17] = {
+   } common_modes[21] = {
{ 640,  480},
{ 720,  480},
{ 800,  600},
@@ -298,10 +298,14 @@ static int dce_virtual_get_modes(struct drm_connector 
*connector)
{1680, 1050},
{1600, 1200},
{1920, 1080},
-   {1920, 1200}
+   {1920, 1200},
+   {4096, 3112},
+   {3656, 2664},
+   {3840, 2160},
+   {4096, 2160},
};
 
-   for (i = 0; i < 17; i++) {
+   for (i = 0; i < 21; i++) {
mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 
60, false, false, false);
drm_mode_probed_add(connector, mode);
}
-- 
2.7.4

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RE: [PATCH 1/4] SWDEV-227605 - Virtual display need to support multiple ctrcs

[Liu, Monk]

Reviewed-by: Monk Liu < monk@amd.com>

_
Monk Liu|GPU Virtualization Team |AMD


-Original Message-
From: amd-gfx  On Behalf Of Emily Deng
Sent: Wednesday, March 25, 2020 4:25 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily 
Subject: [PATCH 1/4] SWDEV-227605 - Virtual display need to support multiple 
ctrcs

The crtc num is determined by virtual_display parameter.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 43a1ee3..d791bfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -38,7 +38,8 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)  
void amdgpu_virt_init_setting(struct amdgpu_device *adev)  {
/* enable virtual display */
-   adev->mode_info.num_crtc = 1;
+   if (adev->mode_info.num_crtc == 0)
+   adev->mode_info.num_crtc = 1;
adev->enable_virtual_display = true;
adev->ddev->driver->driver_features &= ~DRIVER_ATOMIC;
adev->cg_flags = 0;
--
2.7.4

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Re: [RFC PATCH 1/1] drm/amdgpu: rework sched_list generation

[Nirmoy]

On 3/24/20 7:41 PM, Christian König wrote:

Am 24.03.20 um 12:40 schrieb Nirmoy Das:

Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
much more leaner.


Well good start, a few style nit picks below. But in general no time 
right now to review this deeply.



Thanks Christian for your quick review. I will send a updated one with 
your suggestion applied.



Regards,

Nirmoy





Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h    |   4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c    | 148 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h    |   3 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c    |   3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h    |   5 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |   2 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  11 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  28 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |   2 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h    |   4 -
  drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |   3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |  13 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |   5 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |   5 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  11 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  13 +-
  drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |   6 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/si_dma.c    |   3 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c  |   3 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c  |   3 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |   7 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   6 +-
  drivers/gpu/drm/amd/amdgpu/vce_v2_0.c  |   2 +-
  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c  |   3 +-
  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |   3 +-
  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |   6 +-
  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c  |   6 +-
  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  |   6 +-
  35 files changed, 131 insertions(+), 203 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 7dd74253e7b6..ac2ab2933e12 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -984,6 +984,10 @@ struct amdgpu_device {
  char    product_number[16];
  char    product_name[32];
  char    serial[16];
+
+    /* drm scheduler list */
+    struct drm_gpu_scheduler 
*ctx_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX][AMDGPU_MAX_COMPUTE_RINGS];

+    uint32_t ctx_num_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
  };
    static inline struct amdgpu_device *amdgpu_ttm_adev(struct 
ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

index 6ed36a2c5f73..24e98d674570 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -72,6 +72,15 @@ static enum gfx_pipe_priority 
amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sch

  }
  }
  +static unsigned int amdgpu_ctx_sched_prio_to_hw_prio(enum 
drm_sched_priority prio,

+ const int hw_ip)
+{
+    if (hw_ip == AMDGPU_HW_IP_COMPUTE)
+    return amdgpu_ctx_sched_prio_to_compute_prio(prio);
+
+    return AMDGPU_RING_PRIO_DEFAULT;
+}
+
  static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 
hw_ip, const u32 ring)

  {
  struct amdgpu_device *adev = ctx->adev;
@@ -90,52 +99,19 @@ static int amdgpu_ctx_init_entity(struct 
amdgpu_ctx *ctx, const u32 hw_ip, const

  entity->sequence = 1;
  priority = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ?
  ctx->init_priority : ctx->override_priority;
-    switch (hw_ip) {
-    case AMDGPU_HW_IP_GFX:
-    sched = >gfx.gfx_ring[0].sched;
-    scheds = 
-    num_scheds = 1;
-    break;
-    case AMDGPU_HW_IP_COMPUTE:
-    hw_prio = amdgpu_ctx_sched_prio_to_compute_prio(priority);
-    scheds = adev->gfx.compute_prio_sched[hw_prio];
-    num_scheds = adev->gfx.num_compute_sched[hw_prio];
-    break;
-    case AMDGPU_HW_IP_DMA:
-    scheds = adev->sdma.sdma_sched;
-    num_scheds = adev->sdma.num_sdma_sched;
-    break;
-    case AMDGPU_HW_IP_UVD:
-    sched = >uvd.inst[0].ring.sched;
-    scheds = 
-    num_scheds = 1;
-  

Re: [PATCH] drm/amdgpu: fix hpd bo size calculation error

[Wang, Kevin(Yang)]

[AMD Official Use Only - Internal Distribution Only]

thanks chris.

@Deucher, Alexander @Zhang, 
Hawking
from the view of driver, could you help me review it, then give me a RB.
thanks.

Best Regards,
Kevin


From: Koenig, Christian 
Sent: Wednesday, March 25, 2020 6:28 PM
To: Wang, Kevin(Yang) 
Cc: amd-gfx@lists.freedesktop.org ; Feng, 
Kenneth ; Deucher, Alexander 
Subject: Re: [PATCH] drm/amdgpu: fix hpd bo size calculation error

Good catch! mem.size is actually the backing store size (usually in pages).

Patch is Acked-by: Christian König 

Am 25.03.2020 11:19 schrieb "Wang, Kevin(Yang)" :
the HPD bo size calculation error.
the "mem.size" can't present actual BO size all time.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7f9ac1a14e6f..91c82383b016 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1113,7 +1113,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
 return r;
 }

-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);

 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fb567cf5671b..01b22dad52fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1946,7 +1946,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 return r;
 }

-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);

 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
--
2.17.1

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Re: [PATCH] drm/amdgpu: fix hpd bo size calculation error

[Koenig, Christian]

Good catch! mem.size is actually the backing store size (usually in pages).

Patch is Acked-by: Christian König 

Am 25.03.2020 11:19 schrieb "Wang, Kevin(Yang)" :
the HPD bo size calculation error.
the "mem.size" can't present actual BO size all time.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7f9ac1a14e6f..91c82383b016 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1113,7 +1113,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
 return r;
 }

-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);

 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fb567cf5671b..01b22dad52fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1946,7 +1946,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 return r;
 }

-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);

 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
--
2.17.1

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[PATCH] drm/amdgpu: fix hpd bo size calculation error

[Kevin Wang]

the HPD bo size calculation error.
the "mem.size" can't present actual BO size all time.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7f9ac1a14e6f..91c82383b016 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1113,7 +1113,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
return r;
}
 
-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);
 
amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fb567cf5671b..01b22dad52fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1946,7 +1946,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
return r;
}
 
-   memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
+   memset(hpd, 0, mec_hpd_size);
 
amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
-- 
2.17.1

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Re: [PATCH] drm/amdgpu: Check entity rq

[Pan, Xinhui]

> 2020年3月25日 15:48，Koenig, Christian  写道：
> 
> Am 25.03.20 um 06:47 schrieb xinhui pan:
>> Hit panic during GPU recovery test. drm_sched_entity_select_rq might
>> set NULL to rq. So add a check like drm_sched_job_init does.
> 
> NAK, the rq should never be set to NULL in the first place.
> 
> How did that happened?

well, I have not check the details.
but just got the call trace below.
looks like sched is not ready, and drm_sched_entity_select_rq set entity->rq to 
NULL.
in the next amdgpu_vm_sdma_commit, hit panic when we deference entity->rq.

297567 [   44.667677] amdgpu :03:00.0: GPU reset begin!
297568 [   44.929047] [drm] scheduler sdma0 is not ready, skipping
297569 [   44.929048] [drm] scheduler sdma1 is not ready, skipping
297570 [   44.934608] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
297571 [   44.947941] BUG: kernel NULL pointer dereference, address: 
0038
297572 [   44.955132] #PF: supervisor read access in kernel mode
297573 [   44.960451] #PF: error_code(0x) - not-present page
297574 [   44.965714] PGD 0 P4D 0
297575 [   44.968331] Oops:  [#1] SMP PTI
297576 [   44.971911] CPU: 7 PID: 2496 Comm: gnome-shell Tainted: GW
 5.4.0-rc7+ #1
297577 [   44.980221] Hardware name: System manufacturer System Product 
Name/Z170-A, BIOS 1702 01/28/2016
297578 [   44.989177] RIP: 0010:amdgpu_vm_sdma_commit+0x55/0x190 [amdgpu]
297579 [   44.995242] Code: 47 20 80 7f 10 00 4c 8b a0 88 01 00 00 48 8b 47 08 
4c 8d a8 70 01 00 00 75 07 4c 8d a8 88 02 00 00 49 8b 45 10 41 8b 54 24 08 <48> 
8b 40 38 85 d2 48 8d b8 30 ff ff f   f 0f 84 06 01 00 00 48 8b 80
297580 [   45.014931] RSP: 0018:b66e008839d0 EFLAGS: 00010246
297581 [   45.020504] RAX:  RBX: b66e00883a30 RCX: 
00100400
297582 [   45.028062] RDX: 003c RSI: 8df123662138 RDI: 
b66e00883a30
297583 [   45.035662] RBP: b66e00883a00 R08: b66e0088395c R09: 
b66e00883960
297584 [   45.043298] R10: 00100240 R11: 0035 R12: 
8df1425385e8
297585 [   45.050916] R13: 8df13cfd1288 R14: 8df123662138 R15: 
8df13cfd1000
297586 [   45.058524] FS:  7fcc8f6b2100() GS:8df15e38() 
knlGS:
297587 [   45.067114] CS:  0010 DS:  ES:  CR0: 80050033
297588 [   45.073206] CR2: 0038 CR3: 000641fb6006 CR4: 
003606e0
297589 [   45.080791] DR0:  DR1:  DR2: 

297590 [   45.088277] DR3:  DR6: fffe0ff0 DR7: 
0400
297591 [   45.095773] Call Trace:
297592 [   45.098354]  amdgpu_vm_bo_update_mapping+0x1c1/0x1f0 [amdgpu]
297593 [   45.104427]  ? mark_held_locks+0x4d/0x80
297594 [   45.108682]  amdgpu_vm_bo_update+0x3b7/0x960 [amdgpu]
297595 [   45.114049]  ? rcu_read_lock_sched_held+0x4f/0x80
297596 [   45.119111]  amdgpu_gem_va_ioctl+0x4f3/0x510 [amdgpu]
297597 [   45.124495]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
297598 [   45.130250]  drm_ioctl_kernel+0xb0/0x100 [drm]
297599 [   45.134988]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
297600 [   45.140742]  ? drm_ioctl_kernel+0xb0/0x100 [drm]
297601 [   45.145622]  drm_ioctl+0x389/0x450 [drm]
297602 [   45.149804]  ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu]
297603 [   45.11]  ? trace_hardirqs_on+0x3b/0xf0
297604 [   45.159892]  amdgpu_drm_ioctl+0x4f/0x80 [amdgpu]
297605 [   45.172104]  do_vfs_ioctl+0xa9/0x6f0
297606 [   45.175909]  ? tomoyo_file_ioctl+0x19/0x20
297607 [   45.180241]  ksys_ioctl+0x75/0x80
297608 [   45.183760]  ? do_syscall_64+0x17/0x230
297609 [   45.187833]  __x64_sys_ioctl+0x1a/0x20
297610 [   45.191846]  do_syscall_64+0x5f/0x230
297611 [   45.195764]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
297612 [   45.201126] RIP: 0033:0x7fcc8c7725d7

> 
> Regards,
> Christian.
> 
>> 
>> Cc: Christian König 
>> Cc: Alex Deucher 
>> Cc: Felix Kuehling 
>> Signed-off-by: xinhui pan 
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
>>  1 file changed, 2 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>> index cf96c335b258..d30d103e48a2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>> @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
>> amdgpu_vm_update_params *p,
>>  int r;
>>  entity = p->direct ? >vm->direct : >vm->delayed;
>> +if (!entity->rq)
>> +return -ENOENT;
>>  ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
>>  WARN_ON(ib->length_dw == 0);
> 

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RE: [PATCH] drm/amd/powerplay: unload mp1 for Arcturus RAS baco reset

[Xu, Feifei]

[AMD Official Use Only - Internal Distribution Only]



Reviewed-by: Feifei Xu 

-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: 2020年3月25日 16:12
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH] drm/amd/powerplay: unload mp1 for Arcturus RAS baco reset

This sequence is recommended by PMFW team for the baco reset with PMFW 
reloaded. And it seems able to address the random failure seen on Arcturus.

Change-Id: Ic5a83ad46466a12533e9f704ad06348852156e78
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4fd77c7cfc80..914c944d901a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1719,6 +1719,12 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
enum smu_baco_state state)
if (ret)
goto out;
 
+   if (ras && ras->supported) {
+   ret = smu_send_smc_msg(smu, 
SMU_MSG_PrepareMp1ForUnload, NULL);
+   if (ret)
+   goto out;
+   }
+
bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
BIF_DOORBELL_INT_CNTL,
DOORBELL_INTERRUPT_DISABLE, 0);
--
2.26.0

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RE: [PATCH 7/7] drm/amdgpu: postpone entering fullaccess mode

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Series Reviewed-by: Emily Deng 

>-Original Message-
>From: amd-gfx  On Behalf Of Monk Liu
>Sent: Wednesday, March 25, 2020 11:59 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: Liu, Monk 
>Subject: [PATCH 7/7] drm/amdgpu: postpone entering fullaccess mode
>
>if host support new handshake we only need to enter fullaccess_mode in 
>ip_init()
>part, otherwise we need to do it before reading vbios (becuase host prepares
>vbios for VF only after received REQ_GPU_INIT event under legacy handshake)
>
>Signed-off-by: Monk Liu 
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index 724ad84..b61161a 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -1814,10 +1814,14 @@ static int amdgpu_device_ip_early_init(struct
>amdgpu_device *adev)
>   return r;
>   }
>   }
>+  }
>
>+  /* we need to send REQ_GPU here for legacy handshaker otherwise the
>vbios
>+   * will not be prepared by host for this VF */
>+  if (amdgpu_sriov_vf(adev) && adev->virt.req_init_data_ver < 1) {
>   r = amdgpu_virt_request_full_gpu(adev, true);
>   if (r)
>-  return -EAGAIN;
>+  return r;
>   }
>
>   adev->pm.pp_feature = amdgpu_pp_feature_mask; @@ -1977,6
>+1981,12 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
>   if (r)
>   return r;
>
>+  if (amdgpu_sriov_vf(adev) && adev->virt.req_init_data_ver > 0) {
>+  r = amdgpu_virt_request_full_gpu(adev, true);
>+  if (r)
>+  return -EAGAIN;
>+  }
>+
>   for (i = 0; i < adev->num_ip_blocks; i++) {
>   if (!adev->ip_blocks[i].status.valid)
>   continue;
>--
>2.7.4
>
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[PATCH 3/4] SWDEV-227979 - Add 4k resolution for virtual display

[Emily Deng]

Add 4k resolution for virtual connector.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 3c9f2d2..8656cb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -281,7 +281,7 @@ static int dce_virtual_get_modes(struct drm_connector 
*connector)
static const struct mode_size {
int w;
int h;
-   } common_modes[17] = {
+   } common_modes[21] = {
{ 640,  480},
{ 720,  480},
{ 800,  600},
@@ -298,10 +298,14 @@ static int dce_virtual_get_modes(struct drm_connector 
*connector)
{1680, 1050},
{1600, 1200},
{1920, 1080},
-   {1920, 1200}
+   {1920, 1200},
+   {4096, 3112},
+   {3656, 2664},
+   {3840, 2160},
+   {4096, 2160},
};
 
-   for (i = 0; i < 17; i++) {
+   for (i = 0; i < 21; i++) {
mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 
60, false, false, false);
drm_mode_probed_add(connector, mode);
}
-- 
2.7.4

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[PATCH 4/4] SWDEV-226663 - Ignore the not supported error from psp

[Emily Deng]

As the VCN firmware will not use
vf vmr now. And new psp policy won't support set tmr
now.
For driver compatible issue, ignore the not support error.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c2bf2d9..1a46050 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -205,6 +205,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
int index;
int timeout = 2000;
bool ras_intr = false;
+   bool skip_unsupport = false;
 
mutex_lock(>mutex);
 
@@ -236,6 +237,9 @@ psp_cmd_submit_buf(struct psp_context *psp,
amdgpu_asic_invalidate_hdp(psp->adev, NULL);
}
 
+   /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command in SRIOV */
+   skip_unsupport = (psp->cmd_buf_mem->resp.status == 0x000a) && 
amdgpu_sriov_vf(psp->adev);
+
/* In some cases, psp response status is not 0 even there is no
 * problem while the command is submitted. Some version of PSP FW
 * doesn't write 0 to that field.
@@ -243,7 +247,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
 * during psp initialization to avoid breaking hw_init and it doesn't
 * return -EINVAL.
 */
-   if ((psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
+   if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && 
!ras_intr) {
if (ucode)
DRM_WARN("failed to load ucode id (%d) ",
  ucode->ucode_id);
-- 
2.7.4

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[PATCH 2/4] SWDEV-227334 - No need support vcn decode

[Emily Deng]

As no need to support vcn decode feature, so diable the
ring.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index ec8091a..febd4c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -223,6 +223,10 @@ static int vcn_v2_0_hw_init(void *handle)
if (r)
goto done;
 
+   //Disable vcn decode for sriov
+   if (amdgpu_sriov_vf(adev))
+   ring->sched.ready = false;
+
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
ring = >vcn.inst->ring_enc[i];
r = amdgpu_ring_test_helper(ring);
-- 
2.7.4

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Re: [PATCH 1/4] drm/amdgpu: don't try to reserve training bo for sriov

[Christian König]

Am 24.03.20 um 11:58 schrieb Monk Liu:

1) SRIOV guest KMD doesn't care training buffer
2) if we resered training buffer that will overlap with IP discovery
reservation because training buffer is at vram_size - 0x8000 and
IP discovery is at ()vram_size - 0x1 => vram_size -1)

Signed-off-by: Monk Liu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 665db23..54cfa3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1859,9 +1859,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 *The reserved vram for memory training must be pinned to the specified
 *place on the VRAM, so reserve it early.
 */
-   r = amdgpu_ttm_training_reserve_vram_init(adev);
-   if (r)
-   return r;
+   if (!amdgpu_sriov_vf(adev))
+   r = amdgpu_ttm_training_reserve_vram_init(adev);
+   if (r)
+   return r;


Missing { } here, apart from that the series looks good to me.

Christian.

  
  	/* allocate memory as required for VGA

 * This is used for VGA emulation and pre-OS scanout buffers to


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[PATCH 1/4] SWDEV-227605 - Virtual display need to support multiple ctrcs

[Emily Deng]

The crtc num is determined by virtual_display parameter.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 43a1ee3..d791bfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -38,7 +38,8 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
 {
/* enable virtual display */
-   adev->mode_info.num_crtc = 1;
+   if (adev->mode_info.num_crtc == 0)
+   adev->mode_info.num_crtc = 1;
adev->enable_virtual_display = true;
adev->ddev->driver->driver_features &= ~DRIVER_ATOMIC;
adev->cg_flags = 0;
-- 
2.7.4

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[PATCH -next] drm/amdgpu/uvd7: remove unnecessary conversion to bool

[Chen Zhou]

The conversion to bool is not needed, remove it.

Signed-off-by: Chen Zhou 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 0995378..20f10a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1694,7 +1694,7 @@ static int uvd_v7_0_set_clockgating_state(void *handle,
  enum amd_clockgating_state state)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-   bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+   bool enable = (state == AMD_CG_STATE_GATE);
 
uvd_v7_0_set_bypass_mode(adev, enable);
 
-- 
2.7.4

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[PATCH] drm/amd/powerplay: unload mp1 for Arcturus RAS baco reset

[Evan Quan]

This sequence is recommended by PMFW team for the baco reset
with PMFW reloaded. And it seems able to address the random
failure seen on Arcturus.

Change-Id: Ic5a83ad46466a12533e9f704ad06348852156e78
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4fd77c7cfc80..914c944d901a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1719,6 +1719,12 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
enum smu_baco_state state)
if (ret)
goto out;
 
+   if (ras && ras->supported) {
+   ret = smu_send_smc_msg(smu, 
SMU_MSG_PrepareMp1ForUnload, NULL);
+   if (ret)
+   goto out;
+   }
+
bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
BIF_DOORBELL_INT_CNTL,
DOORBELL_INTERRUPT_DISABLE, 0);
-- 
2.26.0

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Re: [PATCH] drm/amdgpu: Check entity rq

[Christian König]

Am 25.03.20 um 06:47 schrieb xinhui pan:

Hit panic during GPU recovery test. drm_sched_entity_select_rq might
set NULL to rq. So add a check like drm_sched_job_init does.


NAK, the rq should never be set to NULL in the first place.

How did that happened?

Regards,
Christian.



Cc: Christian König 
Cc: Alex Deucher 
Cc: Felix Kuehling 
Signed-off-by: xinhui pan 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index cf96c335b258..d30d103e48a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct 
amdgpu_vm_update_params *p,
int r;
  
  	entity = p->direct ? >vm->direct : >vm->delayed;

+   if (!entity->rq)
+   return -ENOENT;
ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
  
  	WARN_ON(ib->length_dw == 0);


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RE: [PATCH] drm/amdgpu: added xgmi ras error reset sequence

[Zhang, Hawking]

[AMD Official Use Only - Internal Distribution Only]

+ case CHIP_VEGA20:
+ default:

I'd suggest do nothing for default case. Other than that the patch is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
From: Clements, John 
Sent: Wednesday, March 25, 2020 14:50
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: added xgmi ras error reset sequence


[AMD Official Use Only - Internal Distribution Only]

Submitting patch to clear xgmi ras error counters inbetween ras error query
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[PATCH] drm/amdgpu: disable ras query and injection during gpu reset

[Clements, John]

[AMD Official Use Only - Internal Distribution Only]

Submitting patch to disable ras debugfs features during the entire GPU reset 
cycle


0001-drm-amdgpu-disable-ras-query-during-gpu-reset.patch
Description: 0001-drm-amdgpu-disable-ras-query-during-gpu-reset.patch
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[PATCH] drm/amdgpu: added xgmi ras error reset sequence

[Clements, John]

[AMD Official Use Only - Internal Distribution Only]

Submitting patch to clear xgmi ras error counters inbetween ras error query


0001-drm-amdgpu-added-xgmi-ras-error-reset-sequence.patch
Description: 0001-drm-amdgpu-added-xgmi-ras-error-reset-sequence.patch
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