[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Grodzovsky, Andrey
Sent: Saturday, July 11, 2020 1:54 AM
To: Li, Dennis ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ; Zhou1, Tao ; Zhang,
Hawking ; Chen, Guchun ; Koenig,
Christian
Subject: Re:
On Fri, Jul 10, 2020 at 4:38 AM Colin King wrote:
>
> From: Colin Ian King
>
> There is a spelling mistake in a DRM_ERROR error message. Fix it.
>
> Signed-off-by: Colin Ian King
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
> 1 file changed, 1 insertion(+),
From: Chiawen Huang
[Why]
when ppt disabled, the watermark doesn't get fine tune causing
underflow.
[How]
It is a temporary solution to reduce sr_xxx_time by 3 us when ppt
disable.
Signed-off-by: Chiawen Huang
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
From: Josip Pavic
[Why]
Failing to allocate a transfer function during stream construction leads
to a null pointer dereference
[How]
Handle the failed allocation by failing the stream construction
Cc: sta...@vger.kernel.org
Signed-off-by: Josip Pavic
Reviewed-by: Aric Cyr
Acked-by: Rodrigo
From: Mikita Lipski
[why]
Move code for parsing debugfs input into an array of int parameters by
specifying the max number of expected parameters
Signed-off-by: Mikita Lipski
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 259
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: hersen wu
[Why]
new calculated dispclk, dppclk are stored in
context->bw_ctx.bw.dcn.clk.dispclk_khz, dppclk_khz. Current dispclk,
dppclk are from dc->clk_mgr->clks.dispclk_khz. dcn_validate_bandwidth
compute new dispclk, dppclk. dispclk will put in use after
optimize_bandwidth when
From: hersen wu
[Why]
amdgpu_dm->backlight_caps is for single eDP only. the caps are upddated
for very connector. Real eDP caps will be overwritten by other external
display. For OLED panel, caps->aux_support is set to 1 for OLED pnael.
after external connected, caps+.aux_support is set to 0.
From: Sung Lee
[WHY]
In headless systems, if set mode is not called, hardware will not be
powered down on boot, causing HW/SW discrepancies. Powering down
hardware on boot will ensure SW state is accurate.
[HOW]
Set a timer callback on boot for 10 seconds. If set mode is not called
within that
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Updates on DML code;
* Bug fixes;
* FW and DC version update.
Best Regards
Rodrigo Siqueira
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.24
Aric Cyr (1):
drm/amd/display: 3.2.94
Chiawen
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Dmytro Laktyushkin
Our validation is a known mess with actual validation mixed with
topology configuration. This change makes sure topolgical validation is
completed before any topology changes are made so we do not run into
issues where we merge and split a pipe over the course of a
From: Dmytro Laktyushkin
Update *DynamicMetadata variables for providing more flexibility.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c| 8 +++-
Hi Michel,
We try to follow tickets reported in FDO and try to make a triage of it
(using the DC label). However, we need to find a better process to keep
track of FDO bugs and try to map some of the fixes in our weekly
promotion.
Best Regards
Rodrigo Siqueira
On 07/06, Michel Dänzer wrote:
>
On Fri, Jul 10, 2020 at 4:23 PM Jason Gunthorpe wrote:
>
> On Fri, Jul 10, 2020 at 04:02:35PM +0200, Daniel Vetter wrote:
>
> > > dma_fence only possibly makes some sense if you intend to expose the
> > > completion outside a single driver.
> > >
> > > The prefered kernel design pattern for this
On Fri, Jul 10, 2020 at 1:49 PM Nirmoy Das wrote:
>
> Fixes: 394e9a14c63d58e0f (drm/amdgpu: Need to set the baco cap before baco
> reset)
hmmm, this whole thing probably needs to be sorted a bit.
394e9a14c63d58e0f only added the baco cap check for vega10, so we
don't do it for other vega parts.
On 2020-07-10 11:50 a.m., Alex Deucher wrote:
Prevents a warning in the MST create connector case.
v2: create global fake encoders rather per connector fake encoders
to avoid running out of encoder indices.
v3: use the actual number of crtcs on the asic rather than the max
to conserve
On 7/10/20 1:24 PM, Li, Dennis wrote:
[AMD Official Use Only - Internal Distribution Only]
Hi, Andrey,
Please see my below comments.
Best Regards
Dennis Li
-Original Message-
From: Grodzovsky, Andrey
Sent: Friday, July 10, 2020 11:08 PM
To: Li, Dennis ;
Fixes: 394e9a14c63d58e0f (drm/amdgpu: Need to set the baco cap before baco
reset)
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
[AMD Official Use Only - Internal Distribution Only]
Hi, Andrey,
Please see my below comments.
Best Regards
Dennis Li
-Original Message-
From: Grodzovsky, Andrey
Sent: Friday, July 10, 2020 11:08 PM
To: Li, Dennis ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ; Zhou1, Tao
Prevents a warning in the MST create connector case.
v2: create global fake encoders rather per connector fake encoders
to avoid running out of encoder indices.
v3: use the actual number of crtcs on the asic rather than the max
to conserve encoders.
v4: v3 plus missing hunk I forgot to git add.
Ignore this. Forgot to git add one of the changes.
Alex
On Fri, Jul 10, 2020 at 11:46 AM Alex Deucher wrote:
>
> Prevents a warning in the MST create connector case.
>
> v2: create global fake encoders rather per connector fake encoders
> to avoid running out of encoder indices.
>
> v3: use
Prevents a warning in the MST create connector case.
v2: create global fake encoders rather per connector fake encoders
to avoid running out of encoder indices.
v3: use the actual number of crtcs on the asic rather than the max
to conserve encoders.
Bug:
On Fri, Jul 10, 2020 at 03:01:10PM +0200, Christian König wrote:
> Am 10.07.20 um 14:54 schrieb Jason Gunthorpe:
> > On Fri, Jul 10, 2020 at 02:48:16PM +0200, Christian König wrote:
> > > Am 10.07.20 um 14:43 schrieb Jason Gunthorpe:
> > > > On Thu, Jul 09, 2020 at 10:09:11AM +0200, Daniel Vetter
On Thu, Jul 09, 2020 at 10:09:11AM +0200, Daniel Vetter wrote:
> Hi Jason,
>
> Below the paragraph I've added after our discussions around dma-fences
> outside of drivers/gpu. Good enough for an ack on this, or want something
> changed?
>
> Thanks, Daniel
>
> > + * Note that only GPU drivers
From: Colin Ian King
There is a spelling mistake in a DRM_ERROR error message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
On Fri, Jul 10, 2020 at 02:48:16PM +0200, Christian König wrote:
> Am 10.07.20 um 14:43 schrieb Jason Gunthorpe:
> > On Thu, Jul 09, 2020 at 10:09:11AM +0200, Daniel Vetter wrote:
> > > Hi Jason,
> > >
> > > Below the paragraph I've added after our discussions around dma-fences
> > > outside of
On Fri, Jul 10, 2020 at 04:02:35PM +0200, Daniel Vetter wrote:
> > dma_fence only possibly makes some sense if you intend to expose the
> > completion outside a single driver.
> >
> > The prefered kernel design pattern for this is to connect things with
> > a function callback.
> >
> > So the
On 7/8/20 3:48 AM, Dennis Li wrote:
During GPU reset, driver should hold on all external access to
GPU, otherwise psp will randomly fail to do post, and then cause
system hang.
v2:
1. add rwlock for some ioctls, debugfs and file-close function.
2. change to use dqm->is_resetting and dqm_lock
For passthrough device, we do baco reset after 1st vm boot so
if we disable SMU on 1st VM shutdown baco reset will fail for
2nd vm boot.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
For sienna cichlid, add mode1 reset path for sGPU.
And fix some corner cases about mode1 mode reuse.
v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 +++---
>From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.
v2: add mode1 reset dpm interface
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 20
Default value is auto, doesn't change
original reset method logic.
v2: change to use parameter reset_method
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
On Fri, Jul 10, 2020 at 3:48 PM Jason Gunthorpe wrote:
>
> On Fri, Jul 10, 2020 at 03:01:10PM +0200, Christian König wrote:
> > Am 10.07.20 um 14:54 schrieb Jason Gunthorpe:
> > > On Fri, Jul 10, 2020 at 02:48:16PM +0200, Christian König wrote:
> > > > Am 10.07.20 um 14:43 schrieb Jason
On 2020-07-10 9:58 a.m., Alex Deucher wrote:
Prevents a warning in the MST create connector case.
v2: create global fake encoders rather per connector fake encoders
to avoid running out of encoder indices.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1108
Fixes: c6385e503aeaf9
Prevents a warning in the MST create connector case.
v2: create global fake encoders rather per connector fake encoders
to avoid running out of encoder indices.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1108
Fixes: c6385e503aeaf9 ("drm/amdgpu: drop legacy drm load and unload
Am 10.07.20 um 14:54 schrieb Jason Gunthorpe:
On Fri, Jul 10, 2020 at 02:48:16PM +0200, Christian König wrote:
Am 10.07.20 um 14:43 schrieb Jason Gunthorpe:
On Thu, Jul 09, 2020 at 10:09:11AM +0200, Daniel Vetter wrote:
Hi Jason,
Below the paragraph I've added after our discussions around
Hi Dennis,
looks like a possible solution to me, but it would be better if Andrey
could take a look as well.
Christian.
Am 08.07.20 um 09:48 schrieb Dennis Li:
During GPU reset, driver should hold on all external access to
GPU, otherwise psp will randomly fail to do post, and then cause
Am 10.07.20 um 14:43 schrieb Jason Gunthorpe:
On Thu, Jul 09, 2020 at 10:09:11AM +0200, Daniel Vetter wrote:
Hi Jason,
Below the paragraph I've added after our discussions around dma-fences
outside of drivers/gpu. Good enough for an ack on this, or want something
changed?
Thanks, Daniel
+ *
Op 09-07-2020 om 14:33 schreef Daniel Vetter:
> Comes up every few years, gets somewhat tedious to discuss, let's
> write this down once and for all.
>
> What I'm not sure about is whether the text should be more explicit in
> flat out mandating the amdkfd eviction fences for long running compute
[AMD Official Use Only - Internal Distribution Only]
Hi, Paul,
I used our internal tool to make GPU hang and do stress test. In kernel,
when GPU hang, driver has multi-paths to enter amdgpu_device_gpu_recover, the
atomic adev->in_gpu_reset is used to avoid re-entering GPU recovery.
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: chen gong
Sent: Friday, July 10, 2020 4:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Gong, Curry
Subject: [PATCH] drm/amdgpu/powerplay: Target power profile mode should be the
[AMD Public Use]
Got it, Thanks Hawking!
Brs
Wenhui
-Original Message-
From: Zhang, Hawking
Sent: Friday, July 10, 2020 4:07 PM
To: Sheng, Wenhui ; amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: RE: [PATCH 2/4] drm/amdgpu: add psp mode1 reset mode
[AMD Public Use]
Hi @Sheng,
A small mistake
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index f286c1e..ae87c46 100644
---
[AMD Public Use]
Hi @Sheng, Wenhui,
Regarding the following corner cases that need to differentiate legacy mode 1
and new mode 1
1). Emergency start
Create a new function in amdgpu_ras.c, called amdgpu_ras_emergency_start, where
only execute the emergency start for the following configuration
Am 10.07.20 um 07:44 schrieb Jack Xiao:
During preemption test for gfx10, it uses kiq to trigger
gfx preemption, which would result in race condition
with flushing TLB for kiq.
Signed-off-by: Jack Xiao
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 -
[AMD Public Use]
Ok I will refine it.
Brs
Wenhui
-Original Message-
From: Zhang, Hawking
Sent: Friday, July 10, 2020 2:51 PM
To: Zhang, Hawking ; Sheng, Wenhui
; amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: RE: [PATCH 1/4] drm/amd/powerplay: add SMU mode1 reset
[AMD Public
[AMD Public Use]
Hi @Zhang, Hawking
I tried to hide mp0/mp1 mode1 reset under AMD_RESET_METHOD_MODE1, while it
seems that we need to tackle the difference in function
amdgpu_device_gpu_recover, like following change in 3rd patch:
@@ -4275,16 +4277,18 @@ int amdgpu_device_gpu_recover(struct
[AMD Public Use]
BTW, we'd better make the 500ms setting to be a MACRO. We haven't passed the
stress test so might need to extend the waiting in near future.
+ ret = smu_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
+ if (!ret)
+ msleep(500);
Regards,
Hawking
[AMD Public Use]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Xiao, Jack
Sent: Friday, July 10, 2020 13:45
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking
Cc: Xiao, Jack
Subject: [PATCH 2/2] drm/amdgpu: fix preemption unit
[AMD Public Use]
We shall consider add smu mode 1 reset interface in amdgpu_dpm.c, where we have
amdgpu_dpm_mode2_reset and amdgpu_dpm_baco_reset already.
So totally three interfaces there
amdgpu_dpm_baco_reset
amdgpu_dpm_mode2_reset
amdgpu_dpm_mode1_reset
Does it make sense to you? Thoughts?
[AMD Public Use]
How about we expose the reset_method as a new amdgpu module parameter?
Regards,
Hawking
-Original Message-
From: Sheng, Wenhui
Sent: Friday, July 10, 2020 13:46
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Sheng, Wenhui
; Gao, Likun
Subject: [PATCH 4/4]
[AMD Public Use]
Hi @Sheng, Wenhui,
I'm thinking of hiding the MP0/MP1 mode 1 reset under AMD_RESET_METHOD_MODE1.
the callback function reset is per ASIC function, where nv_asic_reset and
soc15_aisc_reset serve for NV series and pre-NV series respectively.
The new mode 1 reset will be used
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