Re: [PATCH 01/11] drm/ttm: add ttm_bo_pin()/ttm_bo_unpin() v2

[Huang Rui]

On Tue, Sep 22, 2020 at 09:31:58PM +0800, Christian König wrote:
> As an alternative to the placement flag add a
> pin count to the ttm buffer object.
> 
> v2: add dma_resv_assert_help() calls
> 
> Signed-off-by: Christian König 

Series look good for me as well.

Reviewed-by: Huang Rui 

Only one comment:

We can modify the TOPDOWN offset as 21 since the NO_EVICT is removed.

 #define TTM_PL_FLAG_UNCACHED(1 << 17)
 #define TTM_PL_FLAG_WC  (1 << 18)
 #define TTM_PL_FLAG_CONTIGUOUS  (1 << 19)
-#define TTM_PL_FLAG_NO_EVICT(1 << 21)
 #define TTM_PL_FLAG_TOPDOWN (1 << 22)

Thanks,
Ray

> ---
>  drivers/gpu/drm/ttm/ttm_bo.c  |  9 ++---
>  drivers/gpu/drm/ttm/ttm_bo_util.c |  2 +-
>  include/drm/ttm/ttm_bo_api.h  | 26 ++
>  3 files changed, 33 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> index 70b3bee27850..b82b49d43942 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -115,7 +115,7 @@ static void ttm_bo_add_mem_to_lru(struct 
> ttm_buffer_object *bo,
>   struct ttm_bo_device *bdev = bo->bdev;
>   struct ttm_resource_manager *man;
>  
> - if (!list_empty(>lru))
> + if (!list_empty(>lru) || bo->pin_count)
>   return;
>  
>   if (mem->placement & TTM_PL_FLAG_NO_EVICT)
> @@ -165,7 +165,8 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
>   ttm_bo_del_from_lru(bo);
>   ttm_bo_add_mem_to_lru(bo, >mem);
>  
> - if (bulk && !(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
> + if (bulk && !(bo->mem.placement & TTM_PL_FLAG_NO_EVICT) &&
> + !bo->pin_count) {
>   switch (bo->mem.mem_type) {
>   case TTM_PL_TT:
>   ttm_bo_bulk_move_set_pos(>tt[bo->priority], bo);
> @@ -544,8 +545,9 @@ static void ttm_bo_release(struct kref *kref)
>* shrinkers, now that they are queued for
>* destruction.
>*/
> - if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) {
> + if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT || bo->pin_count) {
>   bo->mem.placement &= ~TTM_PL_FLAG_NO_EVICT;
> + bo->pin_count = 0;
>   ttm_bo_del_from_lru(bo);
>   ttm_bo_add_mem_to_lru(bo, >mem);
>   }
> @@ -1172,6 +1174,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
>   bo->moving = NULL;
>   bo->mem.placement = TTM_PL_FLAG_CACHED;
>   bo->acc_size = acc_size;
> + bo->pin_count = 0;
>   bo->sg = sg;
>   if (resv) {
>   bo->base.resv = resv;
> diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
> b/drivers/gpu/drm/ttm/ttm_bo_util.c
> index fb2a25f8408f..1968df9743fc 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
> @@ -352,7 +352,6 @@ static int ttm_buffer_object_transfer(struct 
> ttm_buffer_object *bo,
>   return -ENOMEM;
>  
>   fbo->base = *bo;
> - fbo->base.mem.placement |= TTM_PL_FLAG_NO_EVICT;
>  
>   ttm_bo_get(bo);
>   fbo->bo = bo;
> @@ -372,6 +371,7 @@ static int ttm_buffer_object_transfer(struct 
> ttm_buffer_object *bo,
>   kref_init(>base.kref);
>   fbo->base.destroy = _transfered_destroy;
>   fbo->base.acc_size = 0;
> + fbo->base.pin_count = 1;
>   if (bo->type != ttm_bo_type_sg)
>   fbo->base.base.resv = >base.base._resv;
>  
> diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
> index 0f7cd21d6d74..33aca60870e2 100644
> --- a/include/drm/ttm/ttm_bo_api.h
> +++ b/include/drm/ttm/ttm_bo_api.h
> @@ -157,6 +157,7 @@ struct ttm_buffer_object {
>  
>   struct dma_fence *moving;
>   unsigned priority;
> + unsigned pin_count;
>  
>   /**
>* Special members that are protected by the reserve lock
> @@ -606,6 +607,31 @@ static inline bool 
> ttm_bo_uses_embedded_gem_object(struct ttm_buffer_object *bo)
>   return bo->base.dev != NULL;
>  }
>  
> +/**
> + * ttm_bo_pin - Pin the buffer object.
> + * @bo: The buffer object to pin
> + *
> + * Make sure the buffer is not evicted any more during memory pressure.
> + */
> +static inline void ttm_bo_pin(struct ttm_buffer_object *bo)
> +{
> + dma_resv_assert_held(bo->base.resv);
> + ++bo->pin_count;
> +}
> +
> +/**
> + * ttm_bo_unpin - Unpin the buffer object.
> + * @bo: The buffer object to unpin
> + *
> + * Allows the buffer object to be evicted again during memory pressure.
> + */
> +static inline void ttm_bo_unpin(struct ttm_buffer_object *bo)
> +{
> + dma_resv_assert_held(bo->base.resv);
> + WARN_ON_ONCE(!bo->pin_count);
> + --bo->pin_count;
> +}
> +
>  int ttm_mem_evict_first(struct ttm_bo_device *bdev,
>   struct ttm_resource_manager *man,
>   const struct ttm_place *place,
> -- 
> 2.17.1
> 
___
amd-gfx 

RE: [PATCH] drm/amdgpu: remove gpu_info fw support for sienna_cichlid etc.

[Gao, Likun]

[AMD Public Use]

Patch is Reviewed-by: Likun Gao 

Regards,
Likun

-Original Message-
From: Jiansong Chen  
Sent: Wednesday, September 23, 2020 12:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Gao, Likun ; Chen, 
Jiansong (Simon) 
Subject: [PATCH] drm/amdgpu: remove gpu_info fw support for sienna_cichlid etc.

Remove gpu_info fw support for sienna_cichlid etc., since the information can 
be retrieved from discovery binary.

Signed-off-by: Jiansong Chen 
Change-Id: I4cb42aae5d680f28209122bb37962a2291ef785f
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c2eb46e9b71..a174431268b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,8 +80,6 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
-MODULE_FIRMWARE("amdgpu/sienna_cichlid_gpu_info.bin");
-MODULE_FIRMWARE("amdgpu/navy_flounder_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS   2000
 
@@ -1669,6 +1667,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_VEGA20:
+   case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
default:
return 0;
case CHIP_VEGA10:
@@ -1700,12 +1700,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
case CHIP_NAVI12:
chip_name = "navi12";
break;
-   case CHIP_SIENNA_CICHLID:
-   chip_name = "sienna_cichlid";
-   break;
-   case CHIP_NAVY_FLOUNDER:
-   chip_name = "navy_flounder";
-   break;
}
 
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
--
2.25.1
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[PATCH] drm/amdgpu: remove gpu_info fw support for sienna_cichlid etc.

[Jiansong Chen]

Remove gpu_info fw support for sienna_cichlid etc., since the
information can be retrieved from discovery binary.

Signed-off-by: Jiansong Chen 
Change-Id: I4cb42aae5d680f28209122bb37962a2291ef785f
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c2eb46e9b71..a174431268b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,8 +80,6 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
-MODULE_FIRMWARE("amdgpu/sienna_cichlid_gpu_info.bin");
-MODULE_FIRMWARE("amdgpu/navy_flounder_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS   2000
 
@@ -1669,6 +1667,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_VEGA20:
+   case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
default:
return 0;
case CHIP_VEGA10:
@@ -1700,12 +1700,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
case CHIP_NAVI12:
chip_name = "navi12";
break;
-   case CHIP_SIENNA_CICHLID:
-   chip_name = "sienna_cichlid";
-   break;
-   case CHIP_NAVY_FLOUNDER:
-   chip_name = "navy_flounder";
-   break;
}
 
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
-- 
2.25.1

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Re: [PATCH 01/11] drm/ttm: add ttm_bo_pin()/ttm_bo_unpin() v2

[Dave Airlie]

On Tue, 22 Sep 2020 at 23:32, Christian König
 wrote:
>
> As an alternative to the placement flag add a
> pin count to the ttm buffer object.

These all look good to me, nice cleanup.

For the series:
Reviewed-by: Dave Airlie 
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dcn20_validate_bandwidth warnings.

[Bram Stolk]

My system log is full of warnings about dcn20_validate_bandwidth (see
below.)

This is with RX 5500 XT device running amd gpupro driver. 20.30-1109583
amdgpu-dkms 1:5.6.5.24-1109583

This seems to coincide with a screen full of pixel noise, and seems
triggered when going in, or out of a sleep/idle mode?

[184701.291613] [ cut here ]
[184701.291740] WARNING: CPU: 12 PID: 1567 at
/var/lib/dkms/amdgpu/5.6.5.24-1109583/build/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3250
dcn20_validate_bandwidth_fp+0x8a/0xd0 [amdgpu]
[184701.291741] Modules linked in: AMDPowerProfiler(OE) btrfs xor
zstd_compress raid6_pq ufs qnx4 hfsplus hfs minix ntfs msdos jfs xfs
libcrc32c cpuid netlink_diag intel_rapl_msr intel_rapl_common
isst_if_common skx_edac nfit x86_pkg_temp_thermal intel_powerclamp
ipmi_ssif snd_hda_codec_hdmi binfmt_misc uas usb_storage coretemp
snd_hda_intel snd_intel_dspcfg kvm_intel snd_hda_codec kvm snd_hda_core
amdgpu(OE) nls_iso8859_1 snd_hwdep snd_pcm amd_iommu_v2 snd_seq_midi
amd_sched(OE) snd_seq_midi_event amdttm(OE) snd_rawmidi crct10dif_pclmul
snd_seq ghash_clmulni_intel aesni_intel snd_seq_device crypto_simd
snd_timer amdkcl(OE) cryptd glue_helper drm_kms_helper snd fb_sys_fops rapl
mei_me syscopyarea xpad ipmi_si sysfillrect intel_cstate input_leds joydev
ff_memless sysimgblt soundcore mei ioatdma ipmi_devintf ipmi_msghandler
mac_hid acpi_tad sch_fq_codel parport_pc ppdev lp parport drm ip_tables
x_tables autofs4 hid_generic usbhid hid crc32_pclmul igb nvme nvme_core
i2c_algo_bit i2c_i801 dca wmi
[184701.291776]  [last unloaded: AMDPowerProfiler]
[184701.291780] CPU: 12 PID: 1567 Comm: Xorg Tainted: GW  OE
5.4.0-47-generic #51-Ubuntu
[184701.291781] Hardware name: Supermicro Super Server/X11SRM-F, BIOS 2.2
09/03/2020
[184701.291888] RIP: 0010:dcn20_validate_bandwidth_fp+0x8a/0xd0 [amdgpu]
[184701.291890] Code: 24 08 1f 00 00 75 29 31 d2 4c 89 e6 4c 89 ef f2 41 0f
11 84 24 50 26 00 00 e8 f2 f5 ff ff 89 c2 41 22 94 24 08 1f 00 00 75 33
<0f> 0b eb 02 75 cd f2 0f 10 55 e8 f2 41 0f 11 94 24 50 26 00 00 48
[184701.291891] RSP: 0018:b46b4298fa20 EFLAGS: 00010246
[184701.291893] RAX: 0001 RBX:  RCX:
000ea272
[184701.291893] RDX:  RSI: af2e92a2240f908b RDI:
0002f1a0
[184701.291894] RBP: b46b4298fa38 R08: 0005 R09:

[184701.291895] R10: 0004 R11: 00010001 R12:
98678796
[184701.291896] R13: 98699274 R14: 986917709830 R15:
98678796
[184701.291897] FS:  7f9fd16f5a80() GS:98699ff0()
knlGS:
[184701.291898] CS:  0010 DS:  ES:  CR0: 80050033
[184701.291899] CR2: 7fb240ca20c0 CR3: 000806c6c004 CR4:
003606e0
[184701.291900] DR0:  DR1:  DR2:

[184701.291901] DR3:  DR6: fffe0ff0 DR7:
0400
[184701.291901] Call Trace:
[184701.292005]  dcn20_validate_bandwidth+0x29/0x40 [amdgpu]
[184701.292099]  dc_validate_global_state+0x260/0x2d0 [amdgpu]
[184701.292196]  amdgpu_dm_atomic_check+0xcd3/0xd10 [amdgpu]
[184701.292215]  drm_atomic_check_only+0x2b1/0x450 [drm]
[184701.292227]  drm_atomic_commit+0x18/0x50 [drm]
[184701.292239]  drm_atomic_connector_commit_dpms+0xdf/0x100 [drm]
[184701.292252]  drm_mode_obj_set_property_ioctl+0x156/0x2a0 [drm]
[184701.292265]  ? drm_connector_set_obj_prop+0x90/0x90 [drm]
[184701.292277]  drm_connector_property_set_ioctl+0x3b/0x60 [drm]
[184701.292286]  drm_ioctl_kernel+0xae/0xf0 [drm]
[184701.292295]  drm_ioctl+0x234/0x3d0 [drm]
[184701.292306]  ? drm_connector_set_obj_prop+0x90/0x90 [drm]
[184701.292310]  ? ___sys_recvmsg+0x88/0xc0
[184701.292354]  amdgpu_drm_ioctl+0x4e/0x80 [amdgpu]
[184701.292356]  do_vfs_ioctl+0x407/0x670
[184701.292359]  ? fput+0x13/0x15
[184701.292361]  ? __sys_recvmsg+0x88/0xa0
[184701.292363]  ksys_ioctl+0x67/0x90
[184701.292364]  __x64_sys_ioctl+0x1a/0x20
[184701.292367]  do_syscall_64+0x57/0x190
[184701.292370]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[184701.292372] RIP: 0033:0x7f9fd1a5537b
[184701.292373] Code: 0f 1e fa 48 8b 05 15 3b 0d 00 64 c7 00 26 00 00 00 48
c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05
<48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d e5 3a 0d 00 f7 d8 64 89 01 48
[184701.292374] RSP: 002b:7ffc96832f98 EFLAGS: 0246 ORIG_RAX:
0010
[184701.292376] RAX: ffda RBX: 7ffc96832fd0 RCX:
7f9fd1a5537b
[184701.292376] RDX: 7ffc96832fd0 RSI: c01064ab RDI:
000d
[184701.292377] RBP: c01064ab R08: 7ffc96895090 R09:
7ffc96832eb8
[184701.292378] R10: 7ffc96832eb0 R11: 0246 R12:
557656b2fb40
[184701.292379] R13: 000d R14:  R15:
557656a46980
[184701.292381] ---[ end trace 91d0e0d7876bea26 ]---


-- 
Owner/Director of Game Studio Abraham Stolk Inc.
Vancouver BC, Canada
b.st...@gmail.com

Re: [PATCH] drm/amdgpu/dc: Pixel encoding DRM property and module parameter

[James Ettle]

On 22/09/2020 21:33, Alex Deucher wrote:
>> +/**
>> + * DOC: pixel_encoding (string)
>> + * Specify the initial pixel encoding used by a connector.
>> + */
>> +static char amdgpu_pixel_encoding[MAX_INPUT];
>> +MODULE_PARM_DESC(pixel_encoding, "Override pixel encoding");
>> +module_param_string(pixel_encoding, amdgpu_pixel_encoding, 
>> sizeof(amdgpu_pixel_encoding), 0444);
> 
> You can drop this part.  We don't need a module parameter if we have a
> kms property.
> 
> Alex

OK, but is there then an alternative means of setting the pixel encoding to be 
used immediately on boot or when amdgpu loads? Also are there user tools other 
than xrandr to change a KMS property, for Wayland and console users? 

-James

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Re: [PATCH] drm/amdgpu/dc: Pixel encoding DRM property and module parameter

[Alex Deucher]

On Tue, Sep 22, 2020 at 3:34 PM James Ettle  wrote:
>
> Exposes the pixel encoding as the DRM property "pixel encoding"
> and the module parameter pixel_encoding.
>
> The DRM property may take values "auto" (current behaviour
> when a display is plugged in), "rgb" for RGB, or "ycbcr444" for
> YCbCr 4:4:4.
>
> The module parameter may only be set on boot and is of the format
> [connector-name:]encoding[,...] where encoding is one of the
> same values as are valid for the DRM property.
>
> https://gitlab.freedesktop.org/drm/amd/-/issues/476
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  33 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.h   |   4 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |   8 +
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 247 --
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
>  drivers/gpu/drm/amd/display/dc/core/dc.c  |  12 +-
>  drivers/gpu/drm/amd/display/dc/dc_stream.h|   2 +
>  7 files changed, 289 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index d76172965199..37748f35c52b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -614,6 +614,31 @@ static const struct drm_prop_enum_list 
> amdgpu_dither_enum_list[] =
> { AMDGPU_FMT_DITHER_ENABLE, "on" },
>  };
>
> +static const struct drm_prop_enum_list amdgpu_user_pixenc_list[] =
> +{  { AMDGPU_USER_PIXENC_AUTO, "auto" },
> +   { AMDGPU_USER_PIXENC_RGB, "rgb" },
> +   { AMDGPU_USER_PIXENC_YCBCR444, "ycbcr444" },
> +};
> +
> +bool amdgpu_user_pixenc_from_name(
> +   enum amdgpu_user_pixenc *user_pixenc,
> +   const char *pixenc_name)
> +{
> +   /* user_pixenc only modified if name found */
> +   bool found = false;
> +   if (pixenc_name && (*pixenc_name != '\0')) {
> +   const int sz = ARRAY_SIZE(amdgpu_user_pixenc_list);
> +   int i;
> +   for (i = 0; !found && i < sz; ++i) {
> +   if (strcmp(pixenc_name, 
> amdgpu_user_pixenc_list[i].name) == 0) {
> +   *user_pixenc = 
> amdgpu_user_pixenc_list[i].type;
> +   found = true;
> +   }
> +   }
> +   }
> +   return found;
> +}
> +
>  int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
>  {
> int sz;
> @@ -666,6 +691,14 @@ int amdgpu_display_modeset_create_props(struct 
> amdgpu_device *adev)
> "abm level", 0, 4);
> if (!adev->mode_info.abm_level_property)
> return -ENOMEM;
> +
> +   sz = ARRAY_SIZE(amdgpu_user_pixenc_list);
> +   adev->mode_info.pixel_encoding_property =
> +   drm_property_create_enum(adev->ddev, 0,
> +   "pixel encoding",
> +   amdgpu_user_pixenc_list, sz);
> +   if (!adev->mode_info.pixel_encoding_property)
> +   return -ENOMEM;
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
> index 3620b24785e1..72f82e3f4e32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
> @@ -45,4 +45,8 @@ amdgpu_display_user_framebuffer_create(struct drm_device 
> *dev,
>struct drm_file *file_priv,
>const struct drm_mode_fb_cmd2 
> *mode_cmd);
>
> +bool amdgpu_user_pixenc_from_name(
> +   enum amdgpu_user_pixenc *user_pixenc,
> +   const char *pixenc_name);
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> index 37ba07e2feb5..3c21ecf3d259 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> @@ -123,6 +123,12 @@ enum amdgpu_flip_status {
> AMDGPU_FLIP_SUBMITTED
>  };
>
> +enum amdgpu_user_pixenc {
> +   AMDGPU_USER_PIXENC_AUTO,
> +   AMDGPU_USER_PIXENC_RGB,
> +   AMDGPU_USER_PIXENC_YCBCR444
> +};
> +
>  #define AMDGPU_MAX_I2C_BUS 16
>
>  /* amdgpu gpio-based i2c
> @@ -333,6 +339,8 @@ struct amdgpu_mode_info {
> struct drm_property *dither_property;
> /* Adaptive Backlight Modulation (power feature) */
> struct drm_property *abm_level_property;
> +   /* User HDMI pixel encoding override */
> +   struct drm_property *pixel_encoding_property;
> /* hardcoded DFP edid from BIOS */
> struct edid *bios_hardcoded_edid;
> int bios_hardcoded_edid_size;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index b51c527a3f0d..8901271d1902 100644
> --- 

[PATCH] drm/amdgpu/dc: Pixel encoding DRM property and module parameter

[James Ettle]

Exposes the pixel encoding as the DRM property "pixel encoding"
and the module parameter pixel_encoding.

The DRM property may take values "auto" (current behaviour
when a display is plugged in), "rgb" for RGB, or "ycbcr444" for
YCbCr 4:4:4.

The module parameter may only be set on boot and is of the format
[connector-name:]encoding[,...] where encoding is one of the
same values as are valid for the DRM property.

https://gitlab.freedesktop.org/drm/amd/-/issues/476
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  33 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |   8 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 247 --
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  12 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   2 +
 7 files changed, 289 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index d76172965199..37748f35c52b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -614,6 +614,31 @@ static const struct drm_prop_enum_list 
amdgpu_dither_enum_list[] =
{ AMDGPU_FMT_DITHER_ENABLE, "on" },
 };
 
+static const struct drm_prop_enum_list amdgpu_user_pixenc_list[] =
+{  { AMDGPU_USER_PIXENC_AUTO, "auto" },
+   { AMDGPU_USER_PIXENC_RGB, "rgb" },
+   { AMDGPU_USER_PIXENC_YCBCR444, "ycbcr444" },
+};
+
+bool amdgpu_user_pixenc_from_name(
+   enum amdgpu_user_pixenc *user_pixenc,
+   const char *pixenc_name)
+{
+   /* user_pixenc only modified if name found */
+   bool found = false;
+   if (pixenc_name && (*pixenc_name != '\0')) {
+   const int sz = ARRAY_SIZE(amdgpu_user_pixenc_list);
+   int i;
+   for (i = 0; !found && i < sz; ++i) {
+   if (strcmp(pixenc_name, 
amdgpu_user_pixenc_list[i].name) == 0) {
+   *user_pixenc = amdgpu_user_pixenc_list[i].type;
+   found = true;
+   }
+   }
+   }
+   return found;
+}
+
 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
 {
int sz;
@@ -666,6 +691,14 @@ int amdgpu_display_modeset_create_props(struct 
amdgpu_device *adev)
"abm level", 0, 4);
if (!adev->mode_info.abm_level_property)
return -ENOMEM;
+
+   sz = ARRAY_SIZE(amdgpu_user_pixenc_list);
+   adev->mode_info.pixel_encoding_property =
+   drm_property_create_enum(adev->ddev, 0,
+   "pixel encoding",
+   amdgpu_user_pixenc_list, sz);
+   if (!adev->mode_info.pixel_encoding_property)
+   return -ENOMEM;
}
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
index 3620b24785e1..72f82e3f4e32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
@@ -45,4 +45,8 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
   struct drm_file *file_priv,
   const struct drm_mode_fb_cmd2 *mode_cmd);
 
+bool amdgpu_user_pixenc_from_name(
+   enum amdgpu_user_pixenc *user_pixenc,
+   const char *pixenc_name);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 37ba07e2feb5..3c21ecf3d259 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -123,6 +123,12 @@ enum amdgpu_flip_status {
AMDGPU_FLIP_SUBMITTED
 };
 
+enum amdgpu_user_pixenc {
+   AMDGPU_USER_PIXENC_AUTO,
+   AMDGPU_USER_PIXENC_RGB,
+   AMDGPU_USER_PIXENC_YCBCR444
+};
+
 #define AMDGPU_MAX_I2C_BUS 16
 
 /* amdgpu gpio-based i2c
@@ -333,6 +339,8 @@ struct amdgpu_mode_info {
struct drm_property *dither_property;
/* Adaptive Backlight Modulation (power feature) */
struct drm_property *abm_level_property;
+   /* User HDMI pixel encoding override */
+   struct drm_property *pixel_encoding_property;
/* hardcoded DFP edid from BIOS */
struct edid *bios_hardcoded_edid;
int bios_hardcoded_edid_size;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b51c527a3f0d..8901271d1902 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -158,7 +158,6 @@ static int amdgpu_dm_connector_get_modes(struct 
drm_connector *connector);
 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
   struct 

Re: [PATCH] drm/amdgpu/display: fix CFLAGS setup for DCN30

[Nirmoy]

Acked-by: Nirmoy Das 

On 9/22/20 5:36 PM, Alex Deucher wrote:

Properly handle clang and older versions of gcc.

Fixes: e77165bf7b02a3 ("drm/amd/display: Add DCN3 blocks to Makefile")
Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 18 --
  1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index 025637a83c3b..bd2a068f9863 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -31,9 +31,21 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o 
dcn30_optc.o \
dcn30_dio_link_encoder.o dcn30_resource.o
  
  
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse -mpreferred-stack-boundary=4

-
+ifdef CONFIG_X86
  CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -maltivec
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_ARM64
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mgeneral-regs-only
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mgeneral-regs-only
+endif
+
  ifdef CONFIG_CC_IS_GCC
  ifeq ($(call cc-ifversion, -lt, 0701, y), y)
  IS_OLD_GCC = 1
@@ -45,8 +57,10 @@ ifdef IS_OLD_GCC
  # GCC < 7.1 cannot compile code using `double` and 
-mpreferred-stack-boundary=3
  # (8B stack alignment).
  CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mpreferred-stack-boundary=4
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mpreferred-stack-boundary=4
  else
  CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -msse2
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -msse2
  endif
  
  AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30))

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[PATCH v2] Add PP_FEATURE_MASK comments

[Ryan Taylor]

Documents PP_FEATURE_MASK enum.
Provides instructions on how to use ppfeaturemasks.

v2: Improved enum definitions. Adds kernel command line
parameters to ppfeaturemask instructions.

Signed-off-by: Ryan Taylor 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/amd_shared.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index e98c84ef206f..7c84d5beb600 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -128,6 +128,34 @@ enum amd_powergating_state {
 #define AMD_PG_SUPPORT_ATHUB   (1 << 16)
 #define AMD_PG_SUPPORT_JPEG(1 << 17)
 
+/**
+* enum PP_FEATURE_MASK - Used to mask power play features.
+*
+* @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
+* @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
+* @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
+* @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
+* @PP_POWER_CONTAINMENT_MASK: Power containment.
+* @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
+* @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
+* @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
+* @PP_ULV_MASK: Ultra low voltage.
+* @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
+* @PP_CLOCK_STRETCH_MASK: Clock stretching.
+* @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
+* @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
+* @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine 
Fabric clock.
+* @PP_OVERDRIVE_MASK: Over- and under-clocking support.
+* @PP_GFXOFF_MASK: Dynamic graphics engine power control.
+* @PP_ACG_MASK: Adaptive clock generator.
+* @PP_STUTTER_MODE: Stutter mode.
+* @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
+*
+* To override these settings on boot, append amdgpu.ppfeaturemask= to
+* the kernel's command line parameters. This is usually done through a system's
+* boot loader (E.g. GRUB). If manually loading the driver, pass
+* ppfeaturemask= as a modprobe parameter.
+*/
 enum PP_FEATURE_MASK {
PP_SCLK_DPM_MASK = 0x1,
PP_MCLK_DPM_MASK = 0x2,
-- 
2.28.0

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Re: [PATCH] gpu/drm/radeon: fix spellint typo in comments

[Alex Deucher]

Applied with subject typo fixed.  Thanks!

Alex

On Tue, Sep 22, 2020 at 10:07 AM Ernst Sjöstrand  wrote:
>
> There is a typo in your patch subject. ;-)
>
> Regards
> //Ernst
>
> Den tis 22 sep. 2020 kl 15:11 skrev Wang Qing :
>>
>> Modify the comment typo: "definately" -> "definitely".
>>
>> Signed-off-by: Wang Qing 
>> ---
>>  drivers/gpu/drm/radeon/radeon_vm.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
>> b/drivers/gpu/drm/radeon/radeon_vm.c
>> index f60fae0..3d6e2cd
>> --- a/drivers/gpu/drm/radeon/radeon_vm.c
>> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
>> @@ -188,7 +188,7 @@ struct radeon_fence *radeon_vm_grab_id(struct 
>> radeon_device *rdev,
>> vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
>> return NULL;
>>
>> -   /* we definately need to flush */
>> +   /* we definitely need to flush */
>> vm_id->pd_gpu_addr = ~0ll;
>>
>> /* skip over VMID 0, since it is the system VM */
>> --
>> 2.7.4
>>
>> ___
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
> ___
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Re: [PATCH v2] drm/amd/display: optimize code runtime a bit

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Sep 22, 2020 at 3:52 AM Bernard Zhao  wrote:
>
> In the function dal_ddc_service_query_ddc_data,
> get rid of dal_ddc_i2c_payloads_destroy, call
> dal_vector_destruct() directly.
> This change is to make the code run a bit fast.
>
> Signed-off-by: Bernard Zhao 
> Changes since V1:
> *get rid of dal_ddc_i2c_payloads_destroy, call
> dal_vector_destruct() directly.
>
> Link for V1:
> *https://lore.kernel.org/patchwork/patch/1309014/
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 10 +-
>  1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> index b984eecca58b..dec12de37642 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> @@ -148,14 +148,6 @@ static uint32_t dal_ddc_i2c_payloads_get_count(struct 
> i2c_payloads *p)
> return p->payloads.count;
>  }
>
> -static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads *p)
> -{
> -   if (!p)
> -   return;
> -
> -   dal_vector_destruct(>payloads);
> -}
> -
>  #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
>
>  void dal_ddc_i2c_payloads_add(
> @@ -582,7 +574,7 @@ bool dal_ddc_service_query_ddc_data(
> ddc->link,
> );
>
> -   dal_ddc_i2c_payloads_destroy();
> +   dal_vector_destruct();
> }
>
> return success;
> --
> 2.28.0
>
> ___
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Re: [PATCH] drm/amd:fix typoes in comments

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Sep 22, 2020 at 9:11 AM Bernard Zhao  wrote:
>
> Change the comment typo: "programm" -> "program".
>
> Signed-off-by: Bernard Zhao 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c  | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c  | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 2 +-
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c  | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  | 4 ++--
>  8 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 770025a5e500..7c46937c1c0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -98,7 +98,7 @@ struct amdgpu_bo_list_entry;
>  #define AMDGPU_PTE_MTYPE_NV10(a)   ((uint64_t)(a) << 48)
>  #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
>
> -/* How to programm VM fault handling */
> +/* How to program VM fault handling */
>  #define AMDGPU_VM_FAULT_STOP_NEVER 0
>  #define AMDGPU_VM_FAULT_STOP_FIRST 1
>  #define AMDGPU_VM_FAULT_STOP_ALWAYS2
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 3cafba726587..b0c0c438fc93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -348,7 +348,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
> /* Set the write pointer delay */
> WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
>
> -   /* programm the 4GB memory segment for rptr and ring buffer */
> +   /* program the 4GB memory segment for rptr and ring buffer */
> WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
>(0x7 << 16) | (0x1 << 31));
>
> @@ -541,7 +541,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
> uint64_t addr;
> uint32_t size;
>
> -   /* programm the VCPU memory controller bits 0-27 */
> +   /* program the VCPU memory controller bits 0-27 */
> addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
> size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
> WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index a566ff926e90..6e57001f6d0a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -253,7 +253,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
> uint64_t offset;
> uint32_t size;
>
> -   /* programm memory controller bits 0-27 */
> +   /* program memory controller bits 0-27 */
> WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> lower_32_bits(adev->uvd.inst->gpu_addr));
> WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> @@ -404,7 +404,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
> /* set the wb address */
> WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
>
> -   /* programm the RB_BASE for ring buffer */
> +   /* program the RB_BASE for ring buffer */
> WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
> lower_32_bits(ring->gpu_addr));
> WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 0a880bc101b8..d2d90fe5c6f8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -583,7 +583,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
> uint64_t offset;
> uint32_t size;
>
> -   /* programm memory controller bits 0-27 */
> +   /* program memory controller bits 0-27 */
> WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> lower_32_bits(adev->uvd.inst->gpu_addr));
> WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> @@ -825,7 +825,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
> /* set the wb address */
> WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
>
> -   /* programm the RB_BASE for ring buffer */
> +   /* program the RB_BASE for ring buffer */
> WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
> lower_32_bits(ring->gpu_addr));
> WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index e07e3fae99b5..b44c8677ce8d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1073,7 +1073,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
> WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
> 

Re: [PATCH] drm/radeon:fix typoes in comments

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Sep 22, 2020 at 9:11 AM Bernard Zhao  wrote:
>
> Change the comment typo: "programm" -> "program".
>
> Signed-off-by: Bernard Zhao 
> ---
>  drivers/gpu/drm/radeon/uvd_v1_0.c | 4 ++--
>  drivers/gpu/drm/radeon/uvd_v2_2.c | 2 +-
>  drivers/gpu/drm/radeon/uvd_v4_2.c | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c 
> b/drivers/gpu/drm/radeon/uvd_v1_0.c
> index 800721153d51..58557c2263a7 100644
> --- a/drivers/gpu/drm/radeon/uvd_v1_0.c
> +++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
> @@ -117,7 +117,7 @@ int uvd_v1_0_resume(struct radeon_device *rdev)
> if (r)
> return r;
>
> -   /* programm the VCPU memory controller bits 0-27 */
> +   /* program the VCPU memory controller bits 0-27 */
> addr = (rdev->uvd.gpu_addr >> 3) + 16;
> size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;
> WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
> @@ -360,7 +360,7 @@ int uvd_v1_0_start(struct radeon_device *rdev)
> /* Set the write pointer delay */
> WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
>
> -   /* programm the 4GB memory segment for rptr and ring buffer */
> +   /* program the 4GB memory segment for rptr and ring buffer */
> WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
>(0x7 << 16) | (0x1 << 31));
>
> diff --git a/drivers/gpu/drm/radeon/uvd_v2_2.c 
> b/drivers/gpu/drm/radeon/uvd_v2_2.c
> index 23b18edda20e..6266167886d9 100644
> --- a/drivers/gpu/drm/radeon/uvd_v2_2.c
> +++ b/drivers/gpu/drm/radeon/uvd_v2_2.c
> @@ -109,7 +109,7 @@ int uvd_v2_2_resume(struct radeon_device *rdev)
> if (r)
> return r;
>
> -   /* programm the VCPU memory controller bits 0-27 */
> +   /* program the VCPU memory controller bits 0-27 */
> addr = rdev->uvd.gpu_addr >> 3;
> size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
> WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
> diff --git a/drivers/gpu/drm/radeon/uvd_v4_2.c 
> b/drivers/gpu/drm/radeon/uvd_v4_2.c
> index dc54fa4aaea8..f9e97fa63674 100644
> --- a/drivers/gpu/drm/radeon/uvd_v4_2.c
> +++ b/drivers/gpu/drm/radeon/uvd_v4_2.c
> @@ -40,7 +40,7 @@ int uvd_v4_2_resume(struct radeon_device *rdev)
> uint64_t addr;
> uint32_t size;
>
> -   /* programm the VCPU memory controller bits 0-27 */
> +   /* program the VCPU memory controller bits 0-27 */
>
> /* skip over the header of the new firmware format */
> if (rdev->uvd.fw_header_present)
> --
> 2.28.0
>
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Re: [PATCH] drm/amd/display: Fix dcn30_optc.o unknown argument with clang

[Alex Deucher]

On Mon, Sep 21, 2020 at 6:12 PM Anthony Benware  wrote:
>
> [Why]
> Clang can't compile dcn30_optc.o with '-mpreferred-stack-boundary=4'
>
> [How]
> use '-mstack-alignment=4' if Clang is CC and '-mpreferred-stack-boundary=4' 
> if CC is not Clang
>
> Signed-off-by: Anthony Benware 

Thanks for the patch.  I just sent a slightly different one to fix
this up properly with clang and older versions of gcc.

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
> index 025637a83c3b..fcded5498393 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
> @@ -31,7 +31,11 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o 
> dcn30_dpp.o dcn30_optc.o \
> dcn30_dio_link_encoder.o dcn30_resource.o
>
>
> +ifdef CONFIG_CC_IS_CLANG
> +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse 
> -mstack-alignment=4
> +else
>  CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse 
> -mpreferred-stack-boundary=4
> +endif
>
>  CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
>  ifdef CONFIG_CC_IS_GCC
> --
> 2.28.0
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[PATCH] drm/amdgpu/display: fix CFLAGS setup for DCN30

[Alex Deucher]

Properly handle clang and older versions of gcc.

Fixes: e77165bf7b02a3 ("drm/amd/display: Add DCN3 blocks to Makefile")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index 025637a83c3b..bd2a068f9863 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -31,9 +31,21 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o 
dcn30_optc.o \
dcn30_dio_link_encoder.o dcn30_resource.o
 
 
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse 
-mpreferred-stack-boundary=4
-
+ifdef CONFIG_X86
 CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -maltivec
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_ARM64
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mgeneral-regs-only
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mgeneral-regs-only
+endif
+
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
@@ -45,8 +57,10 @@ ifdef IS_OLD_GCC
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
 # (8B stack alignment).
 CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mpreferred-stack-boundary=4
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mpreferred-stack-boundary=4
 else
 CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -msse2
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -msse2
 endif
 
 AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30))
-- 
2.25.4

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Re: [PATCH v3] amdgpu: Add initial kernel documentation for the amd_ip_block_type structure

[Alex Deucher]

On Mon, Sep 21, 2020 at 11:55 AM Ryan Taylor  wrote:
>
> From: Ryan Taylor 
>
> Added IP block section to amdgpu.rst.
> Added more documentation to amd_ip_funcs.
> Created documentation for amd_ip_block_type.
>
> v2: Provides a more detailed DOC section on IP blocks.
> v3: Clarifies the IP block list. Adds info on IP block enumeration.
>
> Signed-off-by: Ryan Taylor 
> Reviewed-by: Alex Deucher 

Looks good.  Feel free to commit it.

Thanks!

Alex

> ---
>  Documentation/gpu/amdgpu.rst |  9 +++
>  drivers/gpu/drm/amd/include/amd_shared.h | 87 +---
>  2 files changed, 71 insertions(+), 25 deletions(-)
>
> diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
> index 29ca5f5feb35..57047dcb8d19 100644
> --- a/Documentation/gpu/amdgpu.rst
> +++ b/Documentation/gpu/amdgpu.rst
> @@ -70,6 +70,15 @@ Interrupt Handling
>  .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> :internal:
>
> +IP Blocks
> +--
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
> +   :doc: IP Blocks
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
> +   :identifiers: amd_ip_block_type amd_ip_funcs
> +
>  AMDGPU XGMI Support
>  ===
>
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
> b/drivers/gpu/drm/amd/include/amd_shared.h
> index e98c84ef206f..6b8a40051f41 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -47,6 +47,40 @@ enum amd_apu_flags {
> AMD_APU_IS_RENOIR = 0x0008UL,
>  };
>
> +/**
> +* DOC: IP Blocks
> +*
> +* GPUs are composed of IP (intellectual property) blocks. These
> +* IP blocks provide various functionalities: display, graphics,
> +* video decode, etc. The IP blocks that comprise a particular GPU
> +* are listed in the GPU's respective SoC file. amdgpu_device.c
> +* acquires the list of IP blocks for the GPU in use on initialization.
> +* It can then operate on this list to perform standard driver operations
> +* such as: init, fini, suspend, resume, etc.
> +*
> +*
> +* IP block implementations are named using the following convention:
> +* _v (E.g.: gfx_v6_0).
> +*/
> +
> +/**
> +* enum amd_ip_block_type - Used to classify IP blocks by functionality.
> +*
> +* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
> +* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
> +* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
> +* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
> +* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
> +* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
> +* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
> +* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
> +* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
> +* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
> +* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
> +* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
> +* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
> +* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
> +*/
>  enum amd_ip_block_type {
> AMD_IP_BLOCK_TYPE_COMMON,
> AMD_IP_BLOCK_TYPE_GMC,
> @@ -165,56 +199,59 @@ enum DC_DEBUG_MASK {
>  };
>
>  enum amd_dpm_forced_level;
> +
>  /**
>   * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
> + * @name: Name of IP block
> + * @early_init: sets up early driver state (pre sw_init),
> + *  does not configure hw - Optional
> + * @late_init: sets up late driver/hw state (post hw_init) - Optional
> + * @sw_init: sets up driver state, does not configure hw
> + * @sw_fini: tears down driver state, does not configure hw
> + * @hw_init: sets up the hw state
> + * @hw_fini: tears down the hw state
> + * @late_fini: final cleanup
> + * @suspend: handles IP specific hw/sw changes for suspend
> + * @resume: handles IP specific hw/sw changes for resume
> + * @is_idle: returns current IP block idle status
> + * @wait_for_idle: poll for idle
> + * @check_soft_reset: check soft reset the IP block
> + * @pre_soft_reset: pre soft reset the IP block
> + * @soft_reset: soft reset the IP block
> + * @post_soft_reset: post soft reset the IP block
> + * @set_clockgating_state: enable/disable cg for the IP block
> + * @set_powergating_state: enable/disable pg for the IP block
> + * @get_clockgating_state: get current clockgating status
> + * @enable_umd_pstate: enable UMD powerstate
> + *
> + * These hooks provide an interface for controlling the operational state
> + * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
> + * the driver can make chip-wide state changes by walking this list and
> + * making calls to hooks from each IP block. This list is ordered to ensure
> + * that the driver initializes the IP blocks in a safe sequence.
>   */
>  struct amd_ip_funcs {
> -   /** @name: Name of IP block */
> char *name;
> -   /**
> -* @early_init:
> -*
> -* sets up early driver state (pre sw_init),
> -* does not configure hw - 

Re: [PATCH] drm/amd/display: Simplify condition in try_disable_dsc

[Alex Deucher]

On Tue, Sep 22, 2020 at 3:47 AM Nathan Chancellor
 wrote:
>
> Clang warns:
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c:637:8:
> warning: logical not is only applied to the left hand side of this
> comparison [-Wlogical-not-parentheses]
> && !params[i].clock_force_enable == 
> DSC_CLK_FORCE_DEFAULT) {
>^ ~~
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c:637:8:
> note: add parentheses after the '!' to evaluate the comparison first
> && !params[i].clock_force_enable == 
> DSC_CLK_FORCE_DEFAULT) {
>^
> (
> )
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c:637:8:
> note: add parentheses around left hand side expression to silence this
> warning
> && !params[i].clock_force_enable == 
> DSC_CLK_FORCE_DEFAULT) {
>^
>()
> 1 warning generated.
>
> The expression "!a == 0" can be more simply written as "a", which makes
> it easier to reason about the logic and prevents the warning.
>
> Fixes: 0749ddeb7d6c ("drm/amd/display: Add DSC force disable to dsc_clock_en 
> debugfs entry")
> Link: https://github.com/ClangBuiltLinux/linux/issues/1158
> Signed-off-by: Nathan Chancellor 

@Wentland, Harry or @Leo (Sunpeng) Li  can you provide some guidance
on what the logic is supposed to be here?

Thanks,

Alex

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 9d7333a36fac..0852a24ee392 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -634,7 +634,7 @@ static void try_disable_dsc(struct drm_atomic_state 
> *state,
> for (i = 0; i < count; i++) {
> if (vars[i].dsc_enabled
> && vars[i].bpp_x16 == 
> params[i].bw_range.max_target_bpp_x16
> -   && !params[i].clock_force_enable == 
> DSC_CLK_FORCE_DEFAULT) {
> +   && params[i].clock_force_enable) {
> kbps_increase[i] = params[i].bw_range.stream_kbps - 
> params[i].bw_range.max_kbps;
> tried[i] = false;
> remaining_to_try += 1;
>
> base-commit: 6651cdf3bfeeaeb499db11668313666bf756579a
> --
> 2.28.0
>
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Re: [PATCH] drm/amdgpu: Add uid info to process BO list

[Alex Deucher]

On Tue, Sep 22, 2020 at 10:39 AM Chauhan, Madhav  wrote:
>
> [AMD Public Use]
>
> -Original Message-
> From: Christian König 
> Sent: Tuesday, September 22, 2020 6:25 PM
> To: Chauhan, Madhav ; Koenig, Christian 
> ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Surampalli, Kishore 
> ; Patel, Mihir ; Saleem, 
> Athar ; Sharma, Shashank 
> Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list
>
> Am 22.09.20 um 12:38 schrieb Chauhan, Madhav:
> > [AMD Public Use]
> >
> > -Original Message-
> > From: Koenig, Christian 
> > Sent: Tuesday, September 22, 2020 12:15 PM
> > To: Chauhan, Madhav ;
> > amd-gfx@lists.freedesktop.org
> > Cc: Surampalli, Kishore ; Patel, Mihir
> > ; Sharma, Shashank ;
> > Deucher, Alexander ; Saleem, Athar
> > 
> > Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list
> >
> > Am 21.09.20 um 21:55 schrieb Chauhan, Madhav:
> >> [AMD Public Use]
> >>
> >> -Original Message-
> >> From: Christian König 
> >> Sent: Tuesday, September 22, 2020 12:54 AM
> >> To: Chauhan, Madhav ;
> >> amd-gfx@lists.freedesktop.org
> >> Cc: Surampalli, Kishore ; Patel, Mihir
> >> ; Sharma, Shashank ;
> >> Deucher, Alexander ; Saleem, Athar
> >> 
> >> Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list
> >>
> >> Am 21.09.20 um 21:18 schrieb Madhav Chauhan:
> >>> UID is helpful while doing analysis of BO allocated by a process.
> >> Looks like a bit overkill to me, why not get the uid from the process info?
> >>
> >> Not sure if I got your point , but used the similar method
> >> implemented at drm level inside drm_debugfs.c. Thanks
> > Good argument, but I'm not sure if we should duplicate that here. What do 
> > you need this for?
> >
> > Thanks, We need details of BOs allocated by a process and associated
> > UID so that we can do memory perf analysis using some scripts To find the 
> > top consumer of GPU memory and see if those application can be optimized.
> >
> > Clients information at DRM level doesn’t print list of BO per process
> > and since that is handled by amdgpu driver specific Functions.  So all
> > the BO list information at one place is really useful and needed by our 
> > customers as various other vendors Already provide this.
>
> Well that is exactly the explanation I didn't want to hear :(
>
> See both the drm client list as well as the amdgpu GEM info are only debugfs 
> files and only intended for providing some information for debugging and are 
> not 100% reliable for the use case you have here.
>
> The first problem is that on modern installations the file descriptor is 
> often opened by the X server instead of the application.
>
> So for example you end up with:
> > pid 1382 command Xorg:
> > 0x0001:  2097152 byte VRAM @ 0x002a00
> > 0x0002: 4096 byte  GTT @ 0x0006c7 
> > 0x0090:   266240 byte VRAM @ 0x05e800
> > 0x0091:  2097152 byte VRAM @ 0x04e200
> > 0x0092:  2097152 byte  GTT
>
> pid 1382 command Xorg:
> > 0x0001:  2097152 byte VRAM @ 0x002800 ...
>
> Then next problem is that the amdgpu_gem_info is completely inaccurate 
> regarding the used memory of an application, since the same BO is sometimes 
> opened multiple times. That's also the reason why we don't provide a total of 
> the consumed memory. It basically just informs you which handle is what.
>
> Then last the debugfs files are not a stable interface and not meant to be 
> consumed by scripts and/or frontend applications. You should instead use 
> sysfs for this.
>
> Thanks for clarifying.
> UID should remain consistent even though X Server opens device on behalf of 
> App??
> Do you mean we may have entry for same BO inside file1->object_idr and 
> file2->object_idr ??
>
> So which interface inside sysfs/ we need to use to get:
> - Total Memory consumed by an application/pid
> - Details of BO like size, domain  (VRAM/GTT) etc per application/pid??

Whether you use this interface or another, it's not clear how you
should do the accounting for shared buffers.

Alex

>
> Regards,
> Madhav
>
> Regards,
> Christian.
>
> >
> > Regards,
> > Madhav
> >
> > Christian.
> >
> >> Regards,
> >> Madhav
> >>
> >> Christian.
> >>
> >>> Signed-off-by: Madhav Chauhan 
> >>> ---
> >>> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-
> >>> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> index f4c2e2e75b8f..c1982349ec7b 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> @@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file 
> >>> *m, void *data)
> >>> struct drm_info_node *node = (struct drm_info_node 
> >>> *)m->private;
> >>> struct drm_device *dev = node->minor->dev;
> >>> struct drm_file *file;
> >>> +   kuid_t uid;

RE: [PATCH] drm/amdgpu: Add uid info to process BO list

[Chauhan, Madhav]

[AMD Public Use]

-Original Message-
From: Christian König  
Sent: Tuesday, September 22, 2020 6:25 PM
To: Chauhan, Madhav ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Surampalli, Kishore 
; Patel, Mihir ; Saleem, Athar 
; Sharma, Shashank 
Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list

Am 22.09.20 um 12:38 schrieb Chauhan, Madhav:
> [AMD Public Use]
>
> -Original Message-
> From: Koenig, Christian 
> Sent: Tuesday, September 22, 2020 12:15 PM
> To: Chauhan, Madhav ; 
> amd-gfx@lists.freedesktop.org
> Cc: Surampalli, Kishore ; Patel, Mihir 
> ; Sharma, Shashank ; 
> Deucher, Alexander ; Saleem, Athar 
> 
> Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list
>
> Am 21.09.20 um 21:55 schrieb Chauhan, Madhav:
>> [AMD Public Use]
>>
>> -Original Message-
>> From: Christian König 
>> Sent: Tuesday, September 22, 2020 12:54 AM
>> To: Chauhan, Madhav ; 
>> amd-gfx@lists.freedesktop.org
>> Cc: Surampalli, Kishore ; Patel, Mihir 
>> ; Sharma, Shashank ; 
>> Deucher, Alexander ; Saleem, Athar 
>> 
>> Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list
>>
>> Am 21.09.20 um 21:18 schrieb Madhav Chauhan:
>>> UID is helpful while doing analysis of BO allocated by a process.
>> Looks like a bit overkill to me, why not get the uid from the process info?
>>
>> Not sure if I got your point , but used the similar method 
>> implemented at drm level inside drm_debugfs.c. Thanks
> Good argument, but I'm not sure if we should duplicate that here. What do you 
> need this for?
>
> Thanks, We need details of BOs allocated by a process and associated 
> UID so that we can do memory perf analysis using some scripts To find the top 
> consumer of GPU memory and see if those application can be optimized.
>
> Clients information at DRM level doesn’t print list of BO per process 
> and since that is handled by amdgpu driver specific Functions.  So all 
> the BO list information at one place is really useful and needed by our 
> customers as various other vendors Already provide this.

Well that is exactly the explanation I didn't want to hear :(

See both the drm client list as well as the amdgpu GEM info are only debugfs 
files and only intended for providing some information for debugging and are 
not 100% reliable for the use case you have here.

The first problem is that on modern installations the file descriptor is often 
opened by the X server instead of the application.

So for example you end up with:
> pid 1382 command Xorg:
>     0x0001:  2097152 byte VRAM @ 0x002a00
>     0x0002: 4096 byte  GTT @ 0x0006c7 
>     0x0090:   266240 byte VRAM @ 0x05e800
>     0x0091:  2097152 byte VRAM @ 0x04e200
>     0x0092:  2097152 byte  GTT 

pid 1382 command Xorg:
>     0x0001:  2097152 byte VRAM @ 0x002800 ...

Then next problem is that the amdgpu_gem_info is completely inaccurate 
regarding the used memory of an application, since the same BO is sometimes 
opened multiple times. That's also the reason why we don't provide a total of 
the consumed memory. It basically just informs you which handle is what.

Then last the debugfs files are not a stable interface and not meant to be 
consumed by scripts and/or frontend applications. You should instead use sysfs 
for this.

Thanks for clarifying. 
UID should remain consistent even though X Server opens device on behalf of 
App??
Do you mean we may have entry for same BO inside file1->object_idr and 
file2->object_idr ?? 

So which interface inside sysfs/ we need to use to get:
- Total Memory consumed by an application/pid
- Details of BO like size, domain  (VRAM/GTT) etc per application/pid??

Regards,
Madhav 

Regards,
Christian.

>
> Regards,
> Madhav
>
> Christian.
>
>> Regards,
>> Madhav
>>
>> Christian.
>>
>>> Signed-off-by: Madhav Chauhan 
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-
>>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>> index f4c2e2e75b8f..c1982349ec7b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>> @@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, 
>>> void *data)
>>> struct drm_info_node *node = (struct drm_info_node *)m->private;
>>> struct drm_device *dev = node->minor->dev;
>>> struct drm_file *file;
>>> +   kuid_t uid;
>>> int r;
>>> 
>>> r = mutex_lock_interruptible(>filelist_mutex);
>>> @@ -909,7 +910,10 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, 
>>> void *data)
>>>  */
>>> rcu_read_lock();
>>> task = pid_task(file->pid, PIDTYPE_PID);
>>> -   seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
>>> +  

Re: [PATCH AUTOSEL 5.4 13/15] drm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is

[Sasha Levin]

On Mon, Sep 21, 2020 at 04:48:05PM +0200, Michel Dänzer wrote:

On 2020-09-21 4:40 p.m., Sasha Levin wrote:

From: Michel Dänzer 

[ Upstream commit 2f228aab21bbc74e90e267a721215ec8be51daf7 ]

Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:

 * Hence drivers must not consult @active in their various
 * _mode_config_funcs.atomic_check callback to reject an atomic
 * commit.

atomic_remove_fb disables the CRTC as needed for disabling the primary
plane.

This prevents at least the following problems if the primary plane gets
disabled (e.g. due to destroying the FB assigned to the primary plane,
as happens e.g. with mutter in Wayland mode):

* The legacy cursor ioctl returned EINVAL for a non-0 cursor FB ID
  (which enables the cursor plane).
* If the cursor plane was enabled, changing the legacy DPMS property
  value from off to on returned EINVAL.

v2:
* Minor changes to code comment and commit log, per review feedback.

GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1108
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1165
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1344
Suggested-by: Daniel Vetter 
Acked-by: Daniel Vetter 
Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Michel Dänzer 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 


I'm a bit nervous about this getting backported so far back so 
quickly. I'd prefer waiting for 5.9 final first at least.


Will drop it for now, thanks.

--
Thanks,
Sasha
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Re: [PATCH] gpu/drm/radeon: fix spellint typo in comments

[Ernst Sjöstrand]

There is a typo in your patch subject. ;-)

Regards
//Ernst

Den tis 22 sep. 2020 kl 15:11 skrev Wang Qing :

> Modify the comment typo: "definately" -> "definitely".
>
> Signed-off-by: Wang Qing 
> ---
>  drivers/gpu/drm/radeon/radeon_vm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c
> b/drivers/gpu/drm/radeon/radeon_vm.c
> index f60fae0..3d6e2cd
> --- a/drivers/gpu/drm/radeon/radeon_vm.c
> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
> @@ -188,7 +188,7 @@ struct radeon_fence *radeon_vm_grab_id(struct
> radeon_device *rdev,
> vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
> return NULL;
>
> -   /* we definately need to flush */
> +   /* we definitely need to flush */
> vm_id->pd_gpu_addr = ~0ll;
>
> /* skip over VMID 0, since it is the system VM */
> --
> 2.7.4
>
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RE: [PATCH] drm/amdkfd: fix wanting in print statement

[Russell, Kent]

[AMD Public Use]

Definitely. Reviewed-by: Kent Russell  . 

> -Original Message-
> From: Alex Deucher 
> Sent: Tuesday, September 22, 2020 9:59 AM
> To: Russell, Kent 
> Cc: amd-gfx list ; Deucher, Alexander
> 
> Subject: Re: [PATCH] drm/amdkfd: fix wanting in print statement
> 
> Can I get an RB?
> 
> On Tue, Sep 22, 2020 at 9:56 AM Russell, Kent  wrote:
> >
> > [AMD Public Use]
> >
> > Thanks Alex, sorry about that!
> >
> >  Kent
> >
> > > -Original Message-
> > > From: amd-gfx  On Behalf Of Alex 
> > > Deucher
> > > Sent: Monday, September 21, 2020 5:33 PM
> > > To: amd-gfx list 
> > > Cc: Deucher, Alexander 
> > > Subject: Re: [PATCH] drm/amdkfd: fix wanting in print statement
> > >
> > > "warning" in print statement.  Fixed locally.
> > >
> > > On Mon, Sep 21, 2020 at 5:20 PM Alex Deucher  
> > > wrote:
> > > >
> > > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c: In function
> > > ‘kfd_create_crat_image_virtual’:
> > > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:12: warning: 
> > > > format ‘%d’
> > > expects argument of type ‘int’, but argument 3 has type ‘size_t’ {aka 
> > > ‘long unsigned int’}
> [-
> > > Wformat=]
> > > >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> > > >   |^
> > > > ./include/linux/printk.h:297:21: note: in definition of macro ‘pr_fmt’
> > > >   297 | #define pr_fmt(fmt) fmt
> > > >   | ^~~
> > > > ./include/linux/dynamic_debug.h:143:2: note: in expansion of macro
> > > ‘__dynamic_func_call’
> > > >   143 |  __dynamic_func_call(__UNIQUE_ID(ddebug), fmt, func, 
> > > > ##__VA_ARGS__)
> > > >   |  ^~~
> > > > ./include/linux/dynamic_debug.h:153:2: note: in expansion of macro
> > > ‘_dynamic_func_call’
> > > >   153 |  _dynamic_func_call(fmt, __dynamic_pr_debug,  \
> > > >   |  ^~
> > > > ./include/linux/printk.h:420:2: note: in expansion of macro 
> > > > ‘dynamic_pr_debug’
> > > >   420 |  dynamic_pr_debug(fmt, ##__VA_ARGS__)
> > > >   |  ^~~~
> > > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:3: note: in 
> > > > expansion of
> macro
> > > ‘pr_debug’
> > > >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> > > >   |   ^~~~
> > > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:27: note: format 
> > > > string is
> > > defined here
> > > >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> > > >   |  ~^
> > > >   |   |
> > > >   |   int
> > > >   |  %ld
> > > >
> > > > Signed-off-by: Alex Deucher 
> > > > ---
> > > >  drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > > b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > > > index c50e9f634d6c..d2981524dba0 100644
> > > > --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > > > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > > > @@ -1388,7 +1388,7 @@ int kfd_create_crat_image_virtual(void 
> > > > **crat_image, size_t
> > > *size,
> > > > if (!pcrat_image)
> > > > return -ENOMEM;
> > > > *size = dyn_size;
> > > > -   pr_debug("CRAT size is %d", dyn_size);
> > > > +   pr_debug("CRAT size is %ld", dyn_size);
> > > > ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
> > > > break;
> > > > case COMPUTE_UNIT_GPU:
> > > > --
> > > > 2.25.4
> > > >
> > > ___
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> > > amd-gfx@lists.freedesktop.org
> > >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.or
> > > g%2Fmailman%2Flistinfo%2Famd-
> > >
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> > >
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Re: [PATCH] drm/amdkfd: fix wanting in print statement

[Alex Deucher]

Can I get an RB?

On Tue, Sep 22, 2020 at 9:56 AM Russell, Kent  wrote:
>
> [AMD Public Use]
>
> Thanks Alex, sorry about that!
>
>  Kent
>
> > -Original Message-
> > From: amd-gfx  On Behalf Of Alex 
> > Deucher
> > Sent: Monday, September 21, 2020 5:33 PM
> > To: amd-gfx list 
> > Cc: Deucher, Alexander 
> > Subject: Re: [PATCH] drm/amdkfd: fix wanting in print statement
> >
> > "warning" in print statement.  Fixed locally.
> >
> > On Mon, Sep 21, 2020 at 5:20 PM Alex Deucher  wrote:
> > >
> > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c: In function
> > ‘kfd_create_crat_image_virtual’:
> > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:12: warning: format 
> > > ‘%d’
> > expects argument of type ‘int’, but argument 3 has type ‘size_t’ {aka ‘long 
> > unsigned int’} [-
> > Wformat=]
> > >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> > >   |^
> > > ./include/linux/printk.h:297:21: note: in definition of macro ‘pr_fmt’
> > >   297 | #define pr_fmt(fmt) fmt
> > >   | ^~~
> > > ./include/linux/dynamic_debug.h:143:2: note: in expansion of macro
> > ‘__dynamic_func_call’
> > >   143 |  __dynamic_func_call(__UNIQUE_ID(ddebug), fmt, func, 
> > > ##__VA_ARGS__)
> > >   |  ^~~
> > > ./include/linux/dynamic_debug.h:153:2: note: in expansion of macro
> > ‘_dynamic_func_call’
> > >   153 |  _dynamic_func_call(fmt, __dynamic_pr_debug,  \
> > >   |  ^~
> > > ./include/linux/printk.h:420:2: note: in expansion of macro 
> > > ‘dynamic_pr_debug’
> > >   420 |  dynamic_pr_debug(fmt, ##__VA_ARGS__)
> > >   |  ^~~~
> > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:3: note: in 
> > > expansion of macro
> > ‘pr_debug’
> > >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> > >   |   ^~~~
> > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:27: note: format 
> > > string is
> > defined here
> > >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> > >   |  ~^
> > >   |   |
> > >   |   int
> > >   |  %ld
> > >
> > > Signed-off-by: Alex Deucher 
> > > ---
> > >  drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > > index c50e9f634d6c..d2981524dba0 100644
> > > --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > > @@ -1388,7 +1388,7 @@ int kfd_create_crat_image_virtual(void 
> > > **crat_image, size_t
> > *size,
> > > if (!pcrat_image)
> > > return -ENOMEM;
> > > *size = dyn_size;
> > > -   pr_debug("CRAT size is %d", dyn_size);
> > > +   pr_debug("CRAT size is %ld", dyn_size);
> > > ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
> > > break;
> > > case COMPUTE_UNIT_GPU:
> > > --
> > > 2.25.4
> > >
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RE: [PATCH] drm/amdkfd: fix wanting in print statement

[Russell, Kent]

[AMD Public Use]

Thanks Alex, sorry about that!

 Kent

> -Original Message-
> From: amd-gfx  On Behalf Of Alex 
> Deucher
> Sent: Monday, September 21, 2020 5:33 PM
> To: amd-gfx list 
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH] drm/amdkfd: fix wanting in print statement
> 
> "warning" in print statement.  Fixed locally.
> 
> On Mon, Sep 21, 2020 at 5:20 PM Alex Deucher  wrote:
> >
> > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c: In function
> ‘kfd_create_crat_image_virtual’:
> > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:12: warning: format 
> > ‘%d’
> expects argument of type ‘int’, but argument 3 has type ‘size_t’ {aka ‘long 
> unsigned int’} [-
> Wformat=]
> >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> >   |^
> > ./include/linux/printk.h:297:21: note: in definition of macro ‘pr_fmt’
> >   297 | #define pr_fmt(fmt) fmt
> >   | ^~~
> > ./include/linux/dynamic_debug.h:143:2: note: in expansion of macro
> ‘__dynamic_func_call’
> >   143 |  __dynamic_func_call(__UNIQUE_ID(ddebug), fmt, func, ##__VA_ARGS__)
> >   |  ^~~
> > ./include/linux/dynamic_debug.h:153:2: note: in expansion of macro
> ‘_dynamic_func_call’
> >   153 |  _dynamic_func_call(fmt, __dynamic_pr_debug,  \
> >   |  ^~
> > ./include/linux/printk.h:420:2: note: in expansion of macro 
> > ‘dynamic_pr_debug’
> >   420 |  dynamic_pr_debug(fmt, ##__VA_ARGS__)
> >   |  ^~~~
> > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:3: note: in expansion 
> > of macro
> ‘pr_debug’
> >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> >   |   ^~~~
> > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:27: note: format 
> > string is
> defined here
> >  1391 |   pr_debug("CRAT size is %d", dyn_size);
> >   |  ~^
> >   |   |
> >   |   int
> >   |  %ld
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >  drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > index c50e9f634d6c..d2981524dba0 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > @@ -1388,7 +1388,7 @@ int kfd_create_crat_image_virtual(void **crat_image, 
> > size_t
> *size,
> > if (!pcrat_image)
> > return -ENOMEM;
> > *size = dyn_size;
> > -   pr_debug("CRAT size is %d", dyn_size);
> > +   pr_debug("CRAT size is %ld", dyn_size);
> > ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
> > break;
> > case COMPUTE_UNIT_GPU:
> > --
> > 2.25.4
> >
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amdgpu: call trace introduced in 5.9-rc1 for Lenovo L14 Renoir

[Dirk Gouders]

Hi,

I noticed a call trace (attached) when starting my machine (ThinkPad
L14).  This machine is new and I am still working on it's
configuration but visually noticeable is that scrolling in xterms with
SHIFT-PgUp/PgDn is broken.  Using the mouse wheel works.

It seems the call trace has been introduced between 5.8 and 5.9-rc1 and
I tried to bisect this but always end in situations where I dont't find
a bootable commit around the current bisect position.  Mainly the
machine then hangs when udevd is started.

Please let me know if I can help with further information.

Dirk

= lspci -vk 

06:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] 
Renoir (rev c3) (prog-if 00 [VGA controller])
Subsystem: Lenovo Renoir
Flags: bus master, fast devsel, latency 0, IRQ 64
Memory at 46000 (64-bit, prefetchable) [size=256M]
Memory at 47000 (64-bit, prefetchable) [size=2M]
I/O ports at 1000 [size=256]
Memory at fd30 (32-bit, non-prefetchable) [size=512K]
Capabilities: [48] Vendor Specific Information: Len=08 
Capabilities: [50] Power Management version 3
Capabilities: [64] Express Legacy Endpoint, MSI 00
Capabilities: [a0] MSI: Enable- Count=1/4 Maskable- 64bit+
Capabilities: [c0] MSI-X: Enable+ Count=4 Masked-
Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 

Capabilities: [270] Secondary PCI Express
Capabilities: [2b0] Address Translation Service (ATS)
Capabilities: [2c0] Page Request Interface (PRI)
Capabilities: [2d0] Process Address Space ID (PASID)
Capabilities: [400] Data Link Feature 
Capabilities: [410] Physical Layer 16.0 GT/s 
Capabilities: [440] Lane Margining at the Receiver 
Kernel driver in use: amdgpu
Kernel modules: amdgpu

= call trace ===

[5.181468] amdgpu :06:00.0: amdgpu: SMU is initialized successfully!
[5.182857] [drm] kiq ring mec 2 pipe 1 q 0
[5.183374] [ cut here ]
[5.183448] WARNING: CPU: 1 PID: 684 at 
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:716 
rn_clk_mgr_construct+0x242/0x389 [amdgpu]
[5.183449] Modules linked in: btusb btrtl btbcm btintel bluetooth 
ecdh_generic ecc iwlmvm mac80211 libarc4 wmi_bmof crct10dif_pclmul 
snd_hda_codec_realtek 
crc32c_intel iwlwifi snd_hda_codec_generic amdgpu(+) tpm_crb snd_hda_codec_hdmi 
gpu_sched i2c_algo_bit ttm sdhci_pci aesni_intel drm_kms_helper cqhci sdhci ccp
 syscopyarea snd_hda_intel sysfillrect tpm_tis snd_intel_dspcfg sysimgblt 
xhci_pci tpm_tis_core fb_sys_fops r8169 snd_hda_codec mmc_core snd_hda_core 
xhci_hcd 
thinkpad_acpi cfg80211 realtek drm snd_pcm rng_core mdio_devres sha1_generic 
snd_timer nvram libphy i2c_piix4 snd k10temp soundcore ledtrig_audio rfkill tpm 
hw
mon wmi battery ac video backlight pinctrl_amd acpi_cpufreq button efivarfs
[5.183470] CPU: 1 PID: 684 Comm: udevd Not tainted 5.9.0-rc6-x86_64+ #170
[5.183471] Hardware name: LENOVO 20U50008GE/20U50008GE, BIOS R19ET26W (1.10 
) 06/22/2020
[5.183531] RIP: 0010:rn_clk_mgr_construct+0x242/0x389 [amdgpu]
[5.183533] Code: 30 4d 85 c9 74 26 ba 03 00 00 00 83 bc d4 a8 00 00 00 00 
89 d6 74 0a 83 bc d4 ac 00 00 00 00 75 40 48 ff ca 48 83 fa ff 75 e1 <0f> 0b 83 
7
b 20 01 0f 84 13 01 00 00 81 bd e8 00 00 00 ff 14 37 00
[5.183533] RSP: 0018:c9000111f798 EFLAGS: 00010246
[5.183534] RAX: 8883fc1d8e00 RBX: 8883f925c9c0 RCX: 
[5.183535] RDX:  RSI:  RDI: 8883f8da70c8
[5.183535] RBP: 8883fe8da000 R08:  R09: 8883f724fc00
[5.183535] R10: 7fc9117f R11: 8883f925c9c0 R12: 8883f925c900
[5.183536] R13: 8883f598 R14:  R15: 0001
[5.183537] FS:  7f9e31a83d80() GS:88840ec4() 
knlGS:
[5.183537] CS:  0010 DS:  ES:  CR0: 80050033
[5.183538] CR2: 55fdf9ec5568 CR3: 0003fb2b6000 CR4: 00350ee0
[5.183538] Call Trace:
[5.183595]  dc_clk_mgr_create+0x135/0x18b [amdgpu]
[5.183651]  dc_create+0x238/0x5e3 [amdgpu]
[5.183708]  amdgpu_dm_init+0x167/0x1101 [amdgpu]
[5.183762]  dm_hw_init+0xa/0x17 [amdgpu]
[5.183805]  amdgpu_device_init+0x1566/0x1853 [amdgpu]
[5.183811]  ? __kmalloc+0xad/0xbf
[5.183852]  ? amdgpu_driver_load_kms+0x1c/0x17f [amdgpu]
[5.183892]  amdgpu_driver_load_kms+0x41/0x17f [amdgpu]
[5.183959]  amdgpu_pci_probe+0x139/0x1c0 [amdgpu]
[5.183967]  pci_device_probe+0xc6/0x135
[5.183971]  really_probe+0x157/0x32a
[5.183974]  driver_probe_device+0x63/0x97
[5.183976]  device_driver_attach+0x37/0x50
[5.183978]  __driver_attach+0x92/0x9a
[5.183980]  ? device_driver_attach+0x50/0x50
[

[PATCH 07/11] drm/qxl: switch over to the new pin interface

[Christian König]

Stop using TTM_PL_FLAG_NO_EVICT.

Signed-off-by: Christian König 
Reviewed-by: Gerd Hoffmann 
Tested-by: Gerd Hoffmann 
---
 drivers/gpu/drm/qxl/qxl_debugfs.c |  2 +-
 drivers/gpu/drm/qxl/qxl_drv.h |  1 -
 drivers/gpu/drm/qxl/qxl_ioctl.c   |  4 +--
 drivers/gpu/drm/qxl/qxl_object.c  | 44 +--
 drivers/gpu/drm/qxl/qxl_object.h  |  2 +-
 drivers/gpu/drm/qxl/qxl_release.c |  4 +--
 drivers/gpu/drm/qxl/qxl_ttm.c |  2 +-
 7 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/qxl/qxl_debugfs.c 
b/drivers/gpu/drm/qxl/qxl_debugfs.c
index 524d35b648d8..183d15e2cf58 100644
--- a/drivers/gpu/drm/qxl/qxl_debugfs.c
+++ b/drivers/gpu/drm/qxl/qxl_debugfs.c
@@ -67,7 +67,7 @@ qxl_debugfs_buffers_info(struct seq_file *m, void *data)
 
seq_printf(m, "size %ld, pc %d, num releases %d\n",
   (unsigned long)bo->tbo.base.size,
-  bo->pin_count, rel);
+  bo->tbo.pin_count, rel);
}
return 0;
 }
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index aae90a9ee1db..3602e8b34189 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -80,7 +80,6 @@ struct qxl_bo {
struct ttm_placeplacements[3];
struct ttm_placementplacement;
struct ttm_bo_kmap_obj  kmap;
-   unsigned int pin_count;
void*kptr;
unsigned intmap_count;
int type;
diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c
index 5cea6eea72ab..0bab9ec6adc1 100644
--- a/drivers/gpu/drm/qxl/qxl_ioctl.c
+++ b/drivers/gpu/drm/qxl/qxl_ioctl.c
@@ -326,8 +326,8 @@ static int qxl_update_area_ioctl(struct drm_device *dev, 
void *data,
if (ret)
goto out;
 
-   if (!qobj->pin_count) {
-   qxl_ttm_placement_from_domain(qobj, qobj->type, false);
+   if (!qobj->tbo.pin_count) {
+   qxl_ttm_placement_from_domain(qobj, qobj->type);
ret = ttm_bo_validate(>tbo, >placement, );
if (unlikely(ret))
goto out;
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index 2bc364412e8b..d3635e3e3267 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -51,14 +51,12 @@ bool qxl_ttm_bo_is_qxl_bo(struct ttm_buffer_object *bo)
return false;
 }
 
-void qxl_ttm_placement_from_domain(struct qxl_bo *qbo, u32 domain, bool pinned)
+void qxl_ttm_placement_from_domain(struct qxl_bo *qbo, u32 domain)
 {
u32 c = 0;
u32 pflag = 0;
unsigned int i;
 
-   if (pinned)
-   pflag |= TTM_PL_FLAG_NO_EVICT;
if (qbo->tbo.base.size <= PAGE_SIZE)
pflag |= TTM_PL_FLAG_TOPDOWN;
 
@@ -128,14 +126,13 @@ int qxl_bo_create(struct qxl_device *qdev,
}
bo->tbo.base.funcs = _object_funcs;
bo->type = domain;
-   bo->pin_count = pinned ? 1 : 0;
bo->surface_id = 0;
INIT_LIST_HEAD(>list);
 
if (surf)
bo->surf = *surf;
 
-   qxl_ttm_placement_from_domain(bo, domain, pinned);
+   qxl_ttm_placement_from_domain(bo, domain);
 
r = ttm_bo_init(>mman.bdev, >tbo, size, type,
>placement, 0, !kernel, size,
@@ -147,6 +144,8 @@ int qxl_bo_create(struct qxl_device *qdev,
size, domain);
return r;
}
+   if (pinned)
+   ttm_bo_pin(>tbo);
*bo_ptr = bo;
return 0;
 }
@@ -248,39 +247,22 @@ static int __qxl_bo_pin(struct qxl_bo *bo)
struct drm_device *ddev = bo->tbo.base.dev;
int r;
 
-   if (bo->pin_count) {
-   bo->pin_count++;
+   if (bo->tbo.pin_count) {
+   ttm_bo_pin(>tbo);
return 0;
}
-   qxl_ttm_placement_from_domain(bo, bo->type, true);
+   qxl_ttm_placement_from_domain(bo, bo->type);
r = ttm_bo_validate(>tbo, >placement, );
-   if (likely(r == 0)) {
-   bo->pin_count = 1;
-   }
+   if (likely(r == 0))
+   ttm_bo_pin(>tbo);
if (unlikely(r != 0))
dev_err(ddev->dev, "%p pin failed\n", bo);
return r;
 }
 
-static int __qxl_bo_unpin(struct qxl_bo *bo)
+static void __qxl_bo_unpin(struct qxl_bo *bo)
 {
-   struct ttm_operation_ctx ctx = { false, false };
-   struct drm_device *ddev = bo->tbo.base.dev;
-   int r, i;
-
-   if (!bo->pin_count) {
-   dev_warn(ddev->dev, "%p unpin not necessary\n", bo);
-   return 0;
-   }
-   bo->pin_count--;
-   if (bo->pin_count)
-   return 0;
-   for (i = 0; i < bo->placement.num_placement; i++)
-   bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
-   r = 

[PATCH 11/11] drm/ttm: remove TTM_PL_FLAG_NO_EVICT

[Christian König]

Not used any more.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_bo.c| 11 +++
 include/drm/ttm/ttm_placement.h |  1 -
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 1a4b25083326..5737b3fae1b3 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -118,9 +118,6 @@ static void ttm_bo_add_mem_to_lru(struct ttm_buffer_object 
*bo,
if (!list_empty(>lru) || bo->pin_count)
return;
 
-   if (mem->placement & TTM_PL_FLAG_NO_EVICT)
-   return;
-
man = ttm_manager_type(bdev, mem->mem_type);
list_add_tail(>lru, >lru[bo->priority]);
 
@@ -165,8 +162,7 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
ttm_bo_del_from_lru(bo);
ttm_bo_add_mem_to_lru(bo, >mem);
 
-   if (bulk && !(bo->mem.placement & TTM_PL_FLAG_NO_EVICT) &&
-   !bo->pin_count) {
+   if (bulk && !bo->pin_count) {
switch (bo->mem.mem_type) {
case TTM_PL_TT:
ttm_bo_bulk_move_set_pos(>tt[bo->priority], bo);
@@ -541,12 +537,11 @@ static void ttm_bo_release(struct kref *kref)
spin_lock(_bo_glob.lru_lock);
 
/*
-* Make NO_EVICT bos immediately available to
+* Make pinned bos immediately available to
 * shrinkers, now that they are queued for
 * destruction.
 */
-   if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT || bo->pin_count) {
-   bo->mem.placement &= ~TTM_PL_FLAG_NO_EVICT;
+   if (bo->pin_count) {
bo->pin_count = 0;
ttm_bo_del_from_lru(bo);
ttm_bo_add_mem_to_lru(bo, >mem);
diff --git a/include/drm/ttm/ttm_placement.h b/include/drm/ttm/ttm_placement.h
index d4022655eae4..50e72df48b8d 100644
--- a/include/drm/ttm/ttm_placement.h
+++ b/include/drm/ttm/ttm_placement.h
@@ -58,7 +58,6 @@
 #define TTM_PL_FLAG_UNCACHED(1 << 17)
 #define TTM_PL_FLAG_WC  (1 << 18)
 #define TTM_PL_FLAG_CONTIGUOUS  (1 << 19)
-#define TTM_PL_FLAG_NO_EVICT(1 << 21)
 #define TTM_PL_FLAG_TOPDOWN (1 << 22)
 
 #define TTM_PL_MASK_CACHING (TTM_PL_FLAG_CACHED | \
-- 
2.17.1

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[PATCH 04/11] drm/vmwgfx: switch over to the new pin interface v2

[Christian König]

Stop using TTM_PL_FLAG_NO_EVICT.

v2: fix unconditional pinning

Signed-off-by: Christian König 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_blit.c   |  4 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 49 +++---
 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c|  4 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c|  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h|  7 +---
 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c |  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c   |  4 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c   |  4 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c |  4 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 42 ---
 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c |  2 +-
 11 files changed, 39 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
index e8d66182cd7b..ea2f2f937eb3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
@@ -459,9 +459,9 @@ int vmw_bo_cpu_blit(struct ttm_buffer_object *dst,
int ret = 0;
 
/* Buffer objects need to be either pinned or reserved: */
-   if (!(dst->mem.placement & TTM_PL_FLAG_NO_EVICT))
+   if (!(dst->pin_count))
dma_resv_assert_held(dst->base.resv);
-   if (!(src->mem.placement & TTM_PL_FLAG_NO_EVICT))
+   if (!(src->pin_count))
dma_resv_assert_held(src->base.resv);
 
if (!ttm_tt_is_populated(dst->ttm)) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
index 30d19b45b602..a1f675c5f471 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
@@ -106,7 +106,7 @@ int vmw_bo_pin_in_placement(struct vmw_private *dev_priv,
if (unlikely(ret != 0))
goto err;
 
-   if (buf->pin_count > 0)
+   if (buf->base.pin_count > 0)
ret = ttm_bo_mem_compat(placement, >mem,
_flags) == true ? 0 : -EINVAL;
else
@@ -155,7 +155,7 @@ int vmw_bo_pin_in_vram_or_gmr(struct vmw_private *dev_priv,
if (unlikely(ret != 0))
goto err;
 
-   if (buf->pin_count > 0) {
+   if (buf->base.pin_count > 0) {
ret = ttm_bo_mem_compat(_vram_gmr_placement, >mem,
_flags) == true ? 0 : -EINVAL;
goto out_unreserve;
@@ -246,12 +246,12 @@ int vmw_bo_pin_in_start_of_vram(struct vmw_private 
*dev_priv,
if (bo->mem.mem_type == TTM_PL_VRAM &&
bo->mem.start < bo->num_pages &&
bo->mem.start > 0 &&
-   buf->pin_count == 0) {
+   buf->base.pin_count == 0) {
ctx.interruptible = false;
(void) ttm_bo_validate(bo, _sys_placement, );
}
 
-   if (buf->pin_count > 0)
+   if (buf->base.pin_count > 0)
ret = ttm_bo_mem_compat(, >mem,
_flags) == true ? 0 : -EINVAL;
else
@@ -343,23 +343,13 @@ void vmw_bo_pin_reserved(struct vmw_buffer_object *vbo, 
bool pin)
 
dma_resv_assert_held(bo->base.resv);
 
-   if (pin) {
-   if (vbo->pin_count++ > 0)
-   return;
-   } else {
-   WARN_ON(vbo->pin_count <= 0);
-   if (--vbo->pin_count > 0)
-   return;
-   }
+   if (pin == !!bo->pin_count)
+   return;
 
pl.fpfn = 0;
pl.lpfn = 0;
pl.mem_type = bo->mem.mem_type;
pl.flags = bo->mem.placement;
-   if (pin)
-   pl.flags |= TTM_PL_FLAG_NO_EVICT;
-   else
-   pl.flags &= ~TTM_PL_FLAG_NO_EVICT;
 
memset(, 0, sizeof(placement));
placement.num_placement = 1;
@@ -368,8 +358,12 @@ void vmw_bo_pin_reserved(struct vmw_buffer_object *vbo, 
bool pin)
ret = ttm_bo_validate(bo, , );
 
BUG_ON(ret != 0 || bo->mem.mem_type != old_mem_type);
-}
 
+   if (pin)
+   ttm_bo_pin(bo);
+   else
+   ttm_bo_unpin(bo);
+}
 
 /**
  * vmw_bo_map_and_cache - Map a buffer object and cache the map
@@ -538,6 +532,7 @@ int vmw_bo_create_kernel(struct vmw_private *dev_priv, 
unsigned long size,
  * @size: Buffer object size in bytes.
  * @placement: Initial placement.
  * @interruptible: Whether waits should be performed interruptible.
+ * @pin: If the BO should be created pinned at a fixed location.
  * @bo_free: The buffer object destructor.
  * Returns: Zero on success, negative error code on error.
  *
@@ -546,9 +541,10 @@ int vmw_bo_create_kernel(struct vmw_private *dev_priv, 
unsigned long size,
 int vmw_bo_init(struct vmw_private *dev_priv,
struct vmw_buffer_object *vmw_bo,
size_t size, struct ttm_placement *placement,
-   bool interruptible,
+   bool interruptible, bool pin,
void (*bo_free)(struct ttm_buffer_object *bo))
 {
+   struct 

[PATCH 10/11] drm/ttm: remove ttm_bo_create

[Christian König]

Not used any more.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_bo.c | 40 
 include/drm/ttm/ttm_bo_api.h | 24 --
 2 files changed, 64 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index b82b49d43942..1a4b25083326 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1254,19 +1254,6 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
 }
 EXPORT_SYMBOL(ttm_bo_init);
 
-static size_t ttm_bo_acc_size(struct ttm_bo_device *bdev,
- unsigned long bo_size,
- unsigned struct_size)
-{
-   unsigned npages = (PAGE_ALIGN(bo_size)) >> PAGE_SHIFT;
-   size_t size = 0;
-
-   size += ttm_round_pot(struct_size);
-   size += ttm_round_pot(npages * sizeof(void *));
-   size += ttm_round_pot(sizeof(struct ttm_tt));
-   return size;
-}
-
 size_t ttm_bo_dma_acc_size(struct ttm_bo_device *bdev,
   unsigned long bo_size,
   unsigned struct_size)
@@ -1281,33 +1268,6 @@ size_t ttm_bo_dma_acc_size(struct ttm_bo_device *bdev,
 }
 EXPORT_SYMBOL(ttm_bo_dma_acc_size);
 
-int ttm_bo_create(struct ttm_bo_device *bdev,
-   unsigned long size,
-   enum ttm_bo_type type,
-   struct ttm_placement *placement,
-   uint32_t page_alignment,
-   bool interruptible,
-   struct ttm_buffer_object **p_bo)
-{
-   struct ttm_buffer_object *bo;
-   size_t acc_size;
-   int ret;
-
-   bo = kzalloc(sizeof(*bo), GFP_KERNEL);
-   if (unlikely(bo == NULL))
-   return -ENOMEM;
-
-   acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct 
ttm_buffer_object));
-   ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
- interruptible, acc_size,
- NULL, NULL, NULL);
-   if (likely(ret == 0))
-   *p_bo = bo;
-
-   return ret;
-}
-EXPORT_SYMBOL(ttm_bo_create);
-
 int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type)
 {
struct ttm_resource_manager *man = ttm_manager_type(bdev, mem_type);
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 33aca60870e2..6cbe59bc97ab 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -447,30 +447,6 @@ int ttm_bo_init(struct ttm_bo_device *bdev, struct 
ttm_buffer_object *bo,
struct sg_table *sg, struct dma_resv *resv,
void (*destroy) (struct ttm_buffer_object *));
 
-/**
- * ttm_bo_create
- *
- * @bdev: Pointer to a ttm_bo_device struct.
- * @size: Requested size of buffer object.
- * @type: Requested type of buffer object.
- * @placement: Initial placement.
- * @page_alignment: Data alignment in pages.
- * @interruptible: If needing to sleep while waiting for GPU resources,
- * sleep interruptible.
- * @p_bo: On successful completion *p_bo points to the created object.
- *
- * This function allocates a ttm_buffer_object, and then calls ttm_bo_init
- * on that object. The destroy function is set to kfree().
- * Returns
- * -ENOMEM: Out of memory.
- * -EINVAL: Invalid placement flags.
- * -ERESTARTSYS: Interrupted by signal while waiting for resources.
- */
-int ttm_bo_create(struct ttm_bo_device *bdev, unsigned long size,
- enum ttm_bo_type type, struct ttm_placement *placement,
- uint32_t page_alignment, bool interruptible,
- struct ttm_buffer_object **p_bo);
-
 /**
  * ttm_bo_evict_mm
  *
-- 
2.17.1

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[PATCH 06/11] drm/vram-helper: switch over to the new pin interface

[Christian König]

Stop using TTM_PL_FLAG_NO_EVICT.

Signed-off-by: Christian König 
Acked-by: Thomas Zimmermann 
---
 drivers/gpu/drm/drm_gem_vram_helper.c | 37 +++
 include/drm/drm_gem_vram_helper.h |  3 ---
 2 files changed, 9 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c 
b/drivers/gpu/drm/drm_gem_vram_helper.c
index 50cad0e4a92e..bd3dd17ad81d 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -301,7 +301,7 @@ static u64 drm_gem_vram_pg_offset(struct 
drm_gem_vram_object *gbo)
  */
 s64 drm_gem_vram_offset(struct drm_gem_vram_object *gbo)
 {
-   if (WARN_ON_ONCE(!gbo->pin_count))
+   if (WARN_ON_ONCE(!gbo->bo.pin_count))
return (s64)-ENODEV;
return drm_gem_vram_pg_offset(gbo) << PAGE_SHIFT;
 }
@@ -310,24 +310,21 @@ EXPORT_SYMBOL(drm_gem_vram_offset);
 static int drm_gem_vram_pin_locked(struct drm_gem_vram_object *gbo,
   unsigned long pl_flag)
 {
-   int i, ret;
struct ttm_operation_ctx ctx = { false, false };
+   int ret;
 
-   if (gbo->pin_count)
+   if (gbo->bo.pin_count)
goto out;
 
if (pl_flag)
drm_gem_vram_placement(gbo, pl_flag);
 
-   for (i = 0; i < gbo->placement.num_placement; ++i)
-   gbo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
-
ret = ttm_bo_validate(>bo, >placement, );
if (ret < 0)
return ret;
 
 out:
-   ++gbo->pin_count;
+   ttm_bo_pin(>bo);
 
return 0;
 }
@@ -369,26 +366,9 @@ int drm_gem_vram_pin(struct drm_gem_vram_object *gbo, 
unsigned long pl_flag)
 }
 EXPORT_SYMBOL(drm_gem_vram_pin);
 
-static int drm_gem_vram_unpin_locked(struct drm_gem_vram_object *gbo)
+static void drm_gem_vram_unpin_locked(struct drm_gem_vram_object *gbo)
 {
-   int i, ret;
-   struct ttm_operation_ctx ctx = { false, false };
-
-   if (WARN_ON_ONCE(!gbo->pin_count))
-   return 0;
-
-   --gbo->pin_count;
-   if (gbo->pin_count)
-   return 0;
-
-   for (i = 0; i < gbo->placement.num_placement ; ++i)
-   gbo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
-
-   ret = ttm_bo_validate(>bo, >placement, );
-   if (ret < 0)
-   return ret;
-
-   return 0;
+   ttm_bo_unpin(>bo);
 }
 
 /**
@@ -406,10 +386,11 @@ int drm_gem_vram_unpin(struct drm_gem_vram_object *gbo)
ret = ttm_bo_reserve(>bo, true, false, NULL);
if (ret)
return ret;
-   ret = drm_gem_vram_unpin_locked(gbo);
+
+   drm_gem_vram_unpin_locked(gbo);
ttm_bo_unreserve(>bo);
 
-   return ret;
+   return 0;
 }
 EXPORT_SYMBOL(drm_gem_vram_unpin);
 
diff --git a/include/drm/drm_gem_vram_helper.h 
b/include/drm/drm_gem_vram_helper.h
index 62cc6e6c3a4f..128f88174d32 100644
--- a/include/drm/drm_gem_vram_helper.h
+++ b/include/drm/drm_gem_vram_helper.h
@@ -35,7 +35,6 @@ struct vm_area_struct;
  * @placement: TTM placement information. Supported placements are \
%TTM_PL_VRAM and %TTM_PL_SYSTEM
  * @placements:TTM placement information.
- * @pin_count: Pin counter
  *
  * The type struct drm_gem_vram_object represents a GEM object that is
  * backed by VRAM. It can be used for simple framebuffer devices with
@@ -64,8 +63,6 @@ struct drm_gem_vram_object {
/* Supported placements are %TTM_PL_VRAM and %TTM_PL_SYSTEM */
struct ttm_placement placement;
struct ttm_place placements[2];
-
-   int pin_count;
 };
 
 /**
-- 
2.17.1

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[PATCH 03/11] drm/vmwgfx: stop using ttm_bo_create

[Christian König]

Implement in the driver instead since it is the only user of that function.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 42 ++
 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c |  6 ++--
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h|  4 +++
 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c |  8 ++---
 4 files changed, 52 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
index 813f1b148094..30d19b45b602 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
@@ -487,6 +487,48 @@ static void vmw_user_bo_destroy(struct ttm_buffer_object 
*bo)
ttm_prime_object_kfree(vmw_user_bo, prime);
 }
 
+/**
+ * vmw_bo_create_kernel - Create a pinned BO for internal kernel use.
+ *
+ * @dev_priv: Pointer to the device private struct
+ * @size: size of the BO we need
+ * @placement: where to put it
+ * @p_bo: resulting BO
+ *
+ * Creates and pin a simple BO for in kernel use.
+ */
+int vmw_bo_create_kernel(struct vmw_private *dev_priv, unsigned long size,
+struct ttm_placement *placement,
+struct ttm_buffer_object **p_bo)
+{
+   unsigned npages = PAGE_ALIGN(size) >> PAGE_SHIFT;
+   struct ttm_buffer_object *bo;
+   size_t acc_size;
+   int ret;
+
+   bo = kzalloc(sizeof(*bo), GFP_KERNEL);
+   if (unlikely(!bo))
+   return -ENOMEM;
+
+   acc_size = ttm_round_pot(sizeof(*bo));
+   acc_size += ttm_round_pot(npages * sizeof(void *));
+   acc_size += ttm_round_pot(sizeof(struct ttm_tt));
+   ret = ttm_bo_init_reserved(_priv->bdev, bo, size,
+  ttm_bo_type_device, placement, 0,
+  false, acc_size, NULL, NULL, NULL);
+   if (unlikely(ret))
+   goto error_free;
+
+   ttm_bo_pin(bo);
+   ttm_bo_unreserve(bo);
+   *p_bo = bo;
+
+   return 0;
+
+error_free:
+   kfree(bo);
+   return ret;
+}
 
 /**
  * vmw_bo_init - Initialize a vmw buffer object
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
index 3b41cf63110a..9a9fe10d829b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
@@ -1245,9 +1245,9 @@ int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
!dev_priv->has_mob)
return -ENOMEM;
 
-   ret = ttm_bo_create(_priv->bdev, size, ttm_bo_type_device,
-   _mob_ne_placement, 0, false,
-   >cmd_space);
+   ret = vmw_bo_create_kernel(dev_priv, size,
+  _mob_placement,
+  >cmd_space);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h 
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 9ceee4eb0b13..5d07de5183e1 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -845,6 +845,10 @@ extern void vmw_bo_get_guest_ptr(const struct 
ttm_buffer_object *buf,
 SVGAGuestPtr *ptr);
 extern void vmw_bo_pin_reserved(struct vmw_buffer_object *bo, bool pin);
 extern void vmw_bo_bo_free(struct ttm_buffer_object *bo);
+extern int vmw_bo_create_kernel(struct vmw_private *dev_priv,
+   unsigned long size,
+   struct ttm_placement *placement,
+   struct ttm_buffer_object **p_bo);
 extern int vmw_bo_init(struct vmw_private *dev_priv,
   struct vmw_buffer_object *vmw_bo,
   size_t size, struct ttm_placement *placement,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index d7ea658e9910..39a2f720f4ed 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
@@ -793,11 +793,9 @@ int vmw_bo_create_and_populate(struct vmw_private 
*dev_priv,
struct ttm_buffer_object *bo;
int ret;
 
-   ret = ttm_bo_create(_priv->bdev, bo_size,
-   ttm_bo_type_device,
-   _sys_ne_placement,
-   0, false, );
-
+   ret = vmw_bo_create_kernel(dev_priv, bo_size,
+  _sys_placement,
+  );
if (unlikely(ret != 0))
return ret;
 
-- 
2.17.1

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[PATCH 09/11] drm/amdgpu: switch over to the new pin interface

[Christian König]

Stop using TTM_PL_FLAG_NO_EVICT.

Signed-off-by: Christian König 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  5 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  8 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c   |  5 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 41 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|  2 +-
 9 files changed, 24 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index b6b821500d30..64d4b5ff95d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1479,7 +1479,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
}
}
 
-   if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->pin_count)
+   if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
amdgpu_bo_fence(bo,
>process_info->eviction_fence->base,
true);
@@ -1558,7 +1558,8 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
 * required.
 */
if (mem->mapped_to_gpu_memory == 0 &&
-   !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && !mem->bo->pin_count)
+   !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
+   !mem->bo->tbo.pin_count)
amdgpu_amdkfd_remove_eviction_fence(mem->bo,
process_info->eviction_fence);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 12598a4b5c78..d50b63a93d37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -410,7 +410,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
uint32_t domain;
int r;
 
-   if (bo->pin_count)
+   if (bo->tbo.pin_count)
return 0;
 
/* Don't move this buffer if we have depleted our allowance
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index c81206e6096f..4cba095b6c44 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -132,10 +132,7 @@ static void amdgpu_display_unpin_work_func(struct 
work_struct *__work)
/* unpin of the old buffer */
r = amdgpu_bo_reserve(work->old_abo, true);
if (likely(r == 0)) {
-   r = amdgpu_bo_unpin(work->old_abo);
-   if (unlikely(r != 0)) {
-   DRM_ERROR("failed to unpin buffer after flip\n");
-   }
+   amdgpu_bo_unpin(work->old_abo);
amdgpu_bo_unreserve(work->old_abo);
} else
DRM_ERROR("failed to reserve buffer after flip\n");
@@ -249,8 +246,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc 
*crtc,
}
 unpin:
if (!adev->enable_virtual_display)
-   if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
-   DRM_ERROR("failed to unpin new abo in error path\n");
+   amdgpu_bo_unpin(new_abo);
 
 unreserve:
amdgpu_bo_unreserve(new_abo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index 957934926b24..5b465ab774d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -281,7 +281,7 @@ static struct sg_table *amdgpu_dma_buf_map(struct 
dma_buf_attachment *attach,
struct sg_table *sgt;
long r;
 
-   if (!bo->pin_count) {
+   if (!bo->tbo.pin_count) {
/* move buffer into GTT or VRAM */
struct ttm_operation_ctx ctx = { false, false };
unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
@@ -390,7 +390,8 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf 
*dma_buf,
if (unlikely(ret != 0))
return ret;
 
-   if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
+   if (!bo->tbo.pin_count &&
+   (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
ret = ttm_bo_validate(>tbo, >placement, );
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index aa7f230c71bf..59b52804622d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -860,7 +860,7 @@ static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, 
void *data)
seq_printf(m, "\t0x%08x: %12ld byte %s",
   id, amdgpu_bo_size(bo), placement);
 
-   pin_count = 

[PATCH 08/11] drm/radeon: switch over to the new pin interface

[Christian König]

Stop using TTM_PL_FLAG_NO_EVICT.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/radeon/radeon.h |  1 -
 drivers/gpu/drm/radeon/radeon_display.c |  9 ++
 drivers/gpu/drm/radeon/radeon_object.c  | 37 ++---
 drivers/gpu/drm/radeon/radeon_object.h  |  2 +-
 drivers/gpu/drm/radeon/radeon_ttm.c |  2 +-
 5 files changed, 13 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a6d8de01194a..5d54bccebd4d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -497,7 +497,6 @@ struct radeon_bo {
struct ttm_buffer_objecttbo;
struct ttm_bo_kmap_obj  kmap;
u32 flags;
-   unsignedpin_count;
void*kptr;
u32 tiling_flags;
u32 pitch;
diff --git a/drivers/gpu/drm/radeon/radeon_display.c 
b/drivers/gpu/drm/radeon/radeon_display.c
index 7b69d6dfe44a..3eacf33bbe48 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -273,10 +273,7 @@ static void radeon_unpin_work_func(struct work_struct 
*__work)
/* unpin of the old buffer */
r = radeon_bo_reserve(work->old_rbo, false);
if (likely(r == 0)) {
-   r = radeon_bo_unpin(work->old_rbo);
-   if (unlikely(r != 0)) {
-   DRM_ERROR("failed to unpin buffer after flip\n");
-   }
+   radeon_bo_unpin(work->old_rbo);
radeon_bo_unreserve(work->old_rbo);
} else
DRM_ERROR("failed to reserve buffer after flip\n");
@@ -607,9 +604,7 @@ static int radeon_crtc_page_flip_target(struct drm_crtc 
*crtc,
DRM_ERROR("failed to reserve new rbo in error path\n");
goto cleanup;
}
-   if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
-   DRM_ERROR("failed to unpin new rbo in error path\n");
-   }
+   radeon_bo_unpin(new_rbo);
radeon_bo_unreserve(new_rbo);
 
 cleanup:
diff --git a/drivers/gpu/drm/radeon/radeon_object.c 
b/drivers/gpu/drm/radeon/radeon_object.c
index 316e35d3f8a9..0de267ab3913 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -334,8 +334,8 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 
domain, u64 max_offset,
if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
return -EPERM;
 
-   if (bo->pin_count) {
-   bo->pin_count++;
+   if (bo->tbo.pin_count) {
+   ttm_bo_pin(>tbo);
if (gpu_addr)
*gpu_addr = radeon_bo_gpu_offset(bo);
 
@@ -367,13 +367,11 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 
domain, u64 max_offset,
bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
else
bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
-
-   bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
}
 
r = ttm_bo_validate(>tbo, >placement, );
if (likely(r == 0)) {
-   bo->pin_count = 1;
+   ttm_bo_pin(>tbo);
if (gpu_addr != NULL)
*gpu_addr = radeon_bo_gpu_offset(bo);
if (domain == RADEON_GEM_DOMAIN_VRAM)
@@ -391,32 +389,15 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 
*gpu_addr)
return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 }
 
-int radeon_bo_unpin(struct radeon_bo *bo)
+void radeon_bo_unpin(struct radeon_bo *bo)
 {
-   struct ttm_operation_ctx ctx = { false, false };
-   int r, i;
-
-   if (!bo->pin_count) {
-   dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
-   return 0;
-   }
-   bo->pin_count--;
-   if (bo->pin_count)
-   return 0;
-   for (i = 0; i < bo->placement.num_placement; i++) {
-   bo->placements[i].lpfn = 0;
-   bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
-   }
-   r = ttm_bo_validate(>tbo, >placement, );
-   if (likely(r == 0)) {
+   ttm_bo_unpin(>tbo);
+   if (!bo->tbo.pin_count) {
if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
bo->rdev->vram_pin_size -= radeon_bo_size(bo);
else
bo->rdev->gart_pin_size -= radeon_bo_size(bo);
-   } else {
-   dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
}
-   return r;
 }
 
 int radeon_bo_evict_vram(struct radeon_device *rdev)
@@ -549,7 +530,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev,
 
list_for_each_entry(lobj, head, tv.head) {
struct radeon_bo *bo = lobj->robj;
-   if (!bo->pin_count) {
+   if 

[PATCH 02/11] drm/vmwgfx: remove unused placement combination

[Christian König]

Just some dead code cleanup.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h|  1 -
 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 30 --
 2 files changed, 31 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h 
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 1523b51a7284..9ceee4eb0b13 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -1008,7 +1008,6 @@ extern struct ttm_placement vmw_vram_placement;
 extern struct ttm_placement vmw_vram_ne_placement;
 extern struct ttm_placement vmw_vram_sys_placement;
 extern struct ttm_placement vmw_vram_gmr_placement;
-extern struct ttm_placement vmw_vram_gmr_ne_placement;
 extern struct ttm_placement vmw_sys_placement;
 extern struct ttm_placement vmw_sys_ne_placement;
 extern struct ttm_placement vmw_evictable_placement;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index 7454f797d37b..d7ea658e9910 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
@@ -65,13 +65,6 @@ static const struct ttm_place gmr_placement_flags = {
.flags = TTM_PL_FLAG_CACHED
 };
 
-static const struct ttm_place gmr_ne_placement_flags = {
-   .fpfn = 0,
-   .lpfn = 0,
-   .mem_type = VMW_PL_GMR,
-   .flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT
-};
-
 static const struct ttm_place mob_placement_flags = {
.fpfn = 0,
.lpfn = 0,
@@ -128,29 +121,6 @@ struct ttm_placement vmw_vram_gmr_placement = {
.busy_placement = _placement_flags
 };
 
-static const struct ttm_place vram_gmr_ne_placement_flags[] = {
-   {
-   .fpfn = 0,
-   .lpfn = 0,
-   .mem_type = TTM_PL_VRAM,
-   .flags = TTM_PL_FLAG_CACHED |
-TTM_PL_FLAG_NO_EVICT
-   }, {
-   .fpfn = 0,
-   .lpfn = 0,
-   .mem_type = VMW_PL_GMR,
-   .flags = TTM_PL_FLAG_CACHED |
-TTM_PL_FLAG_NO_EVICT
-   }
-};
-
-struct ttm_placement vmw_vram_gmr_ne_placement = {
-   .num_placement = 2,
-   .placement = vram_gmr_ne_placement_flags,
-   .num_busy_placement = 1,
-   .busy_placement = _ne_placement_flags
-};
-
 struct ttm_placement vmw_vram_sys_placement = {
.num_placement = 1,
.placement = _placement_flags,
-- 
2.17.1

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[PATCH 01/11] drm/ttm: add ttm_bo_pin()/ttm_bo_unpin() v2

[Christian König]

As an alternative to the placement flag add a
pin count to the ttm buffer object.

v2: add dma_resv_assert_help() calls

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_bo.c  |  9 ++---
 drivers/gpu/drm/ttm/ttm_bo_util.c |  2 +-
 include/drm/ttm/ttm_bo_api.h  | 26 ++
 3 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 70b3bee27850..b82b49d43942 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -115,7 +115,7 @@ static void ttm_bo_add_mem_to_lru(struct ttm_buffer_object 
*bo,
struct ttm_bo_device *bdev = bo->bdev;
struct ttm_resource_manager *man;
 
-   if (!list_empty(>lru))
+   if (!list_empty(>lru) || bo->pin_count)
return;
 
if (mem->placement & TTM_PL_FLAG_NO_EVICT)
@@ -165,7 +165,8 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
ttm_bo_del_from_lru(bo);
ttm_bo_add_mem_to_lru(bo, >mem);
 
-   if (bulk && !(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
+   if (bulk && !(bo->mem.placement & TTM_PL_FLAG_NO_EVICT) &&
+   !bo->pin_count) {
switch (bo->mem.mem_type) {
case TTM_PL_TT:
ttm_bo_bulk_move_set_pos(>tt[bo->priority], bo);
@@ -544,8 +545,9 @@ static void ttm_bo_release(struct kref *kref)
 * shrinkers, now that they are queued for
 * destruction.
 */
-   if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) {
+   if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT || bo->pin_count) {
bo->mem.placement &= ~TTM_PL_FLAG_NO_EVICT;
+   bo->pin_count = 0;
ttm_bo_del_from_lru(bo);
ttm_bo_add_mem_to_lru(bo, >mem);
}
@@ -1172,6 +1174,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
bo->moving = NULL;
bo->mem.placement = TTM_PL_FLAG_CACHED;
bo->acc_size = acc_size;
+   bo->pin_count = 0;
bo->sg = sg;
if (resv) {
bo->base.resv = resv;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index fb2a25f8408f..1968df9743fc 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -352,7 +352,6 @@ static int ttm_buffer_object_transfer(struct 
ttm_buffer_object *bo,
return -ENOMEM;
 
fbo->base = *bo;
-   fbo->base.mem.placement |= TTM_PL_FLAG_NO_EVICT;
 
ttm_bo_get(bo);
fbo->bo = bo;
@@ -372,6 +371,7 @@ static int ttm_buffer_object_transfer(struct 
ttm_buffer_object *bo,
kref_init(>base.kref);
fbo->base.destroy = _transfered_destroy;
fbo->base.acc_size = 0;
+   fbo->base.pin_count = 1;
if (bo->type != ttm_bo_type_sg)
fbo->base.base.resv = >base.base._resv;
 
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 0f7cd21d6d74..33aca60870e2 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -157,6 +157,7 @@ struct ttm_buffer_object {
 
struct dma_fence *moving;
unsigned priority;
+   unsigned pin_count;
 
/**
 * Special members that are protected by the reserve lock
@@ -606,6 +607,31 @@ static inline bool ttm_bo_uses_embedded_gem_object(struct 
ttm_buffer_object *bo)
return bo->base.dev != NULL;
 }
 
+/**
+ * ttm_bo_pin - Pin the buffer object.
+ * @bo: The buffer object to pin
+ *
+ * Make sure the buffer is not evicted any more during memory pressure.
+ */
+static inline void ttm_bo_pin(struct ttm_buffer_object *bo)
+{
+   dma_resv_assert_held(bo->base.resv);
+   ++bo->pin_count;
+}
+
+/**
+ * ttm_bo_unpin - Unpin the buffer object.
+ * @bo: The buffer object to unpin
+ *
+ * Allows the buffer object to be evicted again during memory pressure.
+ */
+static inline void ttm_bo_unpin(struct ttm_buffer_object *bo)
+{
+   dma_resv_assert_held(bo->base.resv);
+   WARN_ON_ONCE(!bo->pin_count);
+   --bo->pin_count;
+}
+
 int ttm_mem_evict_first(struct ttm_bo_device *bdev,
struct ttm_resource_manager *man,
const struct ttm_place *place,
-- 
2.17.1

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[PATCH 05/11] drm/nouveau: switch over to the new pin interface

[Christian König]

Stop using TTM_PL_FLAG_NO_EVICT.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/nouveau/nouveau_bo.c   | 48 +++---
 drivers/gpu/drm/nouveau/nouveau_bo.h   |  3 --
 drivers/gpu/drm/nouveau/nouveau_chan.c |  2 +-
 3 files changed, 13 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 2ee75646ad6f..bcae4514952f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -139,7 +139,7 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
struct drm_device *dev = drm->dev;
struct nouveau_bo *nvbo = nouveau_bo(bo);
 
-   WARN_ON(nvbo->pin_refcnt > 0);
+   WARN_ON(nvbo->bo.pin_count > 0);
nouveau_bo_del_io_reserve_lru(bo);
nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 
@@ -417,9 +417,8 @@ nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t 
domain,
 {
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
struct ttm_placement *pl = >placement;
-   uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
-TTM_PL_MASK_CACHING) |
-(nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
+   uint32_t flags = nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
+   TTM_PL_MASK_CACHING;
 
pl->placement = nvbo->placements;
set_placement_list(drm, nvbo->placements, >num_placement,
@@ -453,7 +452,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, 
bool contig)
}
}
 
-   if (nvbo->pin_refcnt) {
+   if (nvbo->bo.pin_count) {
bool error = evict;
 
switch (bo->mem.mem_type) {
@@ -472,7 +471,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, 
bool contig)
 bo->mem.mem_type, domain);
ret = -EBUSY;
}
-   nvbo->pin_refcnt++;
+   ttm_bo_pin(>bo);
goto out;
}
 
@@ -483,18 +482,12 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, 
bool contig)
goto out;
}
 
-   nvbo->pin_refcnt++;
nouveau_bo_placement_set(nvbo, domain, 0);
-
-   /* drop pin_refcnt temporarily, so we don't trip the assertion
-* in nouveau_bo_move() that makes sure we're not trying to
-* move a pinned buffer
-*/
-   nvbo->pin_refcnt--;
ret = nouveau_bo_validate(nvbo, false, false);
if (ret)
goto out;
-   nvbo->pin_refcnt++;
+
+   ttm_bo_pin(>bo);
 
switch (bo->mem.mem_type) {
case TTM_PL_VRAM:
@@ -519,30 +512,14 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo)
 {
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
struct ttm_buffer_object *bo = >bo;
-   int ret, ref;
+   int ret;
 
ret = ttm_bo_reserve(bo, false, false, NULL);
if (ret)
return ret;
 
-   ref = --nvbo->pin_refcnt;
-   WARN_ON_ONCE(ref < 0);
-   if (ref)
-   goto out;
-
-   switch (bo->mem.mem_type) {
-   case TTM_PL_VRAM:
-   nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
-   break;
-   case TTM_PL_TT:
-   nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
-   break;
-   default:
-   break;
-   }
-
-   ret = nouveau_bo_validate(nvbo, false, false);
-   if (ret == 0) {
+   ttm_bo_unpin(>bo);
+   if (!nvbo->bo.pin_count) {
switch (bo->mem.mem_type) {
case TTM_PL_VRAM:
drm->gem.vram_available += bo->mem.size;
@@ -555,9 +532,8 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo)
}
}
 
-out:
ttm_bo_unreserve(bo);
-   return ret;
+   return 0;
 }
 
 int
@@ -1065,7 +1041,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
if (ret)
return ret;
 
-   if (nvbo->pin_refcnt)
+   if (nvbo->bo.pin_count)
NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
 
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h 
b/drivers/gpu/drm/nouveau/nouveau_bo.h
index 2a23c8207436..ff68ded8d590 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@ -40,9 +40,6 @@ struct nouveau_bo {
 
struct nouveau_drm_tile *tile;
 
-   /* protect by the ttm reservation lock */
-   int pin_refcnt;
-
struct ttm_bo_kmap_obj dma_buf_vmap;
 };
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c 
b/drivers/gpu/drm/nouveau/nouveau_chan.c
index 8f099601d2f2..5d191e58edf1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -107,7 +107,7 @@ nouveau_channel_del(struct 

Re: [PATCH umr] Fix register name lookup for sdma POLL_REGMEM packet

[StDenis, Tom]

[AMD Official Use Only - Internal Distribution Only]

Hi Xiaojie,

I've pushed your patch out to main.  In reviewing the SDMA opcode I actually 
noticed a couple of other minor things to fix up so I've pushed that out too.

Cheers,
Tom


From: Yuan, Xiaojie 
Sent: Monday, September 21, 2020 23:02
To: amd-gfx@lists.freedesktop.org; StDenis, Tom
Cc: Yuan, Xiaojie
Subject: [PATCH umr] Fix register name lookup for sdma POLL_REGMEM packet

POLL_REGMEM_ADDR_LO/HI are in byte but umr_reg_name() expects register address 
in dword

Signed-off-by: Xiaojie Yuan 
---
 src/lib/ring_decode.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index a74229d..b5838d1 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -1904,10 +1904,10 @@ static void parse_next_sdma_pkt(struct umr_asic *asic, 
struct umr_ring_decoder *
case 0: // WAIT_REG_MEM
switch (decoder->sdma.cur_word) {
case 1: 
printf("POLL_REGMEM_ADDR_LO: %s0x%08lx%s", YELLOW, (unsigned long)ib, RST);
-   if 
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic, 
ib));
+   if 
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic, ib 
>> 2));
break;
case 2: 
printf("POLL_REGMEM_ADDR_HI: %s0x%08lx%s", YELLOW, (unsigned long)ib, RST);
-   if 
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic, 
ib));
+   if 
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic, ib 
>> 2));
break;
case 3: 
printf("POLL_REGMEM_ADDR_VALUE: %s0x%08lx%s", BLUE, (unsigned long)ib, RST);
break;
--
2.20.1

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[PATCH] gpu/drm/radeon: fix spellint typo in comments

[Wang Qing]

Modify the comment typo: "definately" -> "definitely".

Signed-off-by: Wang Qing 
---
 drivers/gpu/drm/radeon/radeon_vm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
b/drivers/gpu/drm/radeon/radeon_vm.c
index f60fae0..3d6e2cd
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -188,7 +188,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device 
*rdev,
vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
return NULL;
 
-   /* we definately need to flush */
+   /* we definitely need to flush */
vm_id->pd_gpu_addr = ~0ll;
 
/* skip over VMID 0, since it is the system VM */
-- 
2.7.4

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[PATCH] drm/radeon:fix typoes in comments

[Bernard Zhao]

Change the comment typo: "programm" -> "program".

Signed-off-by: Bernard Zhao 
---
 drivers/gpu/drm/radeon/uvd_v1_0.c | 4 ++--
 drivers/gpu/drm/radeon/uvd_v2_2.c | 2 +-
 drivers/gpu/drm/radeon/uvd_v4_2.c | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c 
b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 800721153d51..58557c2263a7 100644
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -117,7 +117,7 @@ int uvd_v1_0_resume(struct radeon_device *rdev)
if (r)
return r;
 
-   /* programm the VCPU memory controller bits 0-27 */
+   /* program the VCPU memory controller bits 0-27 */
addr = (rdev->uvd.gpu_addr >> 3) + 16;
size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;
WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
@@ -360,7 +360,7 @@ int uvd_v1_0_start(struct radeon_device *rdev)
/* Set the write pointer delay */
WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
 
-   /* programm the 4GB memory segment for rptr and ring buffer */
+   /* program the 4GB memory segment for rptr and ring buffer */
WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
   (0x7 << 16) | (0x1 << 31));
 
diff --git a/drivers/gpu/drm/radeon/uvd_v2_2.c 
b/drivers/gpu/drm/radeon/uvd_v2_2.c
index 23b18edda20e..6266167886d9 100644
--- a/drivers/gpu/drm/radeon/uvd_v2_2.c
+++ b/drivers/gpu/drm/radeon/uvd_v2_2.c
@@ -109,7 +109,7 @@ int uvd_v2_2_resume(struct radeon_device *rdev)
if (r)
return r;
 
-   /* programm the VCPU memory controller bits 0-27 */
+   /* program the VCPU memory controller bits 0-27 */
addr = rdev->uvd.gpu_addr >> 3;
size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
diff --git a/drivers/gpu/drm/radeon/uvd_v4_2.c 
b/drivers/gpu/drm/radeon/uvd_v4_2.c
index dc54fa4aaea8..f9e97fa63674 100644
--- a/drivers/gpu/drm/radeon/uvd_v4_2.c
+++ b/drivers/gpu/drm/radeon/uvd_v4_2.c
@@ -40,7 +40,7 @@ int uvd_v4_2_resume(struct radeon_device *rdev)
uint64_t addr;
uint32_t size;
 
-   /* programm the VCPU memory controller bits 0-27 */
+   /* program the VCPU memory controller bits 0-27 */
 
/* skip over the header of the new firmware format */
if (rdev->uvd.fw_header_present)
-- 
2.28.0

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[PATCH] drm/amd:fix typoes in comments

[Bernard Zhao]

Change the comment typo: "programm" -> "program".

Signed-off-by: Bernard Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  | 4 ++--
 8 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 770025a5e500..7c46937c1c0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -98,7 +98,7 @@ struct amdgpu_bo_list_entry;
 #define AMDGPU_PTE_MTYPE_NV10(a)   ((uint64_t)(a) << 48)
 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
 
-/* How to programm VM fault handling */
+/* How to program VM fault handling */
 #define AMDGPU_VM_FAULT_STOP_NEVER 0
 #define AMDGPU_VM_FAULT_STOP_FIRST 1
 #define AMDGPU_VM_FAULT_STOP_ALWAYS2
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 3cafba726587..b0c0c438fc93 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -348,7 +348,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
/* Set the write pointer delay */
WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 
-   /* programm the 4GB memory segment for rptr and ring buffer */
+   /* program the 4GB memory segment for rptr and ring buffer */
WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
   (0x7 << 16) | (0x1 << 31));
 
@@ -541,7 +541,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
uint64_t addr;
uint32_t size;
 
-   /* programm the VCPU memory controller bits 0-27 */
+   /* program the VCPU memory controller bits 0-27 */
addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index a566ff926e90..6e57001f6d0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -253,7 +253,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
uint64_t offset;
uint32_t size;
 
-   /* programm memory controller bits 0-27 */
+   /* program memory controller bits 0-27 */
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
lower_32_bits(adev->uvd.inst->gpu_addr));
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -404,7 +404,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
/* set the wb address */
WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 
-   /* programm the RB_BASE for ring buffer */
+   /* program the RB_BASE for ring buffer */
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 0a880bc101b8..d2d90fe5c6f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -583,7 +583,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
uint64_t offset;
uint32_t size;
 
-   /* programm memory controller bits 0-27 */
+   /* program memory controller bits 0-27 */
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
lower_32_bits(adev->uvd.inst->gpu_addr));
WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -825,7 +825,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
/* set the wb address */
WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 
-   /* programm the RB_BASE for ring buffer */
+   /* program the RB_BASE for ring buffer */
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index e07e3fae99b5..b44c8677ce8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1073,7 +1073,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
(upper_32_bits(ring->gpu_addr) >> 2));
 
-   /* programm the RB_BASE for ring buffer */
+   /* program the RB_BASE for ring buffer */
WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

Re: [PATCH] drm/amdgpu: Add uid info to process BO list

[Christian König]

Am 22.09.20 um 12:38 schrieb Chauhan, Madhav:

[AMD Public Use]

-Original Message-
From: Koenig, Christian 
Sent: Tuesday, September 22, 2020 12:15 PM
To: Chauhan, Madhav ; amd-gfx@lists.freedesktop.org
Cc: Surampalli, Kishore ; Patel, Mihir ; Sharma, 
Shashank ; Deucher, Alexander ; Saleem, Athar 

Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list

Am 21.09.20 um 21:55 schrieb Chauhan, Madhav:

[AMD Public Use]

-Original Message-
From: Christian König 
Sent: Tuesday, September 22, 2020 12:54 AM
To: Chauhan, Madhav ;
amd-gfx@lists.freedesktop.org
Cc: Surampalli, Kishore ; Patel, Mihir
; Sharma, Shashank ;
Deucher, Alexander ; Saleem, Athar

Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list

Am 21.09.20 um 21:18 schrieb Madhav Chauhan:

UID is helpful while doing analysis of BO allocated by a process.

Looks like a bit overkill to me, why not get the uid from the process info?

Not sure if I got your point , but used the similar method implemented
at drm level inside drm_debugfs.c. Thanks

Good argument, but I'm not sure if we should duplicate that here. What do you 
need this for?

Thanks, We need details of BOs allocated by a process and associated UID so 
that we can do memory perf analysis using some scripts
To find the top consumer of GPU memory and see if those application can be 
optimized.

Clients information at DRM level doesn’t print list of BO per process and since 
that is handled by amdgpu driver specific
Functions.  So all the BO list information at one place is really useful and 
needed by our customers as various other vendors
Already provide this.


Well that is exactly the explanation I didn't want to hear :(

See both the drm client list as well as the amdgpu GEM info are only 
debugfs files and only intended for providing some information for 
debugging and are not 100% reliable for the use case you have here.


The first problem is that on modern installations the file descriptor is 
often opened by the X server instead of the application.


So for example you end up with:

pid 1382 command Xorg:
    0x0001:  2097152 byte VRAM @ 0x002a00
    0x0002: 4096 byte  GTT @ 0x0006c7

    0x0090:   266240 byte VRAM @ 0x05e800
    0x0091:  2097152 byte VRAM @ 0x04e200
    0x0092:  2097152 byte  GTT
pid 1382 command Xorg:
    0x0001:  2097152 byte VRAM @ 0x002800
...


Then next problem is that the amdgpu_gem_info is completely inaccurate 
regarding the used memory of an application, since the same BO is 
sometimes opened multiple times. That's also the reason why we don't 
provide a total of the consumed memory. It basically just informs you 
which handle is what.


Then last the debugfs files are not a stable interface and not meant to 
be consumed by scripts and/or frontend applications. You should instead 
use sysfs for this.


Regards,
Christian.



Regards,
Madhav

Christian.


Regards,
Madhav

Christian.


Signed-off-by: Madhav Chauhan 
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index f4c2e2e75b8f..c1982349ec7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void 
*data)
struct drm_info_node *node = (struct drm_info_node *)m->private;
struct drm_device *dev = node->minor->dev;
struct drm_file *file;
+   kuid_t uid;
int r;

	r = mutex_lock_interruptible(>filelist_mutex);

@@ -909,7 +910,10 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, 
void *data)
 */
rcu_read_lock();
task = pid_task(file->pid, PIDTYPE_PID);
-   seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
+   uid = task ? __task_cred(task)->euid : GLOBAL_ROOT_UID;
+   seq_printf(m, "pid %8d uid %5d command %s:\n",
+  pid_nr(file->pid),
+  from_kuid_munged(seq_user_ns(m), uid),
   task ? task->comm : "");
rcu_read_unlock();


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RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[Zhang, Hawking]

[AMD Public Use]


[AMD Public Use]

Hi @Chen, JingWen,

CAP firmware will be only used for SRIOV. So please just add specific code path 
under SRIOV to initialize that firmware. Do not introduce SRIOV specific code 
for the most PSP firmware you are not used in guest.

Regards,
Hawking

From: Chen, JingWen 
Sent: Tuesday, September 22, 2020 18:27
To: Deng, Emily ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV


[AMD Public Use]


[AMD Public Use]

Hi Hawking,

We may need other features in PSP in the future, e.g. load cap fw. So we can't 
skip the whole psp_init_microcode.

Best Regards,
JingWen Chen

From: Deng, Emily mailto:emily.d...@amd.com>>
Sent: Tuesday, September 22, 2020 6:22 PM
To: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>; Zhang, 
Hawking mailto:hawking.zh...@amd.com>>; Chen, JingWen 
mailto:jingwen.ch...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV


[AMD Public Use]

Hi Kevin and Hawking,
I think both you are right. But currently we haven't good method to handle 
this. It seems need to re-arch the whole driver, not only refer to this patch. 
Only refer to this patch, I think it is OK.

Best wishes
Emily Deng
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Wang, Kevin(Yang)
Sent: Tuesday, September 22, 2020 3:38 PM
To: Zhang, Hawking mailto:hawking.zh...@amd.com>>; Chen, 
JingWen mailto:jingwen.ch...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV


[AMD Public Use]


[AMD Public Use]

Embedding these SRIOV check into the underlying functions is in many places, 
which is not conducive to subsequent code optimization and maintenance.
It took a long time to clean up the SMU code before, but now some new checks 
have been introduced into the SMU code.
I think a new method should be adopted to solve this problem unless there's a 
special reason.

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Zhang, Hawking 
mailto:hawking.zh...@amd.com>>
Sent: Tuesday, September 22, 2020 3:25 PM
To: Chen, JingWen mailto:jingwen.ch...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Chen, JingWen mailto:jingwen.ch...@amd.com>>
Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[AMD Public Use]

1. Please do not add the amdgpu_sriov_vf check in every psp fw init_microcode 
function. psp_init_microcode is the entry point for all kinds of psp fw 
microcode initialization.
2. I'd like to get a whole picture on all the sequence you want to skip from 
guest side so that we can have more organized/reasonable approach to exclude 
those programing sequence for SRIOV, instead of having the amdgpu_sriov_vf 
patched case by case...

Regards,
Hawking

-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Jingwen Chen
Sent: Tuesday, September 22, 2020 15:09
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen mailto:jingwen.ch...@amd.com>>
Subject: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate 
sw_init for navi12.

v2: skip above fw in SRIOV for vega10 and sienna_cichlid
Signed-off-by: Jingwen Chen 
mailto:jingwen.ch...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  |  9 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   |  3 +++
 .../gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c  | 12 +++-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 11 +++
 6 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2c66e20b2ed9..9e2038de6ea7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2385,6 +2385,9 @@ int psp_init_asd_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_0 *asd_hdr;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for asd microcode\n");
 return -EINVAL;
@@ -2424,6 +2427,9 @@ int psp_init_sos_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
  

RE: [PATCH] drm/amdgpu: Add uid info to process BO list

[Chauhan, Madhav]

[AMD Public Use]

-Original Message-
From: Koenig, Christian  
Sent: Tuesday, September 22, 2020 12:15 PM
To: Chauhan, Madhav ; amd-gfx@lists.freedesktop.org
Cc: Surampalli, Kishore ; Patel, Mihir 
; Sharma, Shashank ; Deucher, 
Alexander ; Saleem, Athar 
Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list

Am 21.09.20 um 21:55 schrieb Chauhan, Madhav:
> [AMD Public Use]
>
> -Original Message-
> From: Christian König 
> Sent: Tuesday, September 22, 2020 12:54 AM
> To: Chauhan, Madhav ; 
> amd-gfx@lists.freedesktop.org
> Cc: Surampalli, Kishore ; Patel, Mihir 
> ; Sharma, Shashank ; 
> Deucher, Alexander ; Saleem, Athar 
> 
> Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list
>
> Am 21.09.20 um 21:18 schrieb Madhav Chauhan:
>> UID is helpful while doing analysis of BO allocated by a process.
> Looks like a bit overkill to me, why not get the uid from the process info?
>
> Not sure if I got your point , but used the similar method implemented 
> at drm level inside drm_debugfs.c. Thanks

Good argument, but I'm not sure if we should duplicate that here. What do you 
need this for?

Thanks, We need details of BOs allocated by a process and associated UID so 
that we can do memory perf analysis using some scripts
To find the top consumer of GPU memory and see if those application can be 
optimized. 

Clients information at DRM level doesn’t print list of BO per process and since 
that is handled by amdgpu driver specific
Functions.  So all the BO list information at one place is really useful and 
needed by our customers as various other vendors
Already provide this.

Regards,
Madhav

Christian.

>
> Regards,
> Madhav
>
> Christian.
>
>> Signed-off-by: Madhav Chauhan 
>> ---
>>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-
>>1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> index f4c2e2e75b8f..c1982349ec7b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> @@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, 
>> void *data)
>>  struct drm_info_node *node = (struct drm_info_node *)m->private;
>>  struct drm_device *dev = node->minor->dev;
>>  struct drm_file *file;
>> +kuid_t uid;
>>  int r;
>>
>>  r = mutex_lock_interruptible(>filelist_mutex);
>> @@ -909,7 +910,10 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, 
>> void *data)
>>   */
>>  rcu_read_lock();
>>  task = pid_task(file->pid, PIDTYPE_PID);
>> -seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
>> +uid = task ? __task_cred(task)->euid : GLOBAL_ROOT_UID;
>> +seq_printf(m, "pid %8d uid %5d command %s:\n",
>> +   pid_nr(file->pid),
>> +   from_kuid_munged(seq_user_ns(m), uid),
>> task ? task->comm : "");
>>  rcu_read_unlock();
>>
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RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[Chen, JingWen]

[AMD Public Use]


[AMD Public Use]

Hi Hawking,

We may need other features in PSP in the future, e.g. load cap fw. So we can't 
skip the whole psp_init_microcode.

Best Regards,
JingWen Chen

From: Deng, Emily 
Sent: Tuesday, September 22, 2020 6:22 PM
To: Wang, Kevin(Yang) ; Zhang, Hawking 
; Chen, JingWen ; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV


[AMD Public Use]

Hi Kevin and Hawking,
I think both you are right. But currently we haven't good method to handle 
this. It seems need to re-arch the whole driver, not only refer to this patch. 
Only refer to this patch, I think it is OK.

Best wishes
Emily Deng
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Wang, Kevin(Yang)
Sent: Tuesday, September 22, 2020 3:38 PM
To: Zhang, Hawking mailto:hawking.zh...@amd.com>>; Chen, 
JingWen mailto:jingwen.ch...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV


[AMD Public Use]


[AMD Public Use]

Embedding these SRIOV check into the underlying functions is in many places, 
which is not conducive to subsequent code optimization and maintenance.
It took a long time to clean up the SMU code before, but now some new checks 
have been introduced into the SMU code.
I think a new method should be adopted to solve this problem unless there's a 
special reason.

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Zhang, Hawking 
mailto:hawking.zh...@amd.com>>
Sent: Tuesday, September 22, 2020 3:25 PM
To: Chen, JingWen mailto:jingwen.ch...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Chen, JingWen mailto:jingwen.ch...@amd.com>>
Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[AMD Public Use]

1. Please do not add the amdgpu_sriov_vf check in every psp fw init_microcode 
function. psp_init_microcode is the entry point for all kinds of psp fw 
microcode initialization.
2. I'd like to get a whole picture on all the sequence you want to skip from 
guest side so that we can have more organized/reasonable approach to exclude 
those programing sequence for SRIOV, instead of having the amdgpu_sriov_vf 
patched case by case...

Regards,
Hawking

-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Jingwen Chen
Sent: Tuesday, September 22, 2020 15:09
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen mailto:jingwen.ch...@amd.com>>
Subject: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate 
sw_init for navi12.

v2: skip above fw in SRIOV for vega10 and sienna_cichlid
Signed-off-by: Jingwen Chen 
mailto:jingwen.ch...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  |  9 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   |  3 +++
 .../gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c  | 12 +++-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 11 +++
 6 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2c66e20b2ed9..9e2038de6ea7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2385,6 +2385,9 @@ int psp_init_asd_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_0 *asd_hdr;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for asd microcode\n");
 return -EINVAL;
@@ -2424,6 +2427,9 @@ int psp_init_sos_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for sos microcode\n");
 return -EINVAL;
@@ -2558,6 +2564,9 @@ int psp_init_ta_microcode(struct psp_context *psp,
 int err = 0;
 int ta_index = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for ta microcode\n");
 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 810635cbf4c1..86fb1eddf5a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -592,6 +592,9 @@ static int 

RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[Deng, Emily]

[AMD Public Use]

Hi Kevin and Hawking,
I think both you are right. But currently we haven't good method to handle 
this. It seems need to re-arch the whole driver, not only refer to this patch. 
Only refer to this patch, I think it is OK.

Best wishes
Emily Deng
From: amd-gfx  On Behalf Of Wang, 
Kevin(Yang)
Sent: Tuesday, September 22, 2020 3:38 PM
To: Zhang, Hawking ; Chen, JingWen 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV


[AMD Public Use]


[AMD Public Use]

Embedding these SRIOV check into the underlying functions is in many places, 
which is not conducive to subsequent code optimization and maintenance.
It took a long time to clean up the SMU code before, but now some new checks 
have been introduced into the SMU code.
I think a new method should be adopted to solve this problem unless there's a 
special reason.

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Zhang, Hawking 
mailto:hawking.zh...@amd.com>>
Sent: Tuesday, September 22, 2020 3:25 PM
To: Chen, JingWen mailto:jingwen.ch...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Chen, JingWen mailto:jingwen.ch...@amd.com>>
Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[AMD Public Use]

1. Please do not add the amdgpu_sriov_vf check in every psp fw init_microcode 
function. psp_init_microcode is the entry point for all kinds of psp fw 
microcode initialization.
2. I'd like to get a whole picture on all the sequence you want to skip from 
guest side so that we can have more organized/reasonable approach to exclude 
those programing sequence for SRIOV, instead of having the amdgpu_sriov_vf 
patched case by case...

Regards,
Hawking

-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Jingwen Chen
Sent: Tuesday, September 22, 2020 15:09
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen mailto:jingwen.ch...@amd.com>>
Subject: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate 
sw_init for navi12.

v2: skip above fw in SRIOV for vega10 and sienna_cichlid
Signed-off-by: Jingwen Chen 
mailto:jingwen.ch...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  |  9 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   |  3 +++
 .../gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c  | 12 +++-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 11 +++
 6 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2c66e20b2ed9..9e2038de6ea7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2385,6 +2385,9 @@ int psp_init_asd_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_0 *asd_hdr;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for asd microcode\n");
 return -EINVAL;
@@ -2424,6 +2427,9 @@ int psp_init_sos_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for sos microcode\n");
 return -EINVAL;
@@ -2558,6 +2564,9 @@ int psp_init_ta_microcode(struct psp_context *psp,
 int err = 0;
 int ta_index = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for ta microcode\n");
 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 810635cbf4c1..86fb1eddf5a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -592,6 +592,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device 
*adev)
 struct amdgpu_firmware_info *info = NULL;
 const struct common_firmware_header *header = NULL;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 DRM_DEBUG("\n");

 switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 48c95a78a173..9c72b95b7463 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -203,6 +203,9 @@ static int sdma_v5_0_init_microcode(struct 

RE: [PATCH 1/1] drm/amdgpu: fix hdp register access error

[Zhang, Hawking]

[AMD Public Use]

Thanks.

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Stanley.Yang  
Sent: Tuesday, September 22, 2020 17:10
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Yang, Stanley 
Subject: [PATCH 1/1] drm/amdgpu: fix hdp register access error

mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO

Signed-off-by: Stanley.Yang 
Change-Id: I4375a8a67d3a13f9605479e169169e22dd5833d1
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index 0ec66030bd11..bc894cfba60c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -621,7 +621,7 @@ static void nv_invalidate_hdp(struct amdgpu_device *adev,
struct amdgpu_ring *ring)
 {
if (!ring || !ring->funcs->emit_wreg) {
-   WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
+   WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
} else {
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 
1);
--
2.17.1
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[PATCH 1/1] drm/amdgpu: fix hdp register access error

[Stanley . Yang]

mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO

Signed-off-by: Stanley.Yang 
Change-Id: I4375a8a67d3a13f9605479e169169e22dd5833d1
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 0ec66030bd11..bc894cfba60c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -621,7 +621,7 @@ static void nv_invalidate_hdp(struct amdgpu_device *adev,
struct amdgpu_ring *ring)
 {
if (!ring || !ring->funcs->emit_wreg) {
-   WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
+   WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
} else {
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 
1);
-- 
2.17.1

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[PATCH] drm/amd/display: Simplify condition in try_disable_dsc

[Nathan Chancellor]

Clang warns:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c:637:8:
warning: logical not is only applied to the left hand side of this
comparison [-Wlogical-not-parentheses]
&& !params[i].clock_force_enable == 
DSC_CLK_FORCE_DEFAULT) {
   ^ ~~
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c:637:8:
note: add parentheses after the '!' to evaluate the comparison first
&& !params[i].clock_force_enable == 
DSC_CLK_FORCE_DEFAULT) {
   ^
(
)
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c:637:8:
note: add parentheses around left hand side expression to silence this
warning
&& !params[i].clock_force_enable == 
DSC_CLK_FORCE_DEFAULT) {
   ^
   ()
1 warning generated.

The expression "!a == 0" can be more simply written as "a", which makes
it easier to reason about the logic and prevents the warning.

Fixes: 0749ddeb7d6c ("drm/amd/display: Add DSC force disable to dsc_clock_en 
debugfs entry")
Link: https://github.com/ClangBuiltLinux/linux/issues/1158
Signed-off-by: Nathan Chancellor 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9d7333a36fac..0852a24ee392 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -634,7 +634,7 @@ static void try_disable_dsc(struct drm_atomic_state *state,
for (i = 0; i < count; i++) {
if (vars[i].dsc_enabled
&& vars[i].bpp_x16 == 
params[i].bw_range.max_target_bpp_x16
-   && !params[i].clock_force_enable == 
DSC_CLK_FORCE_DEFAULT) {
+   && params[i].clock_force_enable) {
kbps_increase[i] = params[i].bw_range.stream_kbps - 
params[i].bw_range.max_kbps;
tried[i] = false;
remaining_to_try += 1;

base-commit: 6651cdf3bfeeaeb499db11668313666bf756579a
-- 
2.28.0

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Re:Re: [PATCH] drm/amd/display: optimize code runtime a bit

[Bernard]

From: Alex Deucher 
Date: 2020-09-22 03:33:20
To:  Bernard Zhao 
Cc:  Harry Wentland ,Leo Li ,Alex 
Deucher ,"Christian König" 
,David Airlie ,Daniel Vetter 
,Rodrigo Siqueira ,Jun Lei 
,Aric Cyr ,Wenjing Liu 
,abdoulaye berthe ,Michael 
Strauss ,Brandon Syu ,Martin 
Leung ,amd-gfx list 
,Maling list - DRI developers 
,LKML 
,opensource.ker...@vivo.com
Subject: Re: [PATCH] drm/amd/display: optimize code runtime a bit>On Mon, Sep 
21, 2020 at 9:14 AM Bernard Zhao  wrote:
>>
>> Static function dal_ddc_i2c_payloads_destroy is only called
>> in dal_ddc_service_query_ddc_data, the parameter is 
>> , there is no point NULL risk, so no need to check.
>> This change is to make the code run a bit fast.
>>
>
>How about just getting rid of dal_ddc_i2c_payloads_destroy() and just
>call dal_vector_destruct() directly.

Good idea, I will resubmit a patch, thanks!

BR//Bernard

>Alex
>
>
>> Signed-off-by: Bernard Zhao 
>> ---
>>  drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 3 ---
>>  1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
>> index b984eecca58b..6dcc666738fc 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
>> @@ -150,9 +150,6 @@ static uint32_t dal_ddc_i2c_payloads_get_count(struct 
>> i2c_payloads *p)
>>
>>  static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads *p)
>>  {
>> -   if (!p)
>> -   return;
>> -
>> dal_vector_destruct(>payloads);
>>  }
>>
>> --
>> 2.28.0
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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[PATCH v2] drm/amd/display: optimize code runtime a bit

[Bernard Zhao]

In the function dal_ddc_service_query_ddc_data,
get rid of dal_ddc_i2c_payloads_destroy, call
dal_vector_destruct() directly.
This change is to make the code run a bit fast.

Signed-off-by: Bernard Zhao 
Changes since V1:
*get rid of dal_ddc_i2c_payloads_destroy, call
dal_vector_destruct() directly.

Link for V1:
*https://lore.kernel.org/patchwork/patch/1309014/
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 10 +-
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index b984eecca58b..dec12de37642 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -148,14 +148,6 @@ static uint32_t dal_ddc_i2c_payloads_get_count(struct 
i2c_payloads *p)
return p->payloads.count;
 }
 
-static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads *p)
-{
-   if (!p)
-   return;
-
-   dal_vector_destruct(>payloads);
-}
-
 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
 
 void dal_ddc_i2c_payloads_add(
@@ -582,7 +574,7 @@ bool dal_ddc_service_query_ddc_data(
ddc->link,
);
 
-   dal_ddc_i2c_payloads_destroy();
+   dal_vector_destruct();
}
 
return success;
-- 
2.28.0

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Re: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[Wang, Kevin(Yang)]

[AMD Public Use]

Embedding these SRIOV check into the underlying functions is in many places, 
which is not conducive to subsequent code optimization and maintenance.
It took a long time to clean up the SMU code before, but now some new checks 
have been introduced into the SMU code.
I think a new method should be adopted to solve this problem unless there's a 
special reason.

Best Regards,
Kevin

From: amd-gfx  on behalf of Zhang, 
Hawking 
Sent: Tuesday, September 22, 2020 3:25 PM
To: Chen, JingWen ; amd-gfx@lists.freedesktop.org 

Cc: Chen, JingWen 
Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[AMD Public Use]

1. Please do not add the amdgpu_sriov_vf check in every psp fw init_microcode 
function. psp_init_microcode is the entry point for all kinds of psp fw 
microcode initialization.
2. I'd like to get a whole picture on all the sequence you want to skip from 
guest side so that we can have more organized/reasonable approach to exclude 
those programing sequence for SRIOV, instead of having the amdgpu_sriov_vf 
patched case by case...

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Jingwen Chen
Sent: Tuesday, September 22, 2020 15:09
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen 
Subject: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate 
sw_init for navi12.

v2: skip above fw in SRIOV for vega10 and sienna_cichlid
Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  |  9 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   |  3 +++
 .../gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c  | 12 +++-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 11 +++
 6 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2c66e20b2ed9..9e2038de6ea7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2385,6 +2385,9 @@ int psp_init_asd_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_0 *asd_hdr;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for asd microcode\n");
 return -EINVAL;
@@ -2424,6 +2427,9 @@ int psp_init_sos_microcode(struct psp_context *psp,
 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
 int err = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for sos microcode\n");
 return -EINVAL;
@@ -2558,6 +2564,9 @@ int psp_init_ta_microcode(struct psp_context *psp,
 int err = 0;
 int ta_index = 0;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 if (!chip_name) {
 dev_err(adev->dev, "invalid chip name for ta microcode\n");
 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 810635cbf4c1..86fb1eddf5a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -592,6 +592,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device 
*adev)
 struct amdgpu_firmware_info *info = NULL;
 const struct common_firmware_header *header = NULL;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 DRM_DEBUG("\n");

 switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 48c95a78a173..9c72b95b7463 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -203,6 +203,9 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device 
*adev)
 const struct common_firmware_header *header = NULL;
 const struct sdma_firmware_header_v1_0 *hdr;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 DRM_DEBUG("\n");

 switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 34ccf376ee45..9f3952723c63 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -148,6 +148,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device 
*adev)
 struct amdgpu_firmware_info *info = NULL;
 const struct common_firmware_header *header = NULL;

+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
 DRM_DEBUG("\n");

 switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c 

RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[Zhang, Hawking]

[AMD Public Use]

1. Please do not add the amdgpu_sriov_vf check in every psp fw init_microcode 
function. psp_init_microcode is the entry point for all kinds of psp fw 
microcode initialization.
2. I'd like to get a whole picture on all the sequence you want to skip from 
guest side so that we can have more organized/reasonable approach to exclude 
those programing sequence for SRIOV, instead of having the amdgpu_sriov_vf 
patched case by case...

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Jingwen Chen
Sent: Tuesday, September 22, 2020 15:09
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen 
Subject: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate 
sw_init for navi12.

v2: skip above fw in SRIOV for vega10 and sienna_cichlid
Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  |  9 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   |  3 +++
 .../gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c  | 12 +++-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 11 +++
 6 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2c66e20b2ed9..9e2038de6ea7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2385,6 +2385,9 @@ int psp_init_asd_microcode(struct psp_context *psp,
const struct psp_firmware_header_v1_0 *asd_hdr;
int err = 0;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
if (!chip_name) {
dev_err(adev->dev, "invalid chip name for asd microcode\n");
return -EINVAL;
@@ -2424,6 +2427,9 @@ int psp_init_sos_microcode(struct psp_context *psp,
const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
int err = 0;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
if (!chip_name) {
dev_err(adev->dev, "invalid chip name for sos microcode\n");
return -EINVAL;
@@ -2558,6 +2564,9 @@ int psp_init_ta_microcode(struct psp_context *psp,
int err = 0;
int ta_index = 0;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
if (!chip_name) {
dev_err(adev->dev, "invalid chip name for ta microcode\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 810635cbf4c1..86fb1eddf5a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -592,6 +592,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device 
*adev)
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
DRM_DEBUG("\n");
 
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 48c95a78a173..9c72b95b7463 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -203,6 +203,9 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device 
*adev)
const struct common_firmware_header *header = NULL;
const struct sdma_firmware_header_v1_0 *hdr;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
DRM_DEBUG("\n");
 
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 34ccf376ee45..9f3952723c63 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -148,6 +148,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device 
*adev)
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
DRM_DEBUG("\n");
 
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
index 1e222c5d91a4..daf122f24f23 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
@@ -209,11 +209,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
int ret;
struct cgs_firmware_info info = {0};
 
-   ret = cgs_get_firmware_info(hwmgr->device,
-   CGS_UCODE_ID_SMU,
-   );
-   if (ret || !info.kptr)
-   return -EINVAL;
+   if (!amdgpu_sriov_vf((struct amdgpu_device *)hwmgr->adev)) {
+   ret = 

[PATCH 1/2] drm/amd/pm: Skip use smc fw data in SRIOV

[Jingwen Chen]

smc fw is not needed in SRIOV, thus driver should not try to get smc
fw data.

Signed-off-by: Jingwen Chen 
---
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 61 ++-
 1 file changed, 32 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index b53872eb4398..d8ca6d968813 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -322,39 +322,42 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
void *table;
uint16_t version_major, version_minor;
 
-   hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
-   version_major = le16_to_cpu(hdr->header.header_version_major);
-   version_minor = le16_to_cpu(hdr->header.header_version_minor);
-   if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) 
||
-   adev->asic_type == CHIP_NAVY_FLOUNDER) {
-   dev_info(adev->dev, "use driver provided pptable %d\n", 
smu->smu_table.boot_values.pp_table_id);
-   switch (version_minor) {
-   case 0:
-   ret = smu_v11_0_set_pptable_v2_0(smu, , );
-   break;
-   case 1:
-   ret = smu_v11_0_set_pptable_v2_1(smu, , ,
-
smu->smu_table.boot_values.pp_table_id);
-   break;
-   default:
-   ret = -EINVAL;
-   break;
+   if (!amdgpu_sriov_vf(adev)) {
+   hdr = (const struct smc_firmware_header_v1_0 *) 
adev->pm.fw->data;
+   version_major = le16_to_cpu(hdr->header.header_version_major);
+   version_minor = le16_to_cpu(hdr->header.header_version_minor);
+   if ((version_major == 2 && 
smu->smu_table.boot_values.pp_table_id > 0) ||
+   adev->asic_type == CHIP_NAVY_FLOUNDER) {
+   dev_info(adev->dev, "use driver provided pptable %d\n", 
smu->smu_table.boot_values.pp_table_id);
+   switch (version_minor) {
+   case 0:
+   ret = smu_v11_0_set_pptable_v2_0(smu, , 
);
+   break;
+   case 1:
+   ret = smu_v11_0_set_pptable_v2_1(smu, , 
,
+   
smu->smu_table.boot_values.pp_table_id);
+   break;
+   default:
+   ret = -EINVAL;
+   break;
+   }
+   if (ret)
+   return ret;
+   goto out;
}
-   if (ret)
-   return ret;
+   }
 
-   } else {
-   dev_info(adev->dev, "use vbios provided pptable\n");
-   index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
-   powerplayinfo);
+   dev_info(adev->dev, "use vbios provided pptable\n");
+   index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+   powerplayinfo);
 
-   ret = amdgpu_atombios_get_data_table(adev, index, 
_table_size, , ,
- (uint8_t **));
-   if (ret)
-   return ret;
-   size = atom_table_size;
-   }
+   ret = amdgpu_atombios_get_data_table(adev, index, _table_size, 
, ,
+   (uint8_t **));
+   if (ret)
+   return ret;
+   size = atom_table_size;
 
+out:
if (!smu->smu_table.power_play_table)
smu->smu_table.power_play_table = table;
if (!smu->smu_table.power_play_table_size)
-- 
2.25.1

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[PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV

[Jingwen Chen]

smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to
accelerate sw_init for navi12.

v2: skip above fw in SRIOV for vega10 and sienna_cichlid
Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  |  9 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   |  3 +++
 .../gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c  | 12 +++-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 11 +++
 6 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2c66e20b2ed9..9e2038de6ea7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2385,6 +2385,9 @@ int psp_init_asd_microcode(struct psp_context *psp,
const struct psp_firmware_header_v1_0 *asd_hdr;
int err = 0;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
if (!chip_name) {
dev_err(adev->dev, "invalid chip name for asd microcode\n");
return -EINVAL;
@@ -2424,6 +2427,9 @@ int psp_init_sos_microcode(struct psp_context *psp,
const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
int err = 0;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
if (!chip_name) {
dev_err(adev->dev, "invalid chip name for sos microcode\n");
return -EINVAL;
@@ -2558,6 +2564,9 @@ int psp_init_ta_microcode(struct psp_context *psp,
int err = 0;
int ta_index = 0;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
if (!chip_name) {
dev_err(adev->dev, "invalid chip name for ta microcode\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 810635cbf4c1..86fb1eddf5a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -592,6 +592,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device 
*adev)
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
DRM_DEBUG("\n");
 
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 48c95a78a173..9c72b95b7463 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -203,6 +203,9 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device 
*adev)
const struct common_firmware_header *header = NULL;
const struct sdma_firmware_header_v1_0 *hdr;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
DRM_DEBUG("\n");
 
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 34ccf376ee45..9f3952723c63 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -148,6 +148,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device 
*adev)
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
DRM_DEBUG("\n");
 
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
index 1e222c5d91a4..daf122f24f23 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
@@ -209,11 +209,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
int ret;
struct cgs_firmware_info info = {0};
 
-   ret = cgs_get_firmware_info(hwmgr->device,
-   CGS_UCODE_ID_SMU,
-   );
-   if (ret || !info.kptr)
-   return -EINVAL;
+   if (!amdgpu_sriov_vf((struct amdgpu_device *)hwmgr->adev)) {
+   ret = cgs_get_firmware_info(hwmgr->device,
+   CGS_UCODE_ID_SMU,
+   );
+   if (ret || !info.kptr)
+   return -EINVAL;
+   }
 
priv = kzalloc(sizeof(struct vega10_smumgr), GFP_KERNEL);
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 538e6f5e19eb..3010cb31324a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -832,10 +832,13 @@ static int smu_sw_init(void *handle)
 
smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
smu->smu_dpm.requested_dpm_level = 

Re: [PATCH] drm/amdgpu: Add uid info to process BO list

[Christian König]

Am 21.09.20 um 21:55 schrieb Chauhan, Madhav:

[AMD Public Use]

-Original Message-
From: Christian König 
Sent: Tuesday, September 22, 2020 12:54 AM
To: Chauhan, Madhav ; amd-gfx@lists.freedesktop.org
Cc: Surampalli, Kishore ; Patel, Mihir ; Sharma, 
Shashank ; Deucher, Alexander ; Saleem, Athar 

Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list

Am 21.09.20 um 21:18 schrieb Madhav Chauhan:

UID is helpful while doing analysis of BO allocated by a process.

Looks like a bit overkill to me, why not get the uid from the process info?

Not sure if I got your point , but used the similar method implemented at drm 
level inside drm_debugfs.c. Thanks


Good argument, but I'm not sure if we should duplicate that here. What 
do you need this for?


Christian.



Regards,
Madhav

Christian.


Signed-off-by: Madhav Chauhan 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-
   1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index f4c2e2e75b8f..c1982349ec7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void 
*data)
struct drm_info_node *node = (struct drm_info_node *)m->private;
struct drm_device *dev = node->minor->dev;
struct drm_file *file;
+   kuid_t uid;
int r;
   
   	r = mutex_lock_interruptible(>filelist_mutex);

@@ -909,7 +910,10 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, 
void *data)
 */
rcu_read_lock();
task = pid_task(file->pid, PIDTYPE_PID);
-   seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
+   uid = task ? __task_cred(task)->euid : GLOBAL_ROOT_UID;
+   seq_printf(m, "pid %8d uid %5d command %s:\n",
+  pid_nr(file->pid),
+  from_kuid_munged(seq_user_ns(m), uid),
   task ? task->comm : "");
rcu_read_unlock();
   


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