Re: linux-next: Tree for Feb 24 [drivers/gpu/drm/amd/amdgpu/amdgpu.ko]
On 2/23/21 7:36 PM, Stephen Rothwell wrote: > Hi all, > > Please do not add any changes destined for v5.13 to your linux-next > included branches until after v5.12-rc1 has been released. > > Changes since 20210223: > on i386: ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__umoddi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Full randconfig file is attached. -- ~Randy Reported-by: Randy Dunlap config-r7997.gz Description: application/gzip ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Enable SDMA MGCG for Vangogh
On Wed, Feb 24, 2021 at 01:33:19PM +0800, Su, Jinzhou (Joe) wrote: > Add AMD_CG_SUPPORT_SDMA_MGCG for Vangogh > > Signed-off-by: Jinzhou Su Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/nv.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c > index 160fa5f59805..393a0d5905ab 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nv.c > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c > @@ -1003,6 +1003,7 @@ static int nv_common_early_init(void *handle) > AMD_CG_SUPPORT_MC_LS | > AMD_CG_SUPPORT_GFX_FGCG | > AMD_CG_SUPPORT_VCN_MGCG | > + AMD_CG_SUPPORT_SDMA_MGCG | > AMD_CG_SUPPORT_JPEG_MGCG; > adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | > AMD_PG_SUPPORT_VCN | > -- > 2.17.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Enable SDMA MGCG for Vangogh
[AMD Official Use Only - Internal Distribution Only] Acked-by: Alex Deucher From: amd-gfx on behalf of Jinzhou Su Sent: Wednesday, February 24, 2021 12:33 AM To: amd-gfx@lists.freedesktop.org Cc: Su, Jinzhou (Joe) ; Huang, Ray Subject: [PATCH] drm/amdgpu: Enable SDMA MGCG for Vangogh Add AMD_CG_SUPPORT_SDMA_MGCG for Vangogh Signed-off-by: Jinzhou Su --- drivers/gpu/drm/amd/amdgpu/nv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 160fa5f59805..393a0d5905ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1003,6 +1003,7 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_VCN | -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Calexander.deucher%40amd.com%7C791e8418aa8f4ff6eb5708d8d885be42%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637497416235253073%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=Ajm4v5%2FRrbMGO1%2BbUGHByfzI3%2Bb%2F8GJY7hnIt6FHzB0%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Enable SDMA MGCG for Vangogh
Add AMD_CG_SUPPORT_SDMA_MGCG for Vangogh Signed-off-by: Jinzhou Su --- drivers/gpu/drm/amd/amdgpu/nv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 160fa5f59805..393a0d5905ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1003,6 +1003,7 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_VCN | -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/ttm: Do not add non-system domain BO into swap list
[AMD Public Use]
Acked-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, February 24, 2021 11:35 AM
To: Pan, Xinhui
Cc: Deucher, Alexander ; Maling list - DRI
developers ; Koenig, Christian
; amd-gfx list
Subject: Re: [PATCH] drm/ttm: Do not add non-system domain BO into swap list
On Tue, Feb 23, 2021 at 10:28 PM xinhui pan wrote:
>
> BO would be added into swap list if it is validated into system domain.
> If BO is validated again into non-system domain, say, VRAM domain. It
> actually should not be in the swap list.
>
> Signed-off-by: xinhui pan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c
> b/drivers/gpu/drm/ttm/ttm_bo.c index a97d41f4ce3c..3a10bebb75d6 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -111,6 +111,8 @@ void ttm_bo_move_to_lru_tail(struct
> ttm_buffer_object *bo,
>
> swap = _glob.swap_lru[bo->priority];
> list_move_tail(>swap, swap);
> + } else {
> + list_del_init(>swap);
> }
>
> if (bdev->funcs->del_from_lru_notify)
> --
> 2.25.1
>
> ___
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RE: [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm functions
[AMD Public Use]
Series is reviewed-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Darren Powell
Sent: Tuesday, February 23, 2021 12:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren
Subject: [PATCH 8/8] amdgpu/pm: Powerplay API for smu , updates to some pm
functions
v3: updated to include new clocks od_vddgfx_offset, od_cclk
Context mismatch with revision v3 to patch 0003
Modified Functions
smu_sys_set_pp_table()- modifed signature to match Powerplay API
set_pp_table
smu_force_performance_level() - modifed arg0 to match Powerplay API
force_performance_level
smu_od_edit_dpm_table() - modifed arg0 to match Powerplay API
odn_edit_dpm_table
Other Changes
smu_od_edit_dpm_table() - removed call to task(READJUST_POWER_STATE)
after COMMIT_TABLE,
now handled in calling function
amdgpu_set_power_dpm_force_performance_level() - now checks thermal for swsmu
systems before trying to change level
amdgpu_set_pp_od_clk_voltage() - now attempts to set fine_grain_clock_vol
before swsmu edit dpm table
Signed-off-by: Darren Powell
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 98 +--
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 6 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 ++--
3 files changed, 48 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ec5277ed74f7..1675a5e72a0d 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -370,14 +370,7 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
return -EINVAL;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_force_performance_level(>smu, level);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
- } else if (pp_funcs->force_performance_level) {
+ if (pp_funcs->force_performance_level) {
mutex_lock(>pm.mutex);
if (adev->pm.dpm.thermal_active) {
mutex_unlock(>pm.mutex);
@@ -615,15 +608,12 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_sys_set_pp_table(>smu, (void *)buf, count);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return ret;
- }
- } else if (adev->powerplay.pp_funcs->set_pp_table)
- amdgpu_dpm_set_pp_table(adev, buf, count);
+ ret = amdgpu_dpm_set_pp_table(adev, buf, count);
+ if (ret) {
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return ret;
+ }
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -821,53 +811,42 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device
*dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_od_edit_dpm_table(>smu, type,
- parameter, parameter_size);
-
+ if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
+ ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
+ parameter,
+ parameter_size);
if (ret) {
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
return -EINVAL;
}
- } else {
-
- if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
- ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
- parameter,
- parameter_size);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
- }
- }
+ }
- if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
- ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
- parameter, parameter_size);
- if (ret) {
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- return -EINVAL;
-
Re: [PATCH] drm/ttm: Do not add non-system domain BO into swap list
On Tue, Feb 23, 2021 at 10:28 PM xinhui pan wrote:
>
> BO would be added into swap list if it is validated into system domain.
> If BO is validated again into non-system domain, say, VRAM domain. It
> actually should not be in the swap list.
>
> Signed-off-by: xinhui pan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> index a97d41f4ce3c..3a10bebb75d6 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -111,6 +111,8 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
>
> swap = _glob.swap_lru[bo->priority];
> list_move_tail(>swap, swap);
> + } else {
> + list_del_init(>swap);
> }
>
> if (bdev->funcs->del_from_lru_notify)
> --
> 2.25.1
>
> ___
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[PATCH] drm/ttm: Do not add non-system domain BO into swap list
BO would be added into swap list if it is validated into system domain.
If BO is validated again into non-system domain, say, VRAM domain. It
actually should not be in the swap list.
Signed-off-by: xinhui pan
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index a97d41f4ce3c..3a10bebb75d6 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -111,6 +111,8 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
swap = _glob.swap_lru[bo->priority];
list_move_tail(>swap, swap);
+ } else {
+ list_del_init(>swap);
}
if (bdev->funcs->del_from_lru_notify)
--
2.25.1
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[PATCH 4/4] drm/amdgpu: Reset the devices in the XGMI hive duirng probe
In passthrough configuration, hypervisior will trigger the SBR(Secondary bus
reset) to the devices
without sync to each other. This could cause device hang since for XGMI
configuration, all the devices
within the hive need to be reset at a limit time slot. This serial of patches
try to solve this issue
by co-operate with new SMU which will only do minimum house keeping to response
the SBR request but don't
do the real reset job and leave it to driver. Driver need to do the whole sw
init and minimum HW init
to bring up the SMU and trigger the reset(possibly BACO) on all the ASICs at
the same time with existing
gpu_recovery routine.
Signed-off-by: shaoyunl
Change-Id: I34e838e611b7623c7ad824704c7ce350808014fc
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 96 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 +-
4 files changed, 87 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 420ef08a51b5..ae8be6d813a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1220,6 +1220,10 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)
}
}
+ /* Don't post if we need to reset whole hive on init */
+ if (adev->gmc.xgmi.pending_reset)
+ return false;
+
if (adev->has_hw_reset) {
adev->has_hw_reset = false;
return true;
@@ -2147,6 +2151,9 @@ static int amdgpu_device_fw_loading(struct amdgpu_device
*adev)
if (adev->ip_blocks[i].version->type !=
AMD_IP_BLOCK_TYPE_PSP)
continue;
+ if (!adev->ip_blocks[i].status.sw)
+ continue;
+
/* no need to do the fw loading again if already done*/
if (adev->ip_blocks[i].status.hw == true)
break;
@@ -2287,7 +2294,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
if (adev->gmc.xgmi.num_physical_nodes > 1)
amdgpu_xgmi_add_device(adev);
- amdgpu_amdkfd_device_init(adev);
+
+ /* Don't init kfd if whole hive need to be reset during init */
+ if (!adev->gmc.xgmi.pending_reset)
+ amdgpu_amdkfd_device_init(adev);
amdgpu_fru_get_product_info(adev);
@@ -2731,6 +2741,16 @@ static int amdgpu_device_ip_suspend_phase2(struct
amdgpu_device *adev)
adev->ip_blocks[i].status.hw = false;
continue;
}
+
+ /* skip unnecessary suspend if we do not initialize them yet */
+ if (adev->gmc.xgmi.pending_reset &&
+ !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC
||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC
||
+ adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_COMMON ||
+ adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_IH)) {
+ adev->ip_blocks[i].status.hw = false;
+ continue;
+ }
/* XXX handle errors */
r = adev->ip_blocks[i].version->funcs->suspend(adev);
/* XXX handle errors */
@@ -3402,10 +3422,29 @@ int amdgpu_device_init(struct amdgpu_device *adev,
* E.g., driver was not cleanly unloaded previously, etc.
*/
if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
- r = amdgpu_asic_reset(adev);
- if (r) {
- dev_err(adev->dev, "asic reset on init failed\n");
- goto failed;
+ if (adev->gmc.xgmi.num_physical_nodes) {
+ dev_info(adev->dev, "Pending hive reset.\n");
+ adev->gmc.xgmi.pending_reset = true;
+ /* Only need to init necessary block for SMU to handle
the reset */
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.valid)
+ continue;
+ if (!(adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_GMC ||
+ adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_PSP ||
+ adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_COMMON ||
+ adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_IH ||
+ adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_SMC)) {
+ DRM_DEBUG("IP %s disabed for
hw_init.\n",
+
[PATCH 3/4] drm/amdgpu: Init the cp MQD if it's not be initialized before
The MQD might not be initialized duirng first init period if the device need to
be reset
druing probe. Driver need to proper init them in gpu recovery period
Signed-off-by: shaoyunl
Acked-by: Alex Deucher
Change-Id: Iad58a050939af2afa46d1c74a90866c47ba9efd2
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 65db88bb6cbc..bfe1aaa0418f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3696,11 +3696,18 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring
*ring)
struct amdgpu_device *adev = ring->adev;
struct v9_mqd *mqd = ring->mqd_ptr;
int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
+ struct v9_mqd *tmp_mqd;
gfx_v9_0_kiq_setting(ring);
- if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
- /* reset MQD to a clean status */
+ /* GPU could be in bad state during probe, driver trigger the reset
+* after load the SMU, in this case , the mqd is not be initialized.
+* driver need to re-init the mqd.
+* check mqd->cp_hqd_pq_control since this value should not be 0
+*/
+ tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
+ if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){
+ /* for GPU_RESET case , reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx],
sizeof(struct v9_mqd_allocation));
@@ -3736,8 +3743,15 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring
*ring)
struct amdgpu_device *adev = ring->adev;
struct v9_mqd *mqd = ring->mqd_ptr;
int mqd_idx = ring - >gfx.compute_ring[0];
+ struct v9_mqd *tmp_mqd;
- if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
+ /* Same as above kiq init, driver need to re-init the mqd if
mqd->cp_hqd_pq_control
+* is not be initialized before
+*/
+ tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
+
+ if (!tmp_mqd->cp_hqd_pq_control ||
+ (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0x;
((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0x;
--
2.17.1
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[PATCH 2/4] drm/amdgpu: Add kfd init_complete flag to check from amdgpu side
amdgpu driver may be in reset state during init which will not initialize the
kfd,
driver need to initialize the KFD after reset by check the flag
Signed-off-by: shaoyunl
Acked-by: Alex Deucher
Change-Id: Ic1684b55b27e0afd42bee8b9b431c4fb0afcec15
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 -
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index c5343a5eecbe..a876dc3af017 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -165,7 +165,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
adev->doorbell_index.last_non_cp;
}
- kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev),
_resources);
+ adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
+ adev_to_drm(adev),
_resources);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 4687ff2961e1..3182dd97840e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -80,6 +80,7 @@ struct amdgpu_amdkfd_fence {
struct amdgpu_kfd_dev {
struct kfd_dev *dev;
uint64_t vram_used;
+ bool init_complete;
};
enum kgd_engine_type {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2f9ad7ed82be..420ef08a51b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4784,9 +4784,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
skip_sched_resume:
list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
- /*unlock kfd: SRIOV would do it separately */
+ /* unlock kfd: SRIOV would do it separately */
if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
amdgpu_amdkfd_post_reset(tmp_adev);
+
+ /* kfd_post_reset will do nothing if kfd device is not
initialized,
+* need to bring up kfd here if it's not be initialized before
+*/
+ if (!adev->kfd.init_complete)
+ amdgpu_amdkfd_device_init(adev);
+
if (audio_suspended)
amdgpu_device_resume_display_audio(tmp_adev);
amdgpu_device_unlock_adev(tmp_adev);
--
2.17.1
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[PATCH 1/4] drm/amdgpu: get xgmi info at eary_init
Driver need to get XGMI info function earlier before ip_init since driver need
to check
the XGMI setting to determine how to perform reset during init
Signed-off-by: shaoyunl
Acked-by: Alex Deucher
Change-Id: Ic37276bbb6640bb4e9360220fed99494cedd3ef5
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3686e777c76c..3e6bfab5b855 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1151,6 +1151,10 @@ static int gmc_v9_0_early_init(void *handle)
adev->gmc.private_aperture_end =
adev->gmc.private_aperture_start + (4ULL << 30) - 1;
+ /* Need to get xgmi info earlier to decide the reset behavior*/
+ if (adev->gmc.xgmi.supported)
+ adev->gfxhub.funcs->get_xgmi_info(adev);
+
return 0;
}
@@ -1416,12 +1420,6 @@ static int gmc_v9_0_sw_init(void *handle)
}
adev->need_swiotlb = drm_need_swiotlb(44);
- if (adev->gmc.xgmi.supported) {
- r = adev->gfxhub.funcs->get_xgmi_info(adev);
- if (r)
- return r;
- }
-
r = gmc_v9_0_mc_init(adev);
if (r)
return r;
--
2.17.1
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Re: [PATCH] drm/amdgpu: add ih call to process until checkpoint
On 2021-02-23 4:10 p.m., Jonathan Kim wrote:
Add IH function to allow caller to process ring entries until the
checkpoint write pointer.
Suggested-by: Felix Kuehling
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 46 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 2 ++
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index dc852af4f3b7..cae50af9559d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -22,7 +22,7 @@
*/
#include
-
+#include
#include "amdgpu.h"
#include "amdgpu_ih.h"
@@ -160,6 +160,50 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
}
}
+/**
+ * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint
+ *
+ * @adev: amdgpu_device pointer
+ * @ih: ih ring to process
+ *
+ * Used to ensure ring has processed IVs up to the checkpoint write pointer.
+ */
+int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
+{
+ u32 prev_rptr, cur_rptr, checkpoint_wptr;
+
+ if (!ih->enabled || adev->shutdown)
+ return -ENODEV;
+
+ cur_rptr = READ_ONCE(ih->rptr);
+ /* Order read of current rptr with checktpoint wptr. */
+ mb();
+ checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
+
Isn't rmb() enough in this case ? If I understand correctly you just
want to confirm that
you are not reading stale checkpoint_wptr while reading fresh cur_rptr.
Andrey
+ /* allow rptr to wrap around */
+ if (cur_rptr > checkpoint_wptr) {
+ spin_begin();
+ do {
+ spin_cpu_relax();
+ prev_rptr = cur_rptr;
+ cur_rptr = READ_ONCE(ih->rptr);
+ } while (cur_rptr >= prev_rptr);
+ spin_end();
+ }
+
+ /* wait for rptr to catch up to or pass checkpoint. */
+ spin_begin();
+ do {
+ spin_cpu_relax();
+ prev_rptr = cur_rptr;
+ cur_rptr = READ_ONCE(ih->rptr);
+ } while (cur_rptr >= prev_rptr && cur_rptr < checkpoint_wptr);
+ spin_end();
+
+ return 0;
+}
+
/**
* amdgpu_ih_process - interrupt handler
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 6ed4a85fc7c3..6817f0a812d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -87,6 +87,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
amdgpu_ih_ring *ih,
void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring
*ih);
void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
unsigned int num_dw);
+int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih);
int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
struct amdgpu_ih_ring *ih,
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[PATCH] drm/amdgpu: add missing df counter disable write
Request to stop DF performance counters is missing the actual write to the
controller register.
Reported-by: Chris Freehill
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 6b4b30a8dce5..44109a6b8f44 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -568,6 +568,8 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev,
uint64_t config,
if (ret)
return ret;
+ df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
+ hi_base_addr, hi_val);
if (is_remove) {
df_v3_6_reset_perfmon_cntr(adev, config, counter_idx);
--
2.17.1
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[PATCH] drm/amdgpu: add ih call to process until checkpoint
Add IH function to allow caller to process ring entries until the
checkpoint write pointer.
Suggested-by: Felix Kuehling
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 46 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 2 ++
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index dc852af4f3b7..cae50af9559d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -22,7 +22,7 @@
*/
#include
-
+#include
#include "amdgpu.h"
#include "amdgpu_ih.h"
@@ -160,6 +160,50 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const
uint32_t *iv,
}
}
+/**
+ * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint
+ *
+ * @adev: amdgpu_device pointer
+ * @ih: ih ring to process
+ *
+ * Used to ensure ring has processed IVs up to the checkpoint write pointer.
+ */
+int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
+{
+ u32 prev_rptr, cur_rptr, checkpoint_wptr;
+
+ if (!ih->enabled || adev->shutdown)
+ return -ENODEV;
+
+ cur_rptr = READ_ONCE(ih->rptr);
+ /* Order read of current rptr with checktpoint wptr. */
+ mb();
+ checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
+
+ /* allow rptr to wrap around */
+ if (cur_rptr > checkpoint_wptr) {
+ spin_begin();
+ do {
+ spin_cpu_relax();
+ prev_rptr = cur_rptr;
+ cur_rptr = READ_ONCE(ih->rptr);
+ } while (cur_rptr >= prev_rptr);
+ spin_end();
+ }
+
+ /* wait for rptr to catch up to or pass checkpoint. */
+ spin_begin();
+ do {
+ spin_cpu_relax();
+ prev_rptr = cur_rptr;
+ cur_rptr = READ_ONCE(ih->rptr);
+ } while (cur_rptr >= prev_rptr && cur_rptr < checkpoint_wptr);
+ spin_end();
+
+ return 0;
+}
+
/**
* amdgpu_ih_process - interrupt handler
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 6ed4a85fc7c3..6817f0a812d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -87,6 +87,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
amdgpu_ih_ring *ih,
void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring
*ih);
void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
unsigned int num_dw);
+int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih);
int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
struct amdgpu_ih_ring *ih,
--
2.17.1
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Re: [PATCH 2/4] drm/amdgpu: get xgmi info at eary_init
On Tue, Feb 23, 2021 at 1:00 PM Liu, Shaoyun wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks , Alex.
> Whole four patches are needed for the XGMI reset to work normally . I try to
> describe what these patches for in the first patch. But If you don't mind
> this , I can adjust the order as suggested .
Just update the commit messages to indicate that these changes are
needed for big rework in the later patches.
Alex
>
> Thanks
> Shaoyun.liu
>
> -Original Message-
> From: Alex Deucher
> Sent: Tuesday, February 23, 2021 11:26 AM
> To: Liu, Shaoyun
> Cc: amd-gfx list
> Subject: Re: [PATCH 2/4] drm/amdgpu: get xgmi info at eary_init
>
> On Thu, Feb 18, 2021 at 8:19 PM shaoyunl wrote:
> >
> > Driver need to get XGMI info function earlier before ip_init since
> > driver need to check the XGMI setting to determine how to perform
> > reset during init
> >
> > Signed-off-by: shaoyunl
> > Change-Id: Ic37276bbb6640bb4e9360220fed99494cedd3ef5
>
> I think this patch needs to come first or patch 1 won't work. With that
> changed, this patch is:
> Acked-by: Alex Deucher
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 --
> > 1 file changed, 4 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > index 3686e777c76c..3e6bfab5b855 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -1151,6 +1151,10 @@ static int gmc_v9_0_early_init(void *handle)
> > adev->gmc.private_aperture_end =
> > adev->gmc.private_aperture_start + (4ULL << 30) - 1;
> >
> > + /* Need to get xgmi info earlier to decide the reset behavior*/
> > + if (adev->gmc.xgmi.supported)
> > + adev->gfxhub.funcs->get_xgmi_info(adev);
> > +
> > return 0;
> > }
> >
> > @@ -1416,12 +1420,6 @@ static int gmc_v9_0_sw_init(void *handle)
> > }
> > adev->need_swiotlb = drm_need_swiotlb(44);
> >
> > - if (adev->gmc.xgmi.supported) {
> > - r = adev->gfxhub.funcs->get_xgmi_info(adev);
> > - if (r)
> > - return r;
> > - }
> > -
> > r = gmc_v9_0_mc_init(adev);
> > if (r)
> > return r;
> > --
> > 2.17.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Csh
> > aoyun.liu%40amd.com%7Ceb081cfaf9c94e59521008d8d817ccee%7C3dd8961fe4884
> > e608e11a82d994e183d%7C0%7C0%7C637496944032343059%7CUnknown%7CTWFpbGZsb
> > 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C1000sdata=CrS5Nv4uCh8sFRILLGM%2FRgxpVlEEs%2Bft%2FHTdoeQyyqo%3D&
> > amp;reserved=0
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RE: [PATCH 2/4] drm/amdgpu: get xgmi info at eary_init
[AMD Official Use Only - Internal Distribution Only]
Thanks , Alex.
Whole four patches are needed for the XGMI reset to work normally . I try to
describe what these patches for in the first patch. But If you don't mind
this , I can adjust the order as suggested .
Thanks
Shaoyun.liu
-Original Message-
From: Alex Deucher
Sent: Tuesday, February 23, 2021 11:26 AM
To: Liu, Shaoyun
Cc: amd-gfx list
Subject: Re: [PATCH 2/4] drm/amdgpu: get xgmi info at eary_init
On Thu, Feb 18, 2021 at 8:19 PM shaoyunl wrote:
>
> Driver need to get XGMI info function earlier before ip_init since
> driver need to check the XGMI setting to determine how to perform
> reset during init
>
> Signed-off-by: shaoyunl
> Change-Id: Ic37276bbb6640bb4e9360220fed99494cedd3ef5
I think this patch needs to come first or patch 1 won't work. With that
changed, this patch is:
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 3686e777c76c..3e6bfab5b855 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1151,6 +1151,10 @@ static int gmc_v9_0_early_init(void *handle)
> adev->gmc.private_aperture_end =
> adev->gmc.private_aperture_start + (4ULL << 30) - 1;
>
> + /* Need to get xgmi info earlier to decide the reset behavior*/
> + if (adev->gmc.xgmi.supported)
> + adev->gfxhub.funcs->get_xgmi_info(adev);
> +
> return 0;
> }
>
> @@ -1416,12 +1420,6 @@ static int gmc_v9_0_sw_init(void *handle)
> }
> adev->need_swiotlb = drm_need_swiotlb(44);
>
> - if (adev->gmc.xgmi.supported) {
> - r = adev->gfxhub.funcs->get_xgmi_info(adev);
> - if (r)
> - return r;
> - }
> -
> r = gmc_v9_0_mc_init(adev);
> if (r)
> return r;
> --
> 2.17.1
>
> ___
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> e608e11a82d994e183d%7C0%7C0%7C637496944032343059%7CUnknown%7CTWFpbGZsb
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C1000sdata=CrS5Nv4uCh8sFRILLGM%2FRgxpVlEEs%2Bft%2FHTdoeQyyqo%3D&
> amp;reserved=0
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RE: [PATCH 1/4] drm/amdgpu: Reset the devices in the XGMI hive duirng probe
[AMD Official Use Only - Internal Distribution Only]
Comments inline ,
-Original Message-
From: Alex Deucher
Sent: Tuesday, February 23, 2021 11:47 AM
To: Liu, Shaoyun
Cc: amd-gfx list
Subject: Re: [PATCH 1/4] drm/amdgpu: Reset the devices in the XGMI hive duirng
probe
On Thu, Feb 18, 2021 at 8:19 PM shaoyunl wrote:
>
> In passthrough configuration, hypervisior will trigger the
> SBR(Secondary bus reset) to the devices without sync to each other.
> This could cause device hang since for XGMI configuration, all the
> devices within the hive need to be reset at a limit time slot. This
> serial of patches try to solve this issue by co-operate with new SMU
> which will only do minimum house keeping to response the SBR request
> but don't do the real reset job and leave it to driver. Driver need to do the
> whole sw init and minimum HW init to bring up the SMU and trigger the
> reset(possibly BACO) on all the ASICs at the same time with existing
> gpu_recovery routine.
>
> Signed-off-by: shaoyunl
> Change-Id: I34e838e611b7623c7ad824704c7ce350808014fc
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 96 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 6 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 +-
> 4 files changed, 87 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2f9ad7ed82be..9f574fd151bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1220,6 +1220,10 @@ bool amdgpu_device_need_post(struct amdgpu_device
> *adev)
> }
> }
>
> + /* Don't post if we need to reset whole hive on init */
> + if (adev->gmc.xgmi.pending_reset)
> + return false;
> +
> if (adev->has_hw_reset) {
> adev->has_hw_reset = false;
> return true;
> @@ -2147,6 +2151,9 @@ static int amdgpu_device_fw_loading(struct
> amdgpu_device *adev)
> if (adev->ip_blocks[i].version->type !=
> AMD_IP_BLOCK_TYPE_PSP)
> continue;
>
> + if (!adev->ip_blocks[i].status.sw)
> + continue;
> +
> /* no need to do the fw loading again if already
> done*/
> if (adev->ip_blocks[i].status.hw == true)
> break; @@ -2287,7 +2294,10 @@ static
> int amdgpu_device_ip_init(struct amdgpu_device *adev)
>
> if (adev->gmc.xgmi.num_physical_nodes > 1)
> amdgpu_xgmi_add_device(adev);
> - amdgpu_amdkfd_device_init(adev);
> +
> + /* Don't init kfd if whole hive need to be reset during init */
> + if (!adev->gmc.xgmi.pending_reset)
> + amdgpu_amdkfd_device_init(adev);
>
> amdgpu_fru_get_product_info(adev);
>
> @@ -2731,6 +2741,16 @@ static int amdgpu_device_ip_suspend_phase2(struct
> amdgpu_device *adev)
> adev->ip_blocks[i].status.hw = false;
> continue;
> }
> +
> + /* skip unnecessary suspend if we do not initialize them yet
> */
> + if (adev->gmc.xgmi.pending_reset &&
> + !(adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_GMC ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_SMC ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_COMMON ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_IH)) {
> + adev->ip_blocks[i].status.hw = false;
> + continue;
> + }
> /* XXX handle errors */
> r = adev->ip_blocks[i].version->funcs->suspend(adev);
> /* XXX handle errors */ @@ -3402,10 +3422,29 @@ int
> amdgpu_device_init(struct amdgpu_device *adev,
> * E.g., driver was not cleanly unloaded previously, etc.
> */
> if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
> - r = amdgpu_asic_reset(adev);
> - if (r) {
> - dev_err(adev->dev, "asic reset on init failed\n");
> - goto failed;
> + if (adev->gmc.xgmi.num_physical_nodes) {
> + dev_info(adev->dev, "Pending hive reset.\n");
> + adev->gmc.xgmi.pending_reset = true;
> + /* Only need to init necessary block for SMU to
> handle the reset */
> + for (i = 0; i < adev->num_ip_blocks; i++) {
> + if (!adev->ip_blocks[i].status.valid)
> + continue;
> + if (!(adev->ip_blocks[i].version->type ==
>
Re: [PATCH] drm/amdgpu: Remove unnecessary conversion to bool
On Mon, Feb 22, 2021 at 10:44 PM Jiapeng Chong wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:79:40-45: WARNING: conversion > to bool not needed here. > > ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:81:40-45: WARNING: conversion > to bool not needed here. > > Reported-by: Abaci Robot > Signed-off-by: Jiapeng Chong Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 6 ++ > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c > b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c > index 7b1b183..2ac4988 100644 > --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c > @@ -74,10 +74,8 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev, > case CHIP_SIENNA_CICHLID: > case CHIP_NAVY_FLOUNDER: > case CHIP_DIMGREY_CAVEFISH: > - athub_v2_1_update_medium_grain_clock_gating(adev, > - state == AMD_CG_STATE_GATE ? true : false); > - athub_v2_1_update_medium_grain_light_sleep(adev, > - state == AMD_CG_STATE_GATE ? true : false); > + athub_v2_1_update_medium_grain_clock_gating(adev, state == > AMD_CG_STATE_GATE); > + athub_v2_1_update_medium_grain_light_sleep(adev, state == > AMD_CG_STATE_GATE); > break; > default: > break; > -- > 1.8.3.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/display: initialize the variable 'i'
On Tuesday, February 23rd, 2021 at 6:42 PM, Alex Deucher wrote: > yeah, fdo ran out of disk space so I moved to gitlab: > > https://gitlab.freedesktop.org/agd5f/linux/-/commits/drm-next Ah, thanks for the info, my bad! ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/3] drm/ttm: constify static vm_operations_structs
On Wed, Feb 10, 2021 at 8:14 AM Daniel Vetter wrote: > > On Wed, Feb 10, 2021 at 08:45:56AM +0100, Christian König wrote: > > Reviewed-by: Christian König for the series. > > Smash it into -misc? @Christian Koenig did these ever land? I don't see them in drm-misc. Alex > -Daniel > > > > > Am 10.02.21 um 00:48 schrieb Rikard Falkeborn: > > > Constify a few static vm_operations_struct that are never modified. Their > > > only usage is to assign their address to the vm_ops field in the > > > vm_area_struct, which is a pointer to const vm_operations_struct. Make > > > them > > > const to allow the compiler to put them in read-only memory. > > > > > > With this series applied, all static struct vm_operations_struct in the > > > kernel tree are const. > > > > > > Rikard Falkeborn (3): > > >drm/amdgpu/ttm: constify static vm_operations_struct > > >drm/radeon/ttm: constify static vm_operations_struct > > >drm/nouveau/ttm: constify static vm_operations_struct > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- > > > drivers/gpu/drm/nouveau/nouveau_ttm.c | 2 +- > > > drivers/gpu/drm/radeon/radeon_ttm.c | 2 +- > > > 3 files changed, 3 insertions(+), 3 deletions(-) > > > > > > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/4] drm/amdgpu: Reset the devices in the XGMI hive duirng probe
On Thu, Feb 18, 2021 at 8:19 PM shaoyunl wrote:
>
> In passthrough configuration, hypervisior will trigger the SBR(Secondary bus
> reset) to the devices
> without sync to each other. This could cause device hang since for XGMI
> configuration, all the devices
> within the hive need to be reset at a limit time slot. This serial of patches
> try to solve this issue
> by co-operate with new SMU which will only do minimum house keeping to
> response the SBR request but don't
> do the real reset job and leave it to driver. Driver need to do the whole sw
> init and minimum HW init
> to bring up the SMU and trigger the reset(possibly BACO) on all the ASICs at
> the same time with existing
> gpu_recovery routine.
>
> Signed-off-by: shaoyunl
> Change-Id: I34e838e611b7623c7ad824704c7ce350808014fc
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 96 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 6 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 +-
> 4 files changed, 87 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2f9ad7ed82be..9f574fd151bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1220,6 +1220,10 @@ bool amdgpu_device_need_post(struct amdgpu_device
> *adev)
> }
> }
>
> + /* Don't post if we need to reset whole hive on init */
> + if (adev->gmc.xgmi.pending_reset)
> + return false;
> +
> if (adev->has_hw_reset) {
> adev->has_hw_reset = false;
> return true;
> @@ -2147,6 +2151,9 @@ static int amdgpu_device_fw_loading(struct
> amdgpu_device *adev)
> if (adev->ip_blocks[i].version->type !=
> AMD_IP_BLOCK_TYPE_PSP)
> continue;
>
> + if (!adev->ip_blocks[i].status.sw)
> + continue;
> +
> /* no need to do the fw loading again if already
> done*/
> if (adev->ip_blocks[i].status.hw == true)
> break;
> @@ -2287,7 +2294,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device
> *adev)
>
> if (adev->gmc.xgmi.num_physical_nodes > 1)
> amdgpu_xgmi_add_device(adev);
> - amdgpu_amdkfd_device_init(adev);
> +
> + /* Don't init kfd if whole hive need to be reset during init */
> + if (!adev->gmc.xgmi.pending_reset)
> + amdgpu_amdkfd_device_init(adev);
>
> amdgpu_fru_get_product_info(adev);
>
> @@ -2731,6 +2741,16 @@ static int amdgpu_device_ip_suspend_phase2(struct
> amdgpu_device *adev)
> adev->ip_blocks[i].status.hw = false;
> continue;
> }
> +
> + /* skip unnecessary suspend if we do not initialize them yet
> */
> + if (adev->gmc.xgmi.pending_reset &&
> + !(adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_GMC ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_SMC ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_COMMON ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_IH)) {
> + adev->ip_blocks[i].status.hw = false;
> + continue;
> + }
> /* XXX handle errors */
> r = adev->ip_blocks[i].version->funcs->suspend(adev);
> /* XXX handle errors */
> @@ -3402,10 +3422,29 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> * E.g., driver was not cleanly unloaded previously, etc.
> */
> if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
> - r = amdgpu_asic_reset(adev);
> - if (r) {
> - dev_err(adev->dev, "asic reset on init failed\n");
> - goto failed;
> + if (adev->gmc.xgmi.num_physical_nodes) {
> + dev_info(adev->dev, "Pending hive reset.\n");
> + adev->gmc.xgmi.pending_reset = true;
> + /* Only need to init necessary block for SMU to
> handle the reset */
> + for (i = 0; i < adev->num_ip_blocks; i++) {
> + if (!adev->ip_blocks[i].status.valid)
> + continue;
> + if (!(adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_GMC ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_PSP ||
> + adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_COMMON ||
> +
Re: [PATCH 4/4] drm/amdgpu: Init the cp MQD if it's not be initialized before
On Thu, Feb 18, 2021 at 8:20 PM shaoyunl wrote:
>
> The MQD might not be initialized duirng first init period if the device need
> to be reset
> druing probe. Driver need to proper init them in gpu recovery period
>
> Signed-off-by: shaoyunl
> Change-Id: Iad58a050939af2afa46d1c74a90866c47ba9efd2
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 +---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 65db88bb6cbc..8fc2fd518a1b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3696,11 +3696,18 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring
> *ring)
> struct amdgpu_device *adev = ring->adev;
> struct v9_mqd *mqd = ring->mqd_ptr;
> int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
> + struct v9_mqd *tmp_mqd;
>
> gfx_v9_0_kiq_setting(ring);
>
> - if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
> - /* reset MQD to a clean status */
> + /* GPU could be in bad state during probe, driver trigger the reset
> +* after load the SMU, in this case , the mqd is not be initialized.
> +* driver need to re-init the mqd in this case.
> +* check mqd->cp_hqd_pq_control since this value should not be 0
> +*/
> + tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
> + if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){
> + /* for GPU_RESET case , reset MQD to a clean status */
> if (adev->gfx.mec.mqd_backup[mqd_idx])
> memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx],
> sizeof(struct v9_mqd_allocation));
>
> @@ -3736,8 +3743,15 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring
> *ring)
> struct amdgpu_device *adev = ring->adev;
> struct v9_mqd *mqd = ring->mqd_ptr;
> int mqd_idx = ring - >gfx.compute_ring[0];
> + struct v9_mqd *tmp_mqd;
>
> - if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
> + /* Samw as above kiq init, driver need to re-init the mqd if
> mqd->cp_hqd_pq_control
Samw -> Same
I think this also needs to come before patch 1. With these comments fixed:
Acked-by: Alex Deucher
> +* is not be initialized before
> +*/
> + tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
> +
> + if (!tmp_mqd->cp_hqd_pq_control ||
> + (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
> memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
> ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask =
> 0x;
> ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask =
> 0x;
> --
> 2.17.1
>
> ___
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Re: [PATCH 3/4] drm/amdgpu: Add kfd init_complete flag to check from amdgpu side
On Thu, Feb 18, 2021 at 8:19 PM shaoyunl wrote:
>
> amdgpu driver may in reset state duirng init which will not initialize the
> kfd,
grammer "may be in"
typo duirng -> during
> driver need to initialize the KFD after reset by check the flag
>
> Signed-off-by: shaoyunl
> Change-Id: Ic1684b55b27e0afd42bee8b9b431c4fb0afcec15
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
> 3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index c5343a5eecbe..a876dc3af017 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -165,7 +165,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
> adev->doorbell_index.last_non_cp;
> }
>
> - kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev),
> _resources);
> + adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
> + adev_to_drm(adev),
> _resources);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 4687ff2961e1..3182dd97840e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -80,6 +80,7 @@ struct amdgpu_amdkfd_fence {
> struct amdgpu_kfd_dev {
> struct kfd_dev *dev;
> uint64_t vram_used;
> + bool init_complete;
> };
>
> enum kgd_engine_type {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9f574fd151bc..e898fce96f75 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4841,6 +4841,13 @@ int amdgpu_device_gpu_recover(struct amdgpu_device
> *adev,
> /*unlock kfd: SRIOV would do it separately */
> if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
> amdgpu_amdkfd_post_reset(tmp_adev);
> +
> + /*kfd_post_reset will do nothing if kfd device is not
> initialized,
> +*need to bring up kfd here if it's not be initialized before
> +*/
Fix up the comment here. Need a space between * and the comment.
E.g., /* kfd_post_reset ...
Also, I think this patch also needs to come before patch 1.
With those comments addressed:
Acked-by: Alex Deucher
> + if (!adev->kfd.init_complete)
> + amdgpu_amdkfd_device_init(adev);
> +
> if (audio_suspended)
> amdgpu_device_resume_display_audio(tmp_adev);
> amdgpu_device_unlock_adev(tmp_adev);
> --
> 2.17.1
>
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Re: [PATCH 2/4] drm/amdgpu: get xgmi info at eary_init
On Thu, Feb 18, 2021 at 8:19 PM shaoyunl wrote:
>
> Driver need to get XGMI info function earlier before ip_init since driver
> need to check
> the XGMI setting to determine how to perform reset during init
>
> Signed-off-by: shaoyunl
> Change-Id: Ic37276bbb6640bb4e9360220fed99494cedd3ef5
I think this patch needs to come first or patch 1 won't work. With
that changed, this patch is:
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 3686e777c76c..3e6bfab5b855 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1151,6 +1151,10 @@ static int gmc_v9_0_early_init(void *handle)
> adev->gmc.private_aperture_end =
> adev->gmc.private_aperture_start + (4ULL << 30) - 1;
>
> + /* Need to get xgmi info earlier to decide the reset behavior*/
> + if (adev->gmc.xgmi.supported)
> + adev->gfxhub.funcs->get_xgmi_info(adev);
> +
> return 0;
> }
>
> @@ -1416,12 +1420,6 @@ static int gmc_v9_0_sw_init(void *handle)
> }
> adev->need_swiotlb = drm_need_swiotlb(44);
>
> - if (adev->gmc.xgmi.supported) {
> - r = adev->gfxhub.funcs->get_xgmi_info(adev);
> - if (r)
> - return r;
> - }
> -
> r = gmc_v9_0_mc_init(adev);
> if (r)
> return r;
> --
> 2.17.1
>
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Re: [PATCH] drm/amd/display: Remove unnecessary conversion to bool
This was already fixed by a patch from Yang Li . Alex On Tue, Feb 23, 2021 at 1:13 AM Jiapeng Chong wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8260:16-21: WARNING: > conversion to bool not needed here. > > Reported-by: Abaci Robot > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 94cd5dd..323473d 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -8253,8 +8253,7 @@ static void amdgpu_dm_atomic_commit_tail(struct > drm_atomic_state *state) > hdcp_update_display( > adev->dm.hdcp_workqueue, > aconnector->dc_link->link_index, aconnector, > new_con_state->hdcp_content_type, > - new_con_state->content_protection == > DRM_MODE_CONTENT_PROTECTION_DESIRED ? true > - >: false); > + new_con_state->content_protection == > DRM_MODE_CONTENT_PROTECTION_DESIRED); > } > #endif > > -- > 1.8.3.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Enable ASSR in Linux DM
Applied to amd-staging-drm-next.
Thanks
On 02/23, Rodrigo Siqueira wrote:
> On 02/23, Stylon Wang wrote:
> > ASSR implementation was already in DC and DM guarded by
> > CONFIG_DRM_AMD_DC_HDCP. This patch enables ASSR if display
> > declares such support in DPCD.
> >
> > Signed-off-by: Stylon Wang
> > ---
> > drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index c1391bfb7a9b..099f43709060 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -1669,6 +1669,22 @@ bool perform_link_training_with_retries(
> > msleep(delay_dp_power_up_in_ms);
> > }
> >
> > +#ifdef CONFIG_DRM_AMD_DC_HDCP
> > + if (panel_mode == DP_PANEL_MODE_EDP) {
> > + struct cp_psp *cp_psp = >ctx->cp_psp;
> > +
> > + if (cp_psp && cp_psp->funcs.enable_assr) {
> > + if (!cp_psp->funcs.enable_assr(cp_psp->handle,
> > link)) {
> > + /* since eDP implies ASSR on, change
> > panel
> > +* mode to disable ASSR
> > +*/
> > + panel_mode = DP_PANEL_MODE_DEFAULT;
> > + }
> > + } else
> > + panel_mode = DP_PANEL_MODE_DEFAULT;
> > + }
> > +#endif
> > +
> > dp_set_panel_mode(link, panel_mode);
> >
> > if (link->aux_access_disabled) {
> > --
> > 2.25.1
> >
>
> Reviewed-by: Rodrigo Siqueira
>
> --
> Rodrigo Siqueira
> https://siqueira.tech
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Re: [PATCH] drm/amdgpu/display: fix compilation when CONFIG_DRM_AMD_DC_DCN is not set
On 2021-02-23 10:22 a.m., Alex Deucher wrote:
Missing some CONFIG_DRM_AMD_DC_DCN ifdefs.
Fixes: 9d99a805a9a0 ("drm/amd/display: Fix system hang after multiple hotplugs")
Signed-off-by: Alex Deucher
Cc: Stephen Rothwell
Cc: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7a393eeae4b1..22443e696567 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5457,12 +5457,14 @@ static inline int dm_set_vblank(struct drm_crtc *crtc,
bool enable)
if (amdgpu_in_reset(adev))
return 0;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
spin_lock_irqsave(>vblank_lock, flags);
dm->vblank_workqueue->dm = dm;
dm->vblank_workqueue->otg_inst = acrtc->otg_inst;
dm->vblank_workqueue->enable = enable;
spin_unlock_irqrestore(>vblank_lock, flags);
schedule_work(>vblank_workqueue->mall_work);
+#endif
return 0;
}
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[PATCH] drm/amdgpu/display: fix compilation when CONFIG_DRM_AMD_DC_DCN is not set
Missing some CONFIG_DRM_AMD_DC_DCN ifdefs.
Fixes: 9d99a805a9a0 ("drm/amd/display: Fix system hang after multiple hotplugs")
Signed-off-by: Alex Deucher
Cc: Stephen Rothwell
Cc: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7a393eeae4b1..22443e696567 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5457,12 +5457,14 @@ static inline int dm_set_vblank(struct drm_crtc *crtc,
bool enable)
if (amdgpu_in_reset(adev))
return 0;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
spin_lock_irqsave(>vblank_lock, flags);
dm->vblank_workqueue->dm = dm;
dm->vblank_workqueue->otg_inst = acrtc->otg_inst;
dm->vblank_workqueue->enable = enable;
spin_unlock_irqrestore(>vblank_lock, flags);
schedule_work(>vblank_workqueue->mall_work);
+#endif
return 0;
}
--
2.29.2
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[PATCH] drm/amd/display: Remove unnecessary conversion to bool
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8260:16-21: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 94cd5dd..323473d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8253,8 +8253,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) hdcp_update_display( adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, new_con_state->hdcp_content_type, - new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true - : false); + new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED); } #endif -- 1.8.3.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Remove unnecessary conversion to bool
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:79:40-45: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:81:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c index 7b1b183..2ac4988 100644 --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c @@ -74,10 +74,8 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev, case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_DIMGREY_CAVEFISH: - athub_v2_1_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); - athub_v2_1_update_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); + athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE); break; default: break; -- 1.8.3.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [Intel-gfx] [PATCH 19/30] drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay()
On Fri, Feb 19, 2021 at 04:53:15PM -0500, Lyude Paul wrote:
> So that we can start using drm_dbg_*() in
> drm_dp_link_train_clock_recovery_delay().
>
> Signed-off-by: Lyude Paul
I wonder if we could have a drm_dp so we encapsulate both aux and dpcd
related information...
But this one already solves the issue...
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
> drivers/gpu/drm/drm_dp_helper.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +-
> drivers/gpu/drm/msm/edp/edp_ctrl.c| 2 +-
> drivers/gpu/drm/radeon/atombios_dp.c | 2 +-
> drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
> include/drm/drm_dp_helper.h | 4 +++-
> 8 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> index 6d35da65e09f..4468f9d6b4dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> @@ -611,7 +611,7 @@ amdgpu_atombios_dp_link_train_cr(struct
> amdgpu_atombios_dp_link_train_info *dp_i
> dp_info->tries = 0;
> voltage = 0xff;
> while (1) {
> - drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
> + drm_dp_link_train_clock_recovery_delay(dp_info->aux,
> dp_info->dpcd);
>
> if (drm_dp_dpcd_read_link_status(dp_info->aux,
>dp_info->link_status) <= 0) {
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 194e0c273809..ce08eb3bface 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -132,7 +132,8 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8
> link_status[DP_LINK_STATUS_SIZ
> }
> EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
>
> -void drm_dp_link_train_clock_recovery_delay(const u8
> dpcd[DP_RECEIVER_CAP_SIZE])
> +void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
>DP_TRAINING_AUX_RD_MASK;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 892d7db7d94f..222073d46bdb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -441,7 +441,7 @@ static void
> intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_d
> enum drm_dp_phy dp_phy)
> {
> if (dp_phy == DP_PHY_DPRX)
> - drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
> + drm_dp_link_train_clock_recovery_delay(_dp->aux,
> intel_dp->dpcd);
> else
> drm_dp_lttpr_link_train_clock_recovery_delay();
> }
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index 36b39c381b3f..2501a6b326a3 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -1103,7 +1103,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private
> *ctrl,
> tries = 0;
> old_v_level = ctrl->link->phy_params.v_level;
> for (tries = 0; tries < maximum_retries; tries++) {
> - drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd);
> + drm_dp_link_train_clock_recovery_delay(ctrl->aux,
> ctrl->panel->dpcd);
>
> ret = dp_ctrl_read_link_status(ctrl, link_status);
> if (ret)
> diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c
> b/drivers/gpu/drm/msm/edp/edp_ctrl.c
> index 57af3d8b6699..6501598448b4 100644
> --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c
> +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c
> @@ -608,7 +608,7 @@ static int edp_start_link_train_1(struct edp_ctrl *ctrl)
> tries = 0;
> old_v_level = ctrl->v_level;
> while (1) {
> - drm_dp_link_train_clock_recovery_delay(ctrl->dpcd);
> + drm_dp_link_train_clock_recovery_delay(ctrl->drm_aux,
> ctrl->dpcd);
>
> rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status);
> if (rlen < DP_LINK_STATUS_SIZE) {
> diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
> b/drivers/gpu/drm/radeon/atombios_dp.c
> index c50c504bad50..299b9d8da376 100644
> --- a/drivers/gpu/drm/radeon/atombios_dp.c
> +++ b/drivers/gpu/drm/radeon/atombios_dp.c
> @@ -680,7 +680,7 @@ static int radeon_dp_link_train_cr(struct
> radeon_dp_link_train_info *dp_info)
> dp_info->tries = 0;
> voltage = 0xff;
> while (1) {
> - drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
Re: [PATCH] drm/amd/display: Enable ASSR in Linux DM
On 02/23, Stylon Wang wrote:
> ASSR implementation was already in DC and DM guarded by
> CONFIG_DRM_AMD_DC_HDCP. This patch enables ASSR if display
> declares such support in DPCD.
>
> Signed-off-by: Stylon Wang
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index c1391bfb7a9b..099f43709060 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -1669,6 +1669,22 @@ bool perform_link_training_with_retries(
> msleep(delay_dp_power_up_in_ms);
> }
>
> +#ifdef CONFIG_DRM_AMD_DC_HDCP
> + if (panel_mode == DP_PANEL_MODE_EDP) {
> + struct cp_psp *cp_psp = >ctx->cp_psp;
> +
> + if (cp_psp && cp_psp->funcs.enable_assr) {
> + if (!cp_psp->funcs.enable_assr(cp_psp->handle,
> link)) {
> + /* since eDP implies ASSR on, change
> panel
> + * mode to disable ASSR
> + */
> + panel_mode = DP_PANEL_MODE_DEFAULT;
> + }
> + } else
> + panel_mode = DP_PANEL_MODE_DEFAULT;
> + }
> +#endif
> +
> dp_set_panel_mode(link, panel_mode);
>
> if (link->aux_access_disabled) {
> --
> 2.25.1
>
Reviewed-by: Rodrigo Siqueira
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Re: [PATCH 1/2] drm/amd/pm: correct gpu metrics related data structures
This is why I advocated for the sysfs output to be either standard packed
or serialized. It was a hack as it is anyways.
On Mon, Feb 22, 2021 at 4:46 PM Alex Deucher wrote:
> On Sun, Feb 21, 2021 at 11:03 PM Evan Quan wrote:
> >
> > To make sure they are naturally aligned.
> >
> > Change-Id: I496a5b79158bdbd2e17f179098939e050b2ad489
> > Signed-off-by: Evan Quan
>
> Won't this break existing apps that query this info? We need to make
> sure umr and rocm-smi can handle this.
>
> Alex
>
>
> > ---
> > drivers/gpu/drm/amd/include/kgd_pp_interface.h| 11 ++-
> > drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 4 ++--
> > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 8
> > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 8
> > drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 8
> > 5 files changed, 20 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > index 828513412e20..3a8f64e1a10c 100644
> > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > @@ -332,9 +332,9 @@ struct amd_pm_funcs {
> > };
> >
> > struct metrics_table_header {
> > - uint16_tstructure_size;
> > - uint8_t format_revision;
> > - uint8_t content_revision;
> > + uint32_tstructure_size;
> > + uint16_tformat_revision;
> > + uint16_tcontent_revision;
> > };
> >
> > struct gpu_metrics_v1_0 {
> > @@ -385,8 +385,9 @@ struct gpu_metrics_v1_0 {
> > uint16_tcurrent_fan_speed;
> >
> > /* Link width/speed */
> > - uint8_t pcie_link_width;
> > - uint8_t pcie_link_speed; // in 0.1 GT/s
> > + uint16_tpcie_link_width;
> > + uint16_tpcie_link_speed; // in 0.1 GT/s
> > + uint8_t padding[2];
> > };
> >
> > struct gpu_metrics_v2_0 {
> > diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > index 50dd1529b994..f4e7a330f67f 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > @@ -284,11 +284,11 @@ int smu_v11_0_get_dpm_level_range(struct
> smu_context *smu,
> >
> > int smu_v11_0_get_current_pcie_link_width_level(struct smu_context
> *smu);
> >
> > -int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
> > +uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
> >
> > int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context
> *smu);
> >
> > -int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
> > +uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
> >
> > int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
> > bool enablement);
> > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> > index c0753029a8e2..95e905d8418d 100644
> > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> > @@ -52,8 +52,8 @@
> >
> > #define LINK_WIDTH_MAX 6
> > #define LINK_SPEED_MAX 3
> > -static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
> > -static int link_speed[] = {25, 50, 80, 160};
> > +static uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
> > +static uint16_t link_speed[] = {25, 50, 80, 160};
> >
> > static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
> > enum pp_clock_type type, uint32_t mask);
> > @@ -2117,7 +2117,7 @@ static int
> vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
> > >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
> > }
> >
> > -static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
> > +static uint16_t vega12_get_current_pcie_link_width(struct pp_hwmgr
> *hwmgr)
> > {
> > uint32_t width_level;
> >
> > @@ -2137,7 +2137,7 @@ static int
> vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
> > >>
> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
> > }
> >
> > -static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
> > +static uint16_t vega12_get_current_pcie_link_speed(struct pp_hwmgr
> *hwmgr)
> > {
> > uint32_t speed_level;
> >
> > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> > index 87811b005b85..3d462405b572 100644
> > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> > +++
[PATCH] drm/amd/display: Enable ASSR in Linux DM
ASSR implementation was already in DC and DM guarded by
CONFIG_DRM_AMD_DC_HDCP. This patch enables ASSR if display
declares such support in DPCD.
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index c1391bfb7a9b..099f43709060 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1669,6 +1669,22 @@ bool perform_link_training_with_retries(
msleep(delay_dp_power_up_in_ms);
}
+#ifdef CONFIG_DRM_AMD_DC_HDCP
+ if (panel_mode == DP_PANEL_MODE_EDP) {
+ struct cp_psp *cp_psp = >ctx->cp_psp;
+
+ if (cp_psp && cp_psp->funcs.enable_assr) {
+ if (!cp_psp->funcs.enable_assr(cp_psp->handle,
link)) {
+ /* since eDP implies ASSR on, change
panel
+* mode to disable ASSR
+*/
+ panel_mode = DP_PANEL_MODE_DEFAULT;
+ }
+ } else
+ panel_mode = DP_PANEL_MODE_DEFAULT;
+ }
+#endif
+
dp_set_panel_mode(link, panel_mode);
if (link->aux_access_disabled) {
--
2.25.1
___
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